From eee2bec671f96686c8a301ff69d40a8026430f15 Mon Sep 17 00:00:00 2001 From: Marcel Date: Sun, 9 Jun 2019 03:06:42 +0200 Subject: [PATCH] add Ozma Wars --- .../Boothill_MiST/README.txt | 26 + .../Boothill_MiST/SpaceWalk.qpf | 30 + .../Boothill_MiST/SpaceWalk.qsf | 177 ++ .../Midway8080v2_MiST/Boothill_MiST/clean.bat | 15 + .../Boothill_MiST/rtl/SpaceWalk_mist.sv | 193 ++ .../Boothill_MiST/rtl/T80/T80.vhd | 1080 +++++++++ .../Boothill_MiST/rtl/T80/T8080se.vhd | 194 ++ .../Boothill_MiST/rtl/T80/T80_ALU.vhd | 361 +++ .../Boothill_MiST/rtl/T80/T80_MCode.vhd | 1944 +++++++++++++++++ .../Boothill_MiST/rtl/T80/T80_Pack.vhd | 217 ++ .../Boothill_MiST/rtl/T80/T80_Reg.vhd | 114 + .../Boothill_MiST/rtl/build_id.tcl | 35 + .../Boothill_MiST/rtl/dac.vhd | 48 + .../Boothill_MiST/rtl/invaders.vhd | 273 +++ .../Boothill_MiST/rtl/invaders_audio.vhd | 496 +++++ .../Boothill_MiST/rtl/invaders_memory.sv | 66 + .../Boothill_MiST/rtl/invaders_video.vhd | 127 ++ .../Boothill_MiST/rtl/mw8080.vhd | 336 +++ .../Boothill_MiST/rtl/pll.ppf | 10 + .../Boothill_MiST/rtl/pll.qip | 4 + .../Boothill_MiST/rtl/pll.vhd | 382 ++++ .../Boothill_MiST/rtl/roms/rome.cpu | Bin 0 -> 2048 bytes .../Boothill_MiST/rtl/roms/rome.vhd | 150 ++ .../Boothill_MiST/rtl/roms/romf.cpu | Bin 0 -> 2048 bytes .../Boothill_MiST/rtl/roms/romf.vhd | 150 ++ .../Boothill_MiST/rtl/roms/romg.cpu | Bin 0 -> 2048 bytes .../Boothill_MiST/rtl/roms/romg.vhd | 150 ++ .../Boothill_MiST/rtl/roms/romh.cpu | Bin 0 -> 2048 bytes .../Boothill_MiST/rtl/roms/romh.vhd | 150 ++ .../Boothill_MiST/rtl/spram.vhd | 55 + .../Boothill_MiST/rtl/sprom.vhd | 82 + .../Ozma Wars_MiST/OzmaWars.qpf | 30 + .../Ozma Wars_MiST/OzmaWars.qsf | 180 ++ .../Ozma Wars_MiST/README.txt | 27 + .../Ozma Wars_MiST/Release/OzmaWars.rbf | Bin 0 -> 250660 bytes .../Ozma Wars_MiST/clean.bat | 15 + .../Ozma Wars_MiST/rtl/OzmaWars_memory.sv | 80 + .../Ozma Wars_MiST/rtl/OzmaWars_mist.sv | 209 ++ .../Ozma Wars_MiST/rtl/OzmaWars_overlay.vhd | 126 ++ .../Ozma Wars_MiST/rtl/T80/T80.vhd | 1080 +++++++++ .../Ozma Wars_MiST/rtl/T80/T8080se.vhd | 194 ++ .../Ozma Wars_MiST/rtl/T80/T80_ALU.vhd | 361 +++ .../Ozma Wars_MiST/rtl/T80/T80_MCode.vhd | 1944 +++++++++++++++++ .../Ozma Wars_MiST/rtl/T80/T80_Pack.vhd | 217 ++ .../Ozma Wars_MiST/rtl/T80/T80_Reg.vhd | 114 + .../Ozma Wars_MiST/rtl/build_id.tcl | 35 + .../Ozma Wars_MiST/rtl/dac.vhd | 48 + .../Ozma Wars_MiST/rtl/invaders.vhd | 273 +++ .../Ozma Wars_MiST/rtl/invaders_audio.vhd | 496 +++++ .../Ozma Wars_MiST/rtl/mw8080.vhd | 336 +++ .../Ozma Wars_MiST/rtl/pll.qip | 4 + .../Ozma Wars_MiST/rtl/pll.vhd | 382 ++++ .../Ozma Wars_MiST/rtl/roms/mw01.vhd | 150 ++ .../Ozma Wars_MiST/rtl/roms/mw02.vhd | 150 ++ .../Ozma Wars_MiST/rtl/roms/mw03.vhd | 150 ++ .../Ozma Wars_MiST/rtl/roms/mw04.vhd | 150 ++ .../Ozma Wars_MiST/rtl/roms/mw05.vhd | 150 ++ .../Ozma Wars_MiST/rtl/roms/mw06.vhd | 150 ++ .../Ozma Wars_MiST/rtl/spram.vhd | 55 + .../Ozma Wars_MiST/rtl/sprom.vhd | 82 + .../SpaceWalk_MiST/rtl/invaders.vhd | 46 +- 61 files changed, 14076 insertions(+), 23 deletions(-) create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/README.txt create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/SpaceWalk.qpf create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/SpaceWalk.qsf create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/clean.bat create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/SpaceWalk_mist.sv create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/T80/T80.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/T80/T8080se.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/T80/T80_ALU.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/T80/T80_MCode.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/T80/T80_Pack.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/T80/T80_Reg.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/build_id.tcl create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/dac.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/invaders.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/invaders_audio.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/invaders_memory.sv create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/invaders_video.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/mw8080.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/pll.ppf create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/pll.qip create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/pll.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/roms/rome.cpu create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/roms/rome.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/roms/romf.cpu create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/roms/romf.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/roms/romg.cpu create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/roms/romg.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/roms/romh.cpu create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/roms/romh.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/spram.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/sprom.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/OzmaWars.qpf create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/OzmaWars.qsf create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/README.txt create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/Release/OzmaWars.rbf create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/clean.bat create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/OzmaWars_memory.sv create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/OzmaWars_mist.sv create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/OzmaWars_overlay.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/T80/T80.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/T80/T8080se.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/T80/T80_ALU.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/T80/T80_MCode.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/T80/T80_Pack.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/T80/T80_Reg.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/build_id.tcl create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/dac.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/invaders.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/invaders_audio.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/mw8080.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/pll.qip create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/pll.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/roms/mw01.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/roms/mw02.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/roms/mw03.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/roms/mw04.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/roms/mw05.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/roms/mw06.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/spram.vhd create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/sprom.vhd diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/README.txt b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/README.txt new file mode 100644 index 00000000..f5cc3629 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/README.txt @@ -0,0 +1,26 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Booth Hill port to MiST by Gehstock +-- 05 June 2019 +-- +--------------------------------------------------------------------------------- +-- +-- Midway 8080 Hardware +-- Audio based on work by Paul Walsh. +-- Audio and scan converter by MikeJ. +--------------------------------------------------------------------------------- +-- +-- +-- Keyboard inputs : +-- +-- F1 : Start +-- SPACE : Fire +-- RIGHT/LEFT : Movement +-- +-- Joystick support. +-- +-- +--------------------------------------------------------------------------------- + +Work in Progress + diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/SpaceWalk.qpf b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/SpaceWalk.qpf new file mode 100644 index 00000000..31bfde3e --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/SpaceWalk.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition +# Date created = 16:15:41 June 05, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "16:15:41 June 05, 2019" + +# Revisions + +PROJECT_REVISION = "SpaceWalk" diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/SpaceWalk.qsf b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/SpaceWalk.qsf new file mode 100644 index 00000000..6dd8a68c --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/SpaceWalk.qsf @@ -0,0 +1,177 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition +# Date created = 13:13:10 June 05, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Invaders_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39 NOVEMBER 20, 2017" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/SpaceWalk_mist.sv +set_global_assignment -name VHDL_FILE rtl/invaders.vhd +set_global_assignment -name VHDL_FILE rtl/mw8080.vhd +set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/invaders_memory.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/sprom.vhd +set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd +set_global_assignment -name VHDL_FILE rtl/pll.vhd +set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY SpaceWalk_mist +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# EDA Netlist Writer Assignments +# ============================== +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" + +# Assembler Assignments +# ===================== +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# start EDA_TOOL_SETTINGS(eda_simulation) +# --------------------------------------- + + # EDA Netlist Writer Assignments + # ============================== + set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation + +# end EDA_TOOL_SETTINGS(eda_simulation) +# ------------------------------------- + +# --------------------------- +# start ENTITY(Invaders_mist) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Invaders_mist) +# ------------------------- +set_global_assignment -name QIP_FILE "D:/Github/Mist_FPGA/common/mist/mist.qip" +set_global_assignment -name VHDL_FILE rtl/roms/romh.vhd +set_global_assignment -name VHDL_FILE rtl/roms/romg.vhd +set_global_assignment -name VHDL_FILE rtl/roms/romf.vhd +set_global_assignment -name VHDL_FILE rtl/roms/rome.vhd +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/clean.bat b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/clean.bat new file mode 100644 index 00000000..83fb0c47 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/clean.bat @@ -0,0 +1,15 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +del PLLJ_PLLSPE_INFO.txt +del *.qws +del *.ppf +del *.qip +del *.ddb +pause diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/SpaceWalk_mist.sv b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/SpaceWalk_mist.sv new file mode 100644 index 00000000..31078e3d --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/SpaceWalk_mist.sv @@ -0,0 +1,193 @@ +module SpaceWalk_mist( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Boothill;;", + "O34,Scanlines,Off,25%,50%,75%;", + "T6,Reset;", + "V,v1.20.",`BUILD_DATE +}; + +assign LED = 1; +assign AUDIO_R = AUDIO_L; + + +wire clk_sys, clk_mist; +wire pll_locked; +pll pll +( + .inclk0(CLOCK_27), + .areset(), + .c0(clk_sys), + .c1(clk_mist) +); + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] kbjoy; +wire [7:0] joystick_0,joystick_1; +wire scandoublerD; +wire ypbpr; +wire key_pressed; +wire [7:0] key_code; +wire key_strobe; +wire [7:0] audio; +wire hsync,vsync; +wire hs, vs; +wire r,g,b; + +wire [15:0]RAB; +wire [15:0]AD; +wire [7:0]RDB; +wire [7:0]RWD; +wire [7:0]IB; +wire [5:0]SoundCtrl3; +wire [5:0]SoundCtrl5; +wire Rst_n_s; +wire RWE_n; +wire Video; + +invaderst invaderst( + .Rst_n(~(status[0] | status[6] | buttons[1])), + .Clk(clk_sys), + .ENA(), + .Coin(btn_coin), + .Sel1Player(~btn_one_player), + .Sel2Player(~btn_two_players), + .Fire(~m_fire), + .MoveLeft(~m_left), + .MoveRight(~m_right), + .MoveUp(~m_up), + .MoveDown(~m_down), + .RDB(RDB), + .IB(IB), + .RWD(RWD), + .RAB(RAB), + .AD(AD), + .SoundCtrl3(SoundCtrl3), + .SoundCtrl5(SoundCtrl5), + .Rst_n_s(Rst_n_s), + .RWE_n(RWE_n), + .Video(Video), + .HSync(hs), + .VSync(vs) + ); + +invaders_memory invaders_memory ( + .Clock(clk_sys), + .RW_n(RWE_n), + .Addr(AD), + .Ram_Addr(RAB), + .Ram_out(RDB), + .Ram_in(RWD), + .Rom_out(IB) + ); + +invaders_audio invaders_audio ( + .Clk(clk_sys), + .S1(SoundCtrl3), + .S2(SoundCtrl5), + .Aud(audio) + ); + +mist_video #(.COLOR_DEPTH(3)) mist_video( + .clk_sys(clk_mist), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R({Video,Video,Video}), + .G({Video,Video,Video}), + .B({Video,Video,Video}), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoublerD), + .scanlines(status[4:3]), + .ypbpr(ypbpr) + ); + +user_io #( + .STRLEN(($size(CONF_STR)>>3))) +user_io( + .clk_sys (clk_mist ), + .conf_str (CONF_STR ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable (scandoublerD ), + .ypbpr (ypbpr ), + .key_strobe (key_strobe ), + .key_pressed (key_pressed ), + .key_code (key_code ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) + ); + +dac dac ( + .clk_i(clk_mist), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +wire m_up = btn_up | joystick_0[3] | joystick_1[3]; +wire m_down = btn_down | joystick_0[2] | joystick_1[2]; +wire m_left = btn_left | joystick_0[1] | joystick_1[1]; +wire m_right = btn_right | joystick_0[0] | joystick_1[0]; +wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; +wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; +reg btn_one_player = 0; +reg btn_two_players = 0; +reg btn_left = 0; +reg btn_right = 0; +reg btn_down = 0; +reg btn_up = 0; +reg btn_fire1 = 0; +reg btn_fire2 = 0; +reg btn_fire3 = 0; +reg btn_coin = 0; + +always @(posedge clk_mist) begin + if(key_strobe) begin + case(key_code) + 'h75: btn_up <= key_pressed; // up + 'h72: btn_down <= key_pressed; // down + 'h6B: btn_left <= key_pressed; // left + 'h74: btn_right <= key_pressed; // right + 'h76: btn_coin <= key_pressed; // ESC + 'h05: btn_one_player <= key_pressed; // F1 + 'h06: btn_two_players <= key_pressed; // F2 + 'h14: btn_fire3 <= key_pressed; // ctrl + 'h11: btn_fire2 <= key_pressed; // alt + 'h29: btn_fire1 <= key_pressed; // Space + endcase + end +end + +endmodule diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/T80/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/T80/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/T80/T8080se.vhd new file mode 100644 index 00000000..65b92d54 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/T80/T8080se.vhd @@ -0,0 +1,194 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 8080 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original 8080 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0242 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- STACK status output not supported +-- +-- File history : +-- +-- 0237 : First version +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T8080se is + generic( + Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + ); + port( + RESET_n : in std_logic; + CLK : in std_logic; + CLKEN : in std_logic; + READY : in std_logic; + HOLD : in std_logic; + INT : in std_logic; + INTE : out std_logic; + DBIN : out std_logic; + SYNC : out std_logic; + VAIT : out std_logic; + HLDA : out std_logic; + WR_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T8080se; + +architecture rtl of T8080se is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal INT_n : std_logic; + signal HALT_n : std_logic; + signal BUSRQ_n : std_logic; + signal BUSAK_n : std_logic; + signal DO_i : std_logic_vector(7 downto 0); + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + signal One : std_logic; + +begin + + INT_n <= not INT; + BUSRQ_n <= HOLD; + HLDA <= not BUSAK_n; + SYNC <= '1' when TState = "001" else '0'; + VAIT <= '1' when TState = "010" else '0'; + One <= '1'; + + DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA + DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n + DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!! + DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA + DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT + DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1 + DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP + DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR + + u0 : T80 + generic map( + Mode => Mode, + IOWait => 0) + port map( + CEN => CLKEN, + M1_n => open, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => open, + HALT_n => HALT_n, + WAIT_n => READY, + INT_n => INT_n, + NMI_n => One, + RESET_n => RESET_n, + BUSRQ_n => One, + BUSAK_n => BUSAK_n, + CLK_n => CLK, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO_i, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n, + IntE => INTE); + + process (RESET_n, CLK) + begin + if RESET_n = '0' then + DBIN <= '0'; + WR_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK'event and CLK = '1' then + if CLKEN = '1' then + DBIN <= '0'; + WR_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and READY = '0') then + DBIN <= IntCycle_n; + end if; + else + if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then + DBIN <= '1'; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then + WR_n <= '0'; + end if; + end if; + end if; + if TState = "010" and READY = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/T80/T80_ALU.vhd new file mode 100644 index 00000000..e09def1e --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/T80/T80_ALU.vhd @@ -0,0 +1,361 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + OverFlow_v <= Carry_v xor Carry7_v; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/T80/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/T80/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/T80/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/T80/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/T80/T80_Reg.vhd new file mode 100644 index 00000000..1c0f2638 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/T80/T80_Reg.vhd @@ -0,0 +1,114 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/dac.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/dac.vhd new file mode 100644 index 00000000..db58d70b --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 8 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/invaders.vhd new file mode 100644 index 00000000..f3c2cb9d --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/invaders.vhd @@ -0,0 +1,273 @@ +-- Space Invaders core logic +-- 9.984MHz clock +-- +-- Version : 0242 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.fpgaarcade.com +-- +-- Limitations : +-- +-- File history : +-- +-- 0241 : First release +-- +-- 0242 : Cleaned up reset logic +-- +-- 0300 : MikeJ tidyup for audio release + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity invaderst is + port( + Rst_n : in std_logic; + Clk : in std_logic; + ENA : out std_logic; + Coin : in std_logic; + Sel1Player : in std_logic; + Sel2Player : in std_logic; + Fire : in std_logic; + MoveLeft : in std_logic; + MoveRight : in std_logic; + MoveUp : in std_logic; + MoveDown : in std_logic; + DIP : in std_logic_vector(8 downto 1); + RDB : in std_logic_vector(7 downto 0); + IB : in std_logic_vector(7 downto 0); + RWD : out std_logic_vector(7 downto 0); + RAB : out std_logic_vector(12 downto 0); + AD : out std_logic_vector(15 downto 0); + SoundCtrl3 : out std_logic_vector(5 downto 0); + SoundCtrl5 : out std_logic_vector(5 downto 0); + Rst_n_s : out std_logic; + RWE_n : out std_logic; + Video : out std_logic; + HSync : out std_logic; + VSync : out std_logic + ); +end invaderst; + +architecture rtl of invaderst is + + component mw8080 + port( + Rst_n : in std_logic; + Clk : in std_logic; + ENA : out std_logic; + RWE_n : out std_logic; + RDB : in std_logic_vector(7 downto 0); + RAB : out std_logic_vector(12 downto 0); + Sounds : out std_logic_vector(7 downto 0); + Ready : out std_logic; + GDB : in std_logic_vector(7 downto 0); + IB : in std_logic_vector(7 downto 0); + DB : out std_logic_vector(7 downto 0); + AD : out std_logic_vector(15 downto 0); + Status : out std_logic_vector(7 downto 0); + Systb : out std_logic; + Int : out std_logic; + Hold_n : in std_logic; + IntE : out std_logic; + DBin_n : out std_logic; + Vait : out std_logic; + HldA : out std_logic; + Sample : out std_logic; + Wr : out std_logic; + Video : out std_logic; + HSync : out std_logic; + VSync : out std_logic); + end component; + + signal GDB0 : std_logic_vector(7 downto 0); + signal GDB1 : std_logic_vector(7 downto 0); + signal GDB2 : std_logic_vector(7 downto 0); + signal S : std_logic_vector(7 downto 0); + signal GDB : std_logic_vector(7 downto 0); + signal DB : std_logic_vector(7 downto 0); + signal Sounds : std_logic_vector(7 downto 0); + signal AD_i : std_logic_vector(15 downto 0); + signal PortWr : std_logic_vector(6 downto 2); + signal EA : std_logic_vector(2 downto 0); + signal D5 : std_logic_vector(15 downto 0); + signal WD_Cnt : unsigned(7 downto 0); + signal Sample : std_logic; + signal Rst_n_s_i : std_logic; +begin + + Rst_n_s <= Rst_n_s_i; + RWD <= DB; + AD <= AD_i; + + process (Rst_n, Clk) + variable Rst_n_r : std_logic; + begin + if Rst_n = '0' then + Rst_n_r := '0'; + Rst_n_s_i <= '0'; + elsif Clk'event and Clk = '1' then + Rst_n_s_i <= Rst_n_r; + if WD_Cnt = 255 then + Rst_n_s_i <= '0'; + end if; + Rst_n_r := '1'; + end if; + end process; + + process (Rst_n_s_i, Clk) + variable Old_S0 : std_logic; + begin + if Rst_n_s_i = '0' then + WD_Cnt <= (others => '0'); + Old_S0 := '1'; + elsif Clk'event and Clk = '1' then + if Sounds(0) = '1' and Old_S0 = '0' then + WD_Cnt <= WD_Cnt + 1; + end if; + if PortWr(6) = '1' then + WD_Cnt <= (others => '0'); + end if; + Old_S0 := Sounds(0); + end if; + end process; + + u_mw8080: mw8080 + port map( + Rst_n => '1',--Rst_n_s_i, + Clk => Clk, + ENA => ENA, + RWE_n => RWE_n, + RDB => RDB, + IB => IB, + RAB => RAB, + Sounds => Sounds, + Ready => open, + GDB => GDB, + DB => DB, + AD => AD_i, + Status => open, + Systb => open, + Int => open, + Hold_n => '1', + IntE => open, + DBin_n => open, + Vait => open, + HldA => open, + Sample => Sample, + Wr => open, + Video => Video, + HSync => HSync, + VSync => VSync); + + with AD_i(9 downto 8) select + GDB <= GDB0 when "00", + GDB1 when "01", + GDB2 when "10", + S when others; + + GDB0(0) <= not MoveUp;--active low + GDB0(1) <= not MoveDown;--active low + GDB0(2) <= not MoveLeft;--active low + GDB0(3) <= not MoveRight;--active low + GDB0(4) <= '1';--active low + GDB0(5) <= '1';--active low + GDB0(6) <= '1';--active low + GDB0(7) <= not Fire; + + GDB1(0) <= not MoveUp;--active low + GDB1(1) <= not MoveDown;--active low + GDB1(2) <= not MoveLeft;--active low + GDB1(3) <= not MoveRight;--active low + GDB1(4) <= '1';--active low + GDB1(5) <= '1';--active low + GDB1(6) <= '1';--active low + GDB1(7) <= not Fire;--active low + + GDB2(0) <= '0';--active high + GDB2(1) <= '0';--active high + GDB2(2) <= '0';--active high + GDB2(3) <= '0';--active high + GDB2(4) <= '0';--DIPLOCK --active high + GDB2(5) <= not Sel1Player;--active low + GDB2(6) <= not Coin;--active low + GDB2(7) <= not Sel2Player;--active low + + PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0'; + PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0'; + PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0'; + PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0'; + PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0'; + + process (Rst_n_s_i, Clk) + variable OldSample : std_logic; + begin + if Rst_n_s_i = '0' then + D5 <= (others => '0'); + EA <= (others => '0'); + SoundCtrl3 <= (others => '0'); + SoundCtrl5 <= (others => '0'); + OldSample := '0'; + elsif Clk'event and Clk = '1' then + if PortWr(2) = '1' then + EA <= DB(2 downto 0); + end if; + if PortWr(3) = '1' then + SoundCtrl3 <= DB(5 downto 0); + end if; + if PortWr(4) = '1' and OldSample = '0' then + D5(15 downto 8) <= DB; + D5(7 downto 0) <= D5(15 downto 8); + end if; + if PortWr(5) = '1' then + SoundCtrl5 <= DB(5 downto 0); + end if; + OldSample := Sample; + end if; + end process; + + with EA select + S <= D5(15 downto 8) when "000", + D5(14 downto 7) when "001", + D5(13 downto 6) when "010", + D5(12 downto 5) when "011", + D5(11 downto 4) when "100", + D5(10 downto 3) when "101", + D5( 9 downto 2) when "110", + D5( 8 downto 1) when others; + +end; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/invaders_audio.vhd new file mode 100644 index 00000000..f16cf379 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/invaders_audio.vhd @@ -0,0 +1,496 @@ + +-- Version : 0300 +-- The latest version of this file can be found at: +-- http://www.fpgaarcade.com +-- minor tidy up by MikeJ +------------------------------------------------------------------------------- +-- Company: +-- Engineer: PaulWalsh +-- +-- Create Date: 08:45:29 11/04/05 +-- Design Name: +-- Module Name: Invaders Audio +-- Project Name: Space Invaders +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + +entity invaders_audio is + Port ( + Clk : in std_logic; + S1 : in std_logic_vector(5 downto 0); + S2 : in std_logic_vector(5 downto 0); + Aud : out std_logic_vector(7 downto 0) + ); +end; + --* Port 3: (S1) + --* bit 0=UFO (repeats) + --* bit 1=Shot + --* bit 2=Base hit + --* bit 3=Invader hit + --* bit 4=Bonus base + --* + --* Port 5: (S2) + --* bit 0=Fleet movement 1 + --* bit 1=Fleet movement 2 + --* bit 2=Fleet movement 3 + --* bit 3=Fleet movement 4 + --* bit 4=UFO 2 + +architecture Behavioral of invaders_audio is + + signal ClkDiv : unsigned(10 downto 0) := (others => '0'); + signal ClkDiv2 : std_logic_vector(7 downto 0) := (others => '0'); + signal Clk7680_ena : std_logic; + signal Clk480_ena : std_logic; + signal Clk240_ena : std_logic; + signal Clk60_ena : std_logic; + + signal s1_t1 : std_logic_vector(5 downto 0); + signal s2_t1 : std_logic_vector(5 downto 0); + signal tempsum : std_logic_vector(7 downto 0); + + signal vco_cnt : std_logic_vector(3 downto 0); + + signal TriDir1 : std_logic; + signal Fnum : std_logic_vector(3 downto 0); + signal comp : std_logic; + + signal SS : std_logic; + + signal TrigSH : std_logic; + signal SHCnt : std_logic_vector(8 downto 0); + signal SH : std_logic_vector(7 downto 0); + signal SauHit : std_logic_vector(8 downto 0); + signal SHitTri : std_logic_vector(5 downto 0); + + signal TrigIH : std_logic; + signal IHDir : std_logic; + signal IHDir1 : std_logic; + signal IHCnt : std_logic_vector(8 downto 0); + signal IH : std_logic_vector(7 downto 0); + signal InHit : std_logic_vector(8 downto 0); + signal IHitTri : std_logic_vector(5 downto 0); + + signal TrigEx : std_logic; + signal Excnt : std_logic_vector(9 downto 0); + signal ExShift : std_logic_vector(15 downto 0); + signal Ex : std_logic_vector(2 downto 0); + signal Explo : std_logic; + + signal TrigMis : std_logic; + signal MisShift : std_logic_vector(15 downto 0); + signal MisCnt : std_logic_vector(8 downto 0); + signal miscnt1 : unsigned(7 downto 0); + signal Mis : std_logic_vector(2 downto 0); + signal Missile : std_logic; + + signal EnBG : std_logic; + signal BGFnum : std_logic_vector(7 downto 0); + signal BGCnum : std_logic_vector(7 downto 0); + signal bg_cnt : unsigned(7 downto 0); + signal BG : std_logic; + +begin + + -- do a crude addition of all sound samples + p_audio_mix : process + variable IHVol : std_logic_vector(6 downto 0); + variable SHVol : std_logic_vector(6 downto 0); + begin + wait until rising_edge(Clk); + + IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0); + SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0); + + tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol); + + Aud(7) <= tempsum (7); + Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor (Ex(2) and Explo) xor BG; + Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor (Ex(1) and Explo) xor SS; + Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor (Ex(0) and Explo); + Aud(3 downto 0) <= tempsum (3 downto 0); + + end process; + + p_clkdiv : process + begin + wait until rising_edge(Clk); + Clk7680_ena <= '0'; + if ClkDiv = 1277 then + Clk7680_ena <= '1'; + ClkDiv <= (others => '0'); + else + ClkDiv <= ClkDiv + 1; + end if; + end process; + + p_clkdiv2 : process + begin + wait until rising_edge(Clk); + Clk480_ena <= '0'; + Clk240_ena <= '0'; + Clk60_ena <= '0'; + + if (Clk7680_ena = '1') then + ClkDiv2 <= ClkDiv2 + 1; + + if (ClkDiv2(3 downto 0) = "0000") then + Clk480_ena <= '1'; + end if; + + if (ClkDiv2(4 downto 0) = "00000") then + Clk240_ena <= '1'; + end if; + + if (ClkDiv2(7 downto 0) = "00000000") then + Clk60_ena <= '1'; + end if; + + end if; + end process; + + p_delay : process + begin + wait until rising_edge(Clk); + s1_t1 <= S1; + s2_t1 <= S2; + end process; +--*************************Saucer Sound*************************************** + +-- Implement a VCOscilator: frequency is set using counter end point(Fnum) + p_saucer_vco : process + variable term : std_logic_vector(3 downto 0); + begin + wait until rising_edge(Clk); + term := 8 + Fnum; + if (S1(0) = '1') and (Clk7680_ena = '1') then + if vco_cnt = term then + + vco_cnt <= (others => '0'); + SS <= not SS; + else + vco_cnt <= vco_cnt + 1; + end if; + end if; + end process; + +-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator + -- this is 6Hz ?? 0123454321 + p_saucer_lfo : process + begin + wait until rising_edge(Clk); + if (Clk60_ena = '1') then + if Fnum = 4 then -- 5 -1 + Comp <= '1'; + elsif Fnum = 1 then -- 0 +1 + Comp <= '0'; + end if; + + if comp = '1' then + Fnum <= Fnum - 1 ; + else + Fnum <= Fnum + 1 ; + end if; + end if; + end process; + +--**********************SAUCER HIT Sound************************** + +-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO + p_saucer_hit_vco : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if SHitTri = 48 then + SHitTri <= "000000"; + else + SHitTri <= SHitTri+1; + end if; + end if; + end process; + +-- Implement a trianglular wave VCO for Saucer Hit 200Hz to 1kHz approx + p_saucer_hit_lfo : process + begin + wait until rising_edge(Clk); + if (Clk7680_ena = '1') then + if TriDir1 = '1' then + if (SauHit +58 - SHitTri) < 190 + 256 then + SauHit <= SauHit +58 - SHitTri; + else + SauHit <= "110111110"; + TriDir1 <= '0'; + end if; + else + if (SauHit -58 + SHitTri) > 256 then + SauHit <= SauHit -58 + SHitTri; + else + SauHit <= "100000000"; + TriDir1 <= '1'; + end if; + end if; + end if; + end process; + +-- Implement the ADSR for Saucer Hit Sound + p_saucer_adsr : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if (TrigSH = '1') then + SHCnt <= "100000000"; + SH <= "11111111"; + elsif (SHCnt(8) = '1') then + SHCnt <= SHCnt + "1"; + if SHCnt(7 downto 0) = x"60" then -- 96 + SH <= "01111111"; + elsif SHCnt(7 downto 0) = x"90" then -- 144 + SH <= "00111111"; + elsif SHCnt(7 downto 0) = x"C0" then -- 192 + SH <= "00000000"; + end if; + end if; + end if; + end process; + + -- Implement the trigger for The Saucer Hit Sound + p_saucer_hit : process + begin + wait until rising_edge(Clk); + if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge + TrigSH <= '1'; + elsif (Clk480_ena = '1') then + TrigSH <= '0'; + end if; + end process; + +--***********************Invader Hit Sound***************************** +-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO + p_invader_hit_lfo : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if IHitTri = 48-2 then + IHDir <= '0'; + elsif IHitTri =0+2 then + IHDir <= '1'; + end if; + + if IHDir ='1' then + IHitTri <= IHitTri + 2; + else + IHitTri <= IHitTri - 2; + end if; + end if; + end process; + +-- Implement a trianglular wave VCO for Invader Hit 700Hz to 3kHz approx + p_invader_hit_vco : process + begin + wait until rising_edge(Clk); + if (Clk7680_ena = '1') then + if IHDir1 = '1' then + if (InHit +10 + IHitTri) < 110 + 256 then + InHit <= InHit +10 + IHitTri; + else + InHit <= "101101110"; + IHDir1 <= '0'; + end if; + else + if (InHit -10 - IHitTri) > 256 then + InHit <= InHit -10 - IHitTri; + else + InHit <= "100000000"; + IHDir1 <= '1'; + end if; + end if; + end if; + end process; + +-- Implement the ADSR for Invader Hit Sound + p_invader_adsr : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if (TrigIH = '1') then + IHCnt <= "100000000"; + IH <= "11111111"; + elsif (IHCnt(8) = '1') then + IHCnt <= IHCnt + "1"; + if IHCnt(7 downto 0) = x"14" then -- 20 + IH <= "01111111"; + elsif IHCnt(7 downto 0) = x"1C" then -- 28 + IH <= "11111111"; + elsif IHCnt(7 downto 0) = x"30" then -- 48 + IH <= "00000000"; + end if; + end if; + end if; + end process; + + -- Implement the trigger for The Invader Hit Sound + p_invader_hit : process + begin + wait until rising_edge(Clk); + if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge + TrigIH <= '1'; + elsif (Clk480_ena = '1') then + TrigIH <= '0'; + end if; + end process; + +--***********************Explosion***************************** +-- Implement a Pseudo Random Noise Generator + p_explosion_pseudo : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if (ExShift = x"0000") then + ExShift <= "0000000010101001"; + else + ExShift(0) <= Exshift(14) xor ExShift(15); + ExShift(15 downto 1) <= ExShift (14 downto 0); + end if; + end if; + end process; + Explo <= ExShift(0); + + p_explosion_adsr : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if (TrigEx = '1') then + ExCnt <= "1000000000"; + Ex <= "100"; + elsif (ExCnt(9) = '1') then + ExCnt <= ExCnt + "1"; + if ExCnt(8 downto 0) = '0' & x"64" then -- 100 + Ex <= "010"; + elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200 + Ex <= "001"; + elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300 + Ex <= "000"; + end if; + end if; + end if; + end process; + +-- Implement the trigger for The Explosion Sound + p_explosion_trig : process + begin + wait until rising_edge(Clk); + if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge + TrigEx <= '1'; + elsif (Clk480_ena = '1') then + TrigEx <= '0'; + end if; + end process; + +--***********************Missile***************************** +-- Implement a Pseudo Random Noise Generator + p_missile_pseudo : process + begin + wait until rising_edge(Clk); + if (Clk7680_ena = '1') then + if (MisShift = x"0000") then + MisShift <= "0000000010101001"; + else + MisShift(0) <= MisShift(14) xor MisShift(15); + MisShift(15 downto 1) <= MisShift (14 downto 0); + end if; + + miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0)); + if miscnt1 > 60 then + miscnt1 <= "00000000"; + Missile <= not Missile; + end if; + + end if; + end process; + +-- Implement the ADSR for The Missile Sound + p_missile_adsr : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if (TrigMis = '1') then + MisCnt <= "100000000"; + Mis <= "100"; + elsif (MisCnt(8) = '1') then + MisCnt <= MisCnt + "1"; + if MisCnt(7 downto 0) = x"4b" then -- 75 + Mis <= "010"; + elsif MisCnt(7 downto 0) = x"70" then -- 112 + Mis <= "001"; + elsif MisCnt(7 downto 0) = x"96" then -- 150 + Mis <= "000"; + end if; + end if; + end if; + end process; + +-- Implement the trigger for The Missile Sound + p_missile_trig : process + begin + wait until rising_edge(Clk); + if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge + TrigMis <= '1'; + elsif (Clk480_ena = '1') then + TrigMis <= '0'; + end if; + end process; + +-- ******************************** Background invader moving tones ************************** + EnBG <= S2(0) or S2(1) or S2(2) or S2(3); + + with S2(3 downto 0) select + BGFnum <= x"66" when "0001", + x"74" when "0010", + x"7C" when "0100", + x"87" when "1000", + x"87" when others; + + with S2(3 downto 0) select + BGCnum <= x"33" when "0001", + x"3A" when "0010", + x"3E" when "0100", + x"43" when "1000", + x"43" when others; + +-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum) + + p_background : process + begin + wait until rising_edge(Clk); + if (Clk7680_ena = '1') then + if EnBG = '0' then + bg_cnt <= x"00"; + BG <= '0'; + else + bg_cnt <= bg_cnt + 1; + + if bg_cnt = unsigned(BGfnum) then + bg_cnt <= x"00"; + BG <= '0'; + elsif bg_cnt=unsigned(BGCnum) then + BG <='1'; + end if; + end if; + end if; + end process; + +end Behavioral; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/invaders_memory.sv b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/invaders_memory.sv new file mode 100644 index 00000000..382edd1e --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/invaders_memory.sv @@ -0,0 +1,66 @@ + +module invaders_memory( +input Clock, +input RW_n, +input [15:0]Addr, +input [15:0]Ram_Addr, +output [7:0]Ram_out, +input [7:0]Ram_in, +output [7:0]Rom_out +); + +wire [7:0]rom_data_0; +wire [7:0]rom_data_1; +wire [7:0]rom_data_2; +wire [7:0]rom_data_3; + + + +romh romh ( + .clk(Clock), + .addr(Addr[10:0]), + .data(rom_data_0) +); + +romg romg ( + .clk(Clock), + .addr(Addr[10:0]), + .data(rom_data_1) +); + +romf romf ( + .clk(Clock), + .addr(Addr[10:0]), + .data(rom_data_2) +); + +rome rome ( + .clk(Clock), + .addr(Addr[10:0]), + .data(rom_data_3) +); + + +always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3) begin + Rom_out = 8'b00000000; + case (Addr[13:11]) + 3'b000 : Rom_out = rom_data_0; + 3'b001 : Rom_out = rom_data_1; + 3'b010 : Rom_out = rom_data_2; + 3'b011 : Rom_out = rom_data_3; + default : Rom_out = 8'b00000000; + endcase +end + +spram #( + .addr_width_g(13), + .data_width_g(8)) +u_ram0( + .address(Ram_Addr[12:0]), + .clken(1'b1), + .clock(Clock), + .data(Ram_in), + .wren(~RW_n), + .q(Ram_out) + ); +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/invaders_video.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/invaders_video.vhd new file mode 100644 index 00000000..77ac2478 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/invaders_video.vhd @@ -0,0 +1,127 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + + +entity invaders_video is + port( + Video : in std_logic; + Overlay : in std_logic; + CLK : in std_logic; + Rst_n_s : in std_logic; + HSync : in std_logic; + VSync : in std_logic; + O_VIDEO_R : out std_logic; + O_VIDEO_G : out std_logic; + O_VIDEO_B : out std_logic; + O_HSYNC : out std_logic; + O_VSYNC : out std_logic + ); +end invaders_video; + +architecture rtl of invaders_video is + + signal HCnt : std_logic_vector(11 downto 0); + signal VCnt : std_logic_vector(11 downto 0); + signal HSync_t1 : std_logic; + signal Overlay_G1 : boolean; + signal Overlay_G2 : boolean; + signal Overlay_R1 : boolean; + signal Overlay_G1_VCnt : boolean; + signal VideoRGB : std_logic_vector(2 downto 0); +begin + process (Rst_n_s, Clk) + variable cnt : unsigned(3 downto 0); + begin + if Rst_n_s = '0' then + cnt := "0000"; + elsif Clk'event and Clk = '1' then + if cnt = 9 then + cnt := "0000"; + else + cnt := cnt + 1; + end if; + end if; + end process; + + p_overlay : process(Rst_n_s, Clk) + variable HStart : boolean; + begin + if Rst_n_s = '0' then + HCnt <= (others => '0'); + VCnt <= (others => '0'); + HSync_t1 <= '0'; + Overlay_G1_VCnt <= false; + Overlay_G1 <= false; + Overlay_G2 <= false; + Overlay_R1 <= false; + elsif Clk'event and Clk = '1' then + HSync_t1 <= HSync; + HStart := (HSync_t1 = '0') and (HSync = '1'); + + if HStart then + HCnt <= (others => '0'); + else + HCnt <= HCnt + "1"; + end if; + + if (VSync = '0') then + VCnt <= (others => '0'); + elsif HStart then + VCnt <= VCnt + "1"; + end if; + + if HStart then + if (Vcnt = x"1F") then + Overlay_G1_VCnt <= true; + elsif (Vcnt = x"95") then + Overlay_G1_VCnt <= false; + end if; + end if; + + if (HCnt = x"027") and Overlay_G1_VCnt then + Overlay_G1 <= true; + elsif (HCnt = x"046") then + Overlay_G1 <= false; + end if; + + if (HCnt = x"046") then + Overlay_G2 <= true; + elsif (HCnt = x"0B6") then + Overlay_G2 <= false; + end if; + + if (HCnt = x"1A6") then + Overlay_R1 <= true; + elsif (HCnt = x"1E6") then + Overlay_R1 <= false; + end if; + + end if; + end process; + + p_video_out_comb : process(Video, Overlay_G1, Overlay_G2, Overlay_R1) + begin + if (Video = '0') then + VideoRGB <= "000"; + else + if Overlay_G1 or Overlay_G2 then + VideoRGB <= "010"; + elsif Overlay_R1 then + VideoRGB <= "100"; + else + VideoRGB <= "111"; + end if; + end if; + end process; + + + O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); + O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); + O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); + O_HSYNC <= not HSync; + O_VSYNC <= not VSync; + + +end; \ No newline at end of file diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/mw8080.vhd new file mode 100644 index 00000000..b9a88f96 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/mw8080.vhd @@ -0,0 +1,336 @@ +-- Midway 8080 main board +-- 9.984MHz Clock +-- +-- Version : 0242 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.fpgaarcade.com +-- +-- Limitations : +-- +-- File history : +-- +-- 0241 : First release +-- +-- 0242 : Removed the ROM +-- +-- 0300 : MikeJ tidyup for audio release +-- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity mw8080 is + port( + Rst_n : in std_logic; + Clk : in std_logic; + ENA : out std_logic; + RWE_n : out std_logic; + RDB : in std_logic_vector(7 downto 0); + RAB : out std_logic_vector(12 downto 0); + Sounds : out std_logic_vector(7 downto 0); + Ready : out std_logic; + GDB : in std_logic_vector(7 downto 0); + IB : in std_logic_vector(7 downto 0); + DB : out std_logic_vector(7 downto 0); + AD : out std_logic_vector(15 downto 0); + Status : out std_logic_vector(7 downto 0); + Systb : out std_logic; + Int : out std_logic; + Hold_n : in std_logic; + IntE : out std_logic; + DBin_n : out std_logic; + Vait : out std_logic; + HldA : out std_logic; + Sample : out std_logic; + Wr : out std_logic; + Video : out std_logic; + HSync : out std_logic; + VSync : out std_logic); +end mw8080; + +architecture struct of mw8080 is + + component T8080se + generic( + Mode : integer := 2; + T2Write : integer := 0); + port( + RESET_n : in std_logic; + CLK : in std_logic; + CLKEN : in std_logic; + READY : in std_logic; + HOLD : in std_logic; + INT : in std_logic; + INTE : out std_logic; + DBIN : out std_logic; + SYNC : out std_logic; + VAIT : out std_logic; + HLDA : out std_logic; + WR_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0)); + end component; + + signal Ready_i : std_logic; + signal Hold : std_logic; + signal IntTrig : std_logic; + signal IntTrigOld : std_logic; + signal Int_i : std_logic; + signal IntE_i : std_logic; + signal DBin : std_logic; + signal Sync : std_logic; + signal Wr_n, Rd_n : std_logic; + signal ClkEnCnt : unsigned(2 downto 0); + signal Status_i : std_logic_vector(7 downto 0); + signal A : std_logic_vector(15 downto 0); + signal ISel : std_logic_vector(1 downto 0); + signal DI : std_logic_vector(7 downto 0); + signal DO : std_logic_vector(7 downto 0); + signal RR : std_logic_vector(9 downto 0); + + signal VidEn : std_logic; + signal CntD5 : unsigned(3 downto 0); -- Horizontal counter / 320 + signal CntE5 : unsigned(4 downto 0); -- Horizontal counter 2 + signal CntE6 : unsigned(3 downto 0); -- Vertical counter / 262 + signal CntE7 : unsigned(4 downto 0); -- Vertical counter 2 + signal Shift : std_logic_vector(7 downto 0); + +begin + ENA <= ClkEnCnt(2); + Status <= Status_i; + Ready <= Ready_i; + DB <= DO; + Systb <= Sync; + Int <= Int_i; + Hold <= not Hold_n; + IntE <= IntE_i; + DBin_n <= not DBin; + Sample <= not Wr_n and Status_i(4); + Wr <= not Wr_n; + AD <= A; + Sounds(0) <= CntE7(3); + Sounds(1) <= CntE7(2); + Sounds(2) <= CntE7(1); + Sounds(3) <= CntE7(0); + Sounds(4) <= CntE6(3); + Sounds(5) <= CntE6(2); + Sounds(6) <= CntE6(1); + Sounds(7) <= CntE6(0); + + IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4); + + ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13)); + ISel(1) <= Status_i(0) nor Status_i(6); + + with ISel select + DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00", + GDB when "01", + IB when "10", + RR(7 downto 0) when others; + + RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2); + RAB <= A(12 downto 0) when CntD5(2) = '1' else + std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3)); + + u_8080: T8080se + generic map ( + Mode => 2, + T2Write => 1) + port map ( + RESET_n => Rst_n, + CLK => Clk, + CLKEN => ClkEnCnt(2), + READY => Ready_i, + HOLD => Hold, + INT => Int_i, + INTE => IntE_i, + DBIN => DBin, + SYNC => Sync, + VAIT => Vait, + HLDA => HLDA, + WR_n => Wr_n, + A => A, + DI => DI, + DO => DO); + + -- Clock enables + process (Rst_n, Clk) + begin + if Rst_n = '0' then + ClkEnCnt <= "000"; + VidEn <= '0'; + elsif Clk'event and Clk = '1' then + VidEn <= not VidEn; + if ClkEnCnt = 4 then + ClkEnCnt <= "000"; + else + ClkEnCnt <= ClkEnCnt + 1; + end if; + end if; + end process; + + -- Glue + process (Rst_n, Clk) + variable OldASEL : std_logic; + begin + if Rst_n = '0' then + Status_i <= (others => '0'); + IntTrigOld <= '0'; + Int_i <= '0'; + OldASEL := '0'; + Ready_i <= '0'; + RR <= (others => '0'); + elsif Clk'event and Clk = '1' then + -- E3 + -- Interrupt + IntTrigOld <= IntTrig; + if Status_i(0) = '1' then + Int_i <= '0'; + elsif IntTrigOld = '0' and IntTrig = '1' then + Int_i <= IntE_i; + end if; + + -- D7 + -- Status register + if Sync = '1' then + Status_i <= DO; + end if; + + -- A3, C3, E3 + -- RAM register/ready logic + if Sync = '1' and A(13) = '1' then + Ready_i <= '0'; + elsif Ready_i = '1' then + Ready_i <= '1'; + else + Ready_i <= RR(9); + end if; + if Sync = '1' and A(13) = '1' then + RR <= (others => '0'); + elsif (CntD5(2) = '1' and OldASEL = '0') or -- ASEL pos edge + (CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge + RR(7 downto 0) <= RDB; + RR(8) <= '1'; + RR(9) <= RR(8); + end if; + OldASEL := CntD5(2); + end if; + end process; + + -- Video counters + process (Rst_n, Clk) + begin + if Rst_n = '0' then + CntD5 <= (others => '0'); + CntE5 <= (others => '0'); + CntE6 <= (others => '0'); + CntE7 <= (others => '0'); + elsif Clk'event and Clk = '1' then + if VidEn = '1' then + CntD5 <= CntD5 + 1; + if CntD5 = 15 then + + CntE5 <= CntE5 + 1; + if CntE5(3 downto 0) = 15 then + if CntE5(4) = '0' then + CntE5 <= "11100"; + + CntE6 <= CntE6 + 1; + if CntE6 = 15 then + + CntE7 <= CntE7 + 1; + if CntE7(3 downto 0) = 15 then + if CntE7(4) = '0' then + CntE6 <= "1010"; + CntE7 <= "11101"; + else + CntE7 <= "00010"; + end if; + end if; + end if; + end if; + else + end if; + end if; + end if; + end if; + end process; + + -- Video shift register + process (Rst_n, Clk) + begin + if Rst_n = '0' then + Shift <= (others => '0'); + Video <= '0'; + elsif Clk'event and Clk = '1' then + if VidEn = '1' then + if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then + Shift(7 downto 0) <= RDB(7 downto 0); + else + Shift(6 downto 0) <= Shift(7 downto 1); + Shift(7) <= '0'; + end if; + Video <= Shift(0); + end if; + end if; + end process; + + -- Sync + process (Rst_n, Clk) + begin + if Rst_n = '0' then + HSync <= '1'; + VSync <= '1'; + elsif Clk'event and Clk = '1' then + if VidEn = '1' then + if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then + HSync <= '0'; + else + HSync <= '1'; + end if; + if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then + VSync <= '0'; + else + VSync <= '1'; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/pll.ppf b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/pll.ppf new file mode 100644 index 00000000..71e6f03a --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/pll.ppf @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/pll.qip b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/pll.qip new file mode 100644 index 00000000..48665362 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/pll.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/pll.vhd new file mode 100644 index 00000000..feed4923 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/pll.vhd @@ -0,0 +1,382 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.4 Build 182 03/12/2014 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire5_bv(0 DOWNTO 0) <= "0"; + sub_wire5 <= To_stdlogicvector(sub_wire5_bv); + sub_wire2 <= sub_wire0(1); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + c1 <= sub_wire2; + sub_wire3 <= inclk0; + sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 27, + clk0_duty_cycle => 50, + clk0_multiply_by => 10, + clk0_phase_shift => "0", + clk1_divide_by => 9, + clk1_duty_cycle => 50, + clk1_multiply_by => 8, + clk1_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire4, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "24.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "40" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "24.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/roms/rome.cpu b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/roms/rome.cpu new file mode 100644 index 0000000000000000000000000000000000000000..26a3ab84681f9d87ce7aec0b99a5f9d4fb02a8dd GIT binary patch literal 2048 zcmcH(?{8Dr_1^n_*zYCw%d_Lye(yQCFE&kL7veku4IVMi!H%6N_KR!>Lyc&wO=Z(0 zGAg7b8<=cErIb!aA z4y^4TuzSxv=brP<&#QA@Sxez|%(L>!jd*(Lt>g8Wrx_Jh06y{F9`t;C?~7HpvEoji zaW9>AAOCE+>hY|f9x9v}dMc8_<<)$zKz{iKXeA&w3mW!s-}a7Aw&x ztcPKAP}_lP>skS8hp{$->#LsD)1Hk!ulhU|dw{o8{`Z;AmFihfO!Bjw|_}UHUXCXaQXRoA^H6*>St>xo#;m zhcmbt;c!DSi1n^PE=q5Np?bp?S;Xa=pLx^|ef1wJQJ&ZZiDp#TI3ahvbh$plt!sW9 z6!0*MYe5$KP5Nc>q!cs%v^T=y_m5Z8UX91G&;h%52*5k8ukJgpYhT;X46v-^VmlJe0*PZ=Qir7_k!?$e zMUuV6wq31Gn{I(N*J`ypExIkX+HKTAZTo$`XA1Q6hTT23;C;TI+@0j^2wFLwd&hI% zgS;=wBozn=K!gY&iXuSKGy#A*CcrHdKnDS~1-76GP^V^?IGeD{zPn_*oRqFd_5xmkAxiHab`G6(v6?NjtBx|zN3iDwm2AwB2t1hL{>wnE-2By z>tRGm4Z$R}rWwTy%$KX*Q@Vwywutyg4B5a&TP6?kDLE0IIvi#V{I>Cm?; z%CyCjyo(xC#hhoikIRT)lmNY29x`tKS-Ey+rG7%bCj#VczPE8zsa{q7O5a7}jY~Ig zDV7E_?jlQr{ex-j_i?kT1D9TI-BSKpdU<)Z0jD()Pm>WQ0eUT#>)$5ByRO-=X2-P< zW3@8OZiZn(3`C^kX@nwkxcn~psa4(DNvxj0rG`*h4wW9vEN?tBKvFJOZw=G{INkj_pSdN`wM0LMyb=Hb^#QgT2Vc3*a1dA%N^qr242{aE=xz z0SW|@e}!p7IJ=c-A**SHM7|%AjYMKAg6An7@~l9xz&cG#M(}@_NCfDl2app9EWfP@ z^zK?rriu$jq4;EMp;(Bei!{9R@J1fVoV#Fv@#(K{E<{`6?H|V-npxMrY9ALl;TVkR_lZ5_~8`A3IQFw zyLJNsU+eq5=kI&(tIvDy^PX0$cC(jX-=gZ>EJNcSWGXBs?n(a7R(2ypD^|1Y{d$)D zbV1A;_$cBwP*SsL{+MmdIA`>oY{Ts0KiuUmp4)@utmD@Yv2#4$g*cv)`fq=eH8cxV zH0w>3W~d0a1DPjT0!tQDZwrDT3)wrek=cM|Ew*&WV?ckKO;dD`ij0!I#5OBzcQSI< z&3lx5pqoBZSpu8LO|#85T;sbJ4H{9+=`=<9^}n-?NL>FLYv3KowU|0vS<=WN?aGgl zL2}ayUwMVQWOI#jC#P8hfcRn?sa7~o$S9e%Lc#SxZo6_nQnF|-F@MY1Jv)%SWS-^R zV466M%wt^R9WX6c5>zf|Z|m15xQMNh?~d6$8DxVc?ng(+VKPC+$(%}5oxmg&cV&sK3G)qokRjFzuHl0BPSGB{vh4CpT;tv26gVMVj%?O(jRBlVd@B znVY)YJ7P?}@XUuVr@Hjkf4%%??%!#KFd;}cLP&%8YtDsdn+i`Ssffl4Ilqf(UL_!V z@a9$HuML`_IEuOt4dmE&g$w##{ywVreXZEC0>q5^L5&pWX{Di0coSZr2DSzZCRfL}fWefbsgh5EpFd`bU@ezss zC)K$?>JJOHk%VPM^{0d!t&-K|;Dk9PG*-AU^?)?tY*;@cbO%#fv6K!Q_+GiNpuZ%L z$p!soLB3}g9aZ5~Va8$f8NrCS?6!@}PE;)6lgRvqfZy=WA~IV7K7-0F!3FdESjGHW z%n7ZT`(sYW+O-INS#kpFr(*aJ%Jr$r0RZXTsQ*z&-5 zG5gh_Lc?gfei|Y34M<48ekum3_$2*#yWD0!m^WrQ=8c=PF&IcKc*Y6WZ^fLo+O3%T zhppd;IajWywC!1-4shq9YCvhZE@ZC9fB;;#TS<$q09iCgygCQrxMtDz?^O6WYR(67 zdZEeLEqu9mb0&hW1=sX@qv3NhXkyN_$E7@U6SzefS_E!fJn>H~W84lbZPcT8ytnW)OzJg1e zM-X5sx>&{&Kv@^d{{O*p-or9+7t0?cW@|Z;z@2E>w>=O0e90Qf&sN3@z_QLoKm7%2 zF%Z)qfg-rA2E+@c0(xP-^)D=g3(jfqL~LF*<2XW+mQL-X1on?(cYY| z43T?{e5dxcu$Y@yZG2dwRf+f)>QT||NC91T1KvuSO0K@QM_hsPC*C>aox3)=Hz(kH zZ<7QPD}h8L!v$nu0Wo1M6bj9XBFLHugHlw3`aZGkvy#wAcWV6&IWmYxk>;GLpAZ?^ z*;qR%GQO1Ne5U>bkqJ0#?S~>01~#@%s|L`o?Y7~Zsf)@Of=&gpo>t3C@m2gZdW?+X zXV4(oYyL&N9K%yGAux}ABd!#yw?v{1iLk6ze$trwUS;gf5lm4zM(Wqs#c%%$mW%>j literal 0 HcmV?d00001 diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/roms/romf.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/roms/romf.vhd new file mode 100644 index 00000000..032ba6d3 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/roms/romf.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity romf is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of romf is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"7E",X"A7",X"CA",X"0E",X"10",X"C6",X"99",X"27",X"77",X"C2",X"0E",X"10",X"06",X"01",X"21",X"22", + X"20",X"CD",X"32",X"10",X"21",X"23",X"20",X"CD",X"32",X"10",X"23",X"CD",X"32",X"10",X"23",X"CD", + X"32",X"10",X"23",X"CD",X"32",X"10",X"23",X"CD",X"32",X"10",X"23",X"CD",X"32",X"10",X"32",X"4B", + X"20",X"C9",X"7E",X"A7",X"CA",X"3C",X"10",X"35",X"C2",X"3C",X"10",X"37",X"78",X"17",X"47",X"C9", + X"21",X"86",X"20",X"11",X"0B",X"00",X"19",X"E5",X"E5",X"CD",X"A6",X"10",X"E1",X"7D",X"FE",X"B2", + X"C2",X"43",X"10",X"E1",X"CD",X"0D",X"12",X"E1",X"CD",X"0D",X"12",X"E1",X"CD",X"0D",X"12",X"E1", + X"C3",X"0D",X"12",X"11",X"54",X"20",X"1A",X"3C",X"FE",X"03",X"C2",X"6E",X"10",X"AF",X"12",X"21", + X"49",X"20",X"11",X"12",X"00",X"19",X"3D",X"F2",X"75",X"10",X"C9",X"7E",X"E6",X"20",X"C8",X"7E", + X"E6",X"9F",X"77",X"01",X"06",X"00",X"09",X"11",X"33",X"20",X"CD",X"91",X"10",X"23",X"23",X"23", + X"23",X"1A",X"13",X"77",X"23",X"1A",X"13",X"77",X"23",X"13",X"13",X"13",X"1A",X"13",X"3C",X"77", + X"23",X"1A",X"13",X"77",X"23",X"C9",X"3A",X"0B",X"20",X"AE",X"E6",X"10",X"C0",X"7E",X"E6",X"20", + X"C8",X"7E",X"E6",X"40",X"C2",X"B9",X"10",X"36",X"00",X"01",X"05",X"00",X"09",X"5E",X"23",X"56", + X"23",X"EB",X"CD",X"C8",X"10",X"0E",X"1F",X"09",X"1A",X"13",X"77",X"23",X"1A",X"13",X"77",X"C9", + X"7E",X"E6",X"20",X"C8",X"23",X"01",X"05",X"00",X"09",X"5E",X"23",X"56",X"23",X"7B",X"B2",X"C8", + X"D5",X"5E",X"23",X"56",X"09",X"E3",X"CD",X"F6",X"10",X"E1",X"5E",X"23",X"56",X"23",X"7B",X"B2", + X"C8",X"D5",X"5E",X"23",X"56",X"E1",X"01",X"20",X"00",X"E5",X"7B",X"36",X"00",X"23",X"3D",X"C2", + X"FB",X"10",X"E1",X"09",X"15",X"C2",X"F9",X"10",X"C9",X"21",X"33",X"20",X"5E",X"23",X"56",X"23", + X"7A",X"B3",X"C8",X"D5",X"7E",X"23",X"D3",X"01",X"5E",X"23",X"56",X"23",X"4E",X"23",X"46",X"23", + X"E3",X"E6",X"08",X"CC",X"94",X"11",X"C4",X"EB",X"11",X"E1",X"C3",X"0C",X"11",X"7E",X"E6",X"40", + X"C8",X"7E",X"E6",X"BF",X"F6",X"20",X"77",X"E6",X"08",X"47",X"23",X"23",X"5E",X"23",X"7B",X"E6", + X"07",X"05",X"FA",X"46",X"11",X"2F",X"32",X"35",X"20",X"32",X"3C",X"20",X"56",X"23",X"CD",X"D9", + X"11",X"EB",X"22",X"33",X"20",X"EB",X"D5",X"CD",X"B3",X"11",X"23",X"23",X"23",X"23",X"E5",X"21", + X"36",X"20",X"CD",X"87",X"11",X"E1",X"C1",X"5E",X"23",X"7B",X"A7",X"C8",X"16",X"00",X"3E",X"05", + X"EB",X"29",X"3D",X"C2",X"71",X"11",X"09",X"EB",X"7E",X"23",X"83",X"5F",X"EB",X"22",X"3A",X"20", + X"EB",X"CD",X"B3",X"11",X"21",X"3D",X"20",X"73",X"23",X"72",X"23",X"71",X"23",X"70",X"23",X"AF", + X"77",X"23",X"77",X"C9",X"C5",X"E5",X"1A",X"13",X"D3",X"02",X"DB",X"03",X"77",X"23",X"0D",X"C2", + X"96",X"11",X"AF",X"D3",X"02",X"DB",X"03",X"77",X"E1",X"01",X"20",X"00",X"09",X"C1",X"05",X"C2", + X"94",X"11",X"C9",X"5E",X"23",X"E5",X"16",X"00",X"21",X"01",X"03",X"19",X"19",X"5E",X"23",X"56", + X"EB",X"E3",X"5E",X"23",X"E3",X"16",X"00",X"19",X"19",X"5E",X"23",X"56",X"E1",X"EB",X"4E",X"23", + X"46",X"23",X"EB",X"C9",X"7B",X"E6",X"07",X"D3",X"01",X"06",X"03",X"AF",X"7A",X"1F",X"57",X"7B", + X"1F",X"5F",X"05",X"C2",X"DB",X"11",X"7A",X"C6",X"24",X"57",X"C9",X"79",X"85",X"6F",X"C5",X"E5", + X"1A",X"13",X"D3",X"02",X"DB",X"03",X"77",X"2B",X"0D",X"C2",X"F0",X"11",X"AF",X"D3",X"02",X"DB", + X"03",X"77",X"E1",X"01",X"20",X"00",X"09",X"C1",X"05",X"C2",X"EE",X"11",X"C9",X"3A",X"0B",X"20", + X"AE",X"E6",X"10",X"C0",X"7E",X"E6",X"40",X"C8",X"7E",X"F6",X"20",X"77",X"23",X"23",X"5E",X"23", + X"23",X"56",X"23",X"CD",X"D4",X"11",X"73",X"23",X"72",X"23",X"EB",X"CD",X"32",X"12",X"01",X"1F", + X"00",X"09",X"7E",X"12",X"13",X"3E",X"03",X"D3",X"02",X"DB",X"03",X"B6",X"77",X"23",X"7E",X"12", + X"13",X"AF",X"D3",X"02",X"DB",X"03",X"B6",X"77",X"C9",X"F3",X"E1",X"01",X"00",X"00",X"11",X"00", + X"00",X"31",X"20",X"40",X"3E",X"10",X"C5",X"13",X"BA",X"C2",X"56",X"12",X"31",X"00",X"24",X"E9", + X"7E",X"A7",X"F0",X"E6",X"04",X"01",X"00",X"00",X"11",X"04",X"FC",X"CA",X"71",X"12",X"11",X"06", + X"FA",X"23",X"7E",X"E6",X"0F",X"CA",X"A9",X"12",X"1F",X"D2",X"7D",X"12",X"42",X"1F",X"D2",X"82", + X"12",X"43",X"1F",X"D2",X"87",X"12",X"4A",X"1F",X"D2",X"8C",X"12",X"4B",X"79",X"0E",X"00",X"23", + X"A7",X"C4",X"D0",X"12",X"23",X"78",X"A7",X"C4",X"C6",X"12",X"2B",X"2B",X"79",X"A7",X"CA",X"A9", + X"12",X"2B",X"7E",X"E6",X"ED",X"F6",X"60",X"77",X"C9",X"2B",X"7E",X"E6",X"02",X"C2",X"A2",X"12", + X"54",X"5D",X"01",X"0C",X"00",X"09",X"7E",X"FE",X"08",X"C8",X"36",X"08",X"EB",X"7E",X"E6",X"10", + X"C0",X"7E",X"F6",X"70",X"77",X"C9",X"86",X"FE",X"11",X"D8",X"FE",X"B4",X"D0",X"77",X"0C",X"C9", + X"86",X"E5",X"F5",X"23",X"23",X"23",X"5E",X"16",X"00",X"7D",X"FE",X"60",X"21",X"60",X"1A",X"CA", + X"E5",X"12",X"21",X"6A",X"1A",X"19",X"19",X"5E",X"23",X"56",X"F1",X"E1",X"BB",X"D8",X"BA",X"D0", + X"77",X"0C",X"C9",X"21",X"5B",X"20",X"7E",X"A7",X"F2",X"10",X"13",X"CD",X"39",X"13",X"11",X"46", + X"1A",X"3A",X"5C",X"20",X"CD",X"50",X"13",X"21",X"98",X"19",X"CD",X"99",X"13",X"22",X"65",X"20", + X"21",X"6D",X"20",X"7E",X"A7",X"F2",X"2D",X"13",X"CD",X"39",X"13",X"11",X"53",X"1A",X"3A",X"6E", + X"20",X"CD",X"50",X"13",X"21",X"A4",X"19",X"CD",X"99",X"13",X"22",X"77",X"20",X"21",X"7F",X"20", + X"7E",X"A7",X"F0",X"CD",X"39",X"13",X"23",X"71",X"C9",X"23",X"23",X"22",X"50",X"20",X"23",X"7E", + X"23",X"EB",X"21",X"73",X"19",X"01",X"FF",X"00",X"0C",X"BE",X"23",X"DA",X"48",X"13",X"EB",X"C9", + X"1F",X"1F",X"1F",X"1F",X"E6",X"0F",X"C2",X"5B",X"13",X"3E",X"01",X"77",X"23",X"F5",X"E5",X"46", + X"71",X"CD",X"7A",X"13",X"E1",X"F1",X"11",X"08",X"00",X"42",X"19",X"71",X"FE",X"0B",X"FA",X"73", + X"13",X"0E",X"05",X"2B",X"7E",X"A7",X"C0",X"36",X"08",X"C9",X"21",X"2C",X"1A",X"78",X"BE",X"C2", + X"8F",X"13",X"23",X"79",X"BE",X"C2",X"90",X"13",X"1A",X"2A",X"50",X"20",X"86",X"77",X"C9",X"23", + X"23",X"13",X"7D",X"FE",X"06",X"C2",X"7D",X"13",X"C9",X"09",X"09",X"5E",X"23",X"56",X"EB",X"C9", + X"3A",X"43",X"20",X"A7",X"C0",X"21",X"91",X"20",X"CD",X"BD",X"13",X"21",X"9C",X"20",X"CD",X"BD", + X"13",X"21",X"A7",X"20",X"CD",X"F0",X"13",X"21",X"B2",X"20",X"C3",X"F0",X"13",X"7E",X"A7",X"F0", + X"CD",X"95",X"14",X"C8",X"CD",X"6C",X"14",X"FE",X"07",X"F8",X"CD",X"5A",X"14",X"FE",X"0A",X"F8", + X"D6",X"09",X"21",X"90",X"19",X"FE",X"04",X"FA",X"A0",X"14",X"21",X"6E",X"20",X"3E",X"30",X"77", + X"32",X"5C",X"20",X"23",X"7E",X"FE",X"DE",X"DA",X"EC",X"13",X"36",X"DE",X"AF",X"C3",X"1F",X"14", + X"7E",X"A7",X"F0",X"CD",X"95",X"14",X"C8",X"CD",X"6C",X"14",X"FE",X"0A",X"F0",X"CD",X"5A",X"14", + X"FE",X"07",X"F0",X"D6",X"03",X"FE",X"01",X"21",X"8A",X"19",X"F2",X"A0",X"14",X"21",X"5C",X"20", + X"3E",X"30",X"77",X"32",X"6E",X"20",X"23",X"7E",X"FE",X"30",X"DA",X"1F",X"14",X"36",X"30",X"32", + X"55",X"20",X"AF",X"32",X"25",X"20",X"32",X"27",X"20",X"32",X"28",X"20",X"32",X"57",X"20",X"32", + X"58",X"20",X"32",X"22",X"20",X"3C",X"32",X"49",X"20",X"32",X"45",X"20",X"32",X"24",X"20",X"32", + X"43",X"20",X"3A",X"0A",X"20",X"A7",X"C8",X"3E",X"04",X"32",X"26",X"20",X"3A",X"55",X"20",X"A7", + X"3E",X"48",X"CA",X"57",X"14",X"3E",X"88",X"D3",X"03",X"C9",X"7E",X"E6",X"BF",X"77",X"11",X"07", + X"00",X"19",X"AF",X"77",X"23",X"77",X"23",X"77",X"23",X"77",X"78",X"C9",X"E5",X"23",X"23",X"7E", + X"E5",X"21",X"81",X"19",X"06",X"01",X"04",X"04",X"04",X"BE",X"23",X"D2",X"76",X"14",X"E1",X"23", + X"23",X"7E",X"21",X"85",X"19",X"11",X"88",X"19",X"05",X"13",X"23",X"BE",X"DA",X"88",X"14",X"EB", + X"96",X"4F",X"78",X"E1",X"C9",X"E5",X"11",X"07",X"00",X"19",X"7E",X"23",X"23",X"B6",X"E1",X"C9", + X"23",X"23",X"3D",X"C2",X"A0",X"14",X"5E",X"23",X"56",X"2E",X"01",X"61",X"EB",X"C3",X"F6",X"10", + X"21",X"86",X"20",X"11",X"0B",X"00",X"19",X"E5",X"CD",X"C3",X"14",X"E1",X"7D",X"FE",X"B2",X"C2", + X"B3",X"14",X"C9",X"7E",X"A7",X"F0",X"23",X"23",X"7E",X"FE",X"08",X"DA",X"E4",X"14",X"FE",X"F8", + X"D2",X"E4",X"14",X"23",X"23",X"7E",X"FE",X"10",X"DA",X"DE",X"14",X"FE",X"CC",X"D8",X"2B",X"7E", + X"2F",X"3C",X"77",X"C9",X"2B",X"2B",X"7E",X"E6",X"BF",X"77",X"C9",X"21",X"6D",X"20",X"11",X"0D", + X"20",X"CD",X"FA",X"14",X"21",X"5B",X"20",X"11",X"0E",X"20",X"7E",X"A7",X"F0",X"E6",X"01",X"C8", + X"23",X"23",X"23",X"7E",X"FE",X"17",X"D0",X"AF",X"32",X"45",X"20",X"2B",X"2B",X"7E",X"E6",X"0F", + X"F6",X"E0",X"77",X"2B",X"7E",X"E6",X"FE",X"77",X"3E",X"02",X"32",X"22",X"20",X"3A",X"0A",X"20", + X"A7",X"C8",X"1A",X"3C",X"27",X"12",X"C3",X"24",X"1C",X"3A",X"09",X"20",X"D6",X"05",X"F8",X"C2", + X"2C",X"15",X"2A",X"4C",X"20",X"7D",X"FE",X"20",X"D2",X"3E",X"15",X"21",X"23",X"1A",X"46",X"2B", + X"22",X"4C",X"20",X"3A",X"5C",X"20",X"E6",X"0F",X"CA",X"4F",X"15",X"78",X"32",X"67",X"20",X"3A", + X"6E",X"20",X"E6",X"0F",X"C8",X"78",X"32",X"79",X"20",X"C9",X"3A",X"57",X"20",X"A7",X"CA",X"70", + X"15",X"DB",X"00",X"47",X"DB",X"00",X"21",X"20",X"20",X"11",X"B0",X"19",X"B8",X"CC",X"82",X"15", + X"3A",X"58",X"20",X"A7",X"C8",X"DB",X"01",X"47",X"DB",X"01",X"21",X"21",X"20",X"11",X"C0",X"19", + X"B8",X"C0",X"E5",X"2F",X"F5",X"0F",X"0F",X"0F",X"0F",X"E6",X"07",X"4F",X"06",X"00",X"21",X"B4", + X"15",X"09",X"F1",X"E6",X"8F",X"B6",X"E1",X"AE",X"C8",X"4F",X"06",X"01",X"79",X"0F",X"DA",X"AA", + X"15",X"4F",X"78",X"07",X"47",X"13",X"13",X"C3",X"9C",X"15",X"78",X"AE",X"77",X"A0",X"EB",X"4E", + X"23",X"66",X"69",X"E9",X"30",X"70",X"40",X"50",X"20",X"50",X"60",X"10",X"21",X"5B",X"20",X"11", + X"20",X"20",X"C3",X"CB",X"15",X"21",X"6D",X"20",X"11",X"21",X"20",X"7E",X"F6",X"02",X"77",X"1A", + X"E6",X"7F",X"23",X"77",X"C9",X"C8",X"21",X"91",X"20",X"7E",X"A7",X"F2",X"E4",X"15",X"21",X"9C", + X"20",X"7E",X"A7",X"F8",X"11",X"59",X"20",X"1A",X"FE",X"07",X"F0",X"D5",X"3C",X"12",X"11",X"04", + X"00",X"19",X"E5",X"21",X"28",X"1E",X"11",X"A2",X"3E",X"CD",X"30",X"01",X"21",X"5F",X"20",X"5E", + X"16",X"00",X"2B",X"E5",X"21",X"CC",X"19",X"06",X"18",X"3A",X"0A",X"20",X"A7",X"CA",X"18",X"16", + X"78",X"D3",X"03",X"3E",X"04",X"32",X"26",X"20",X"19",X"19",X"19",X"19",X"5E",X"23",X"56",X"23", + X"4E",X"23",X"46",X"E1",X"7E",X"80",X"47",X"2B",X"7E",X"81",X"4F",X"E1",X"70",X"2B",X"72",X"2B", + X"71",X"2B",X"73",X"2B",X"36",X"C0",X"D1",X"1A",X"FE",X"06",X"C0",X"3C",X"12",X"13",X"7B",X"FE", + X"5A",X"CA",X"46",X"16",X"1B",X"1B",X"06",X"0A",X"3A",X"11",X"20",X"A7",X"CA",X"51",X"16",X"06", + X"05",X"1A",X"FE",X"06",X"FA",X"59",X"16",X"06",X"02",X"78",X"32",X"25",X"20",X"32",X"4A",X"20", + X"C9",X"C8",X"21",X"A7",X"20",X"7E",X"A7",X"F2",X"70",X"16",X"21",X"B2",X"20",X"7E",X"A7",X"F8", + X"11",X"5A",X"20",X"1A",X"FE",X"07",X"F0",X"D5",X"3C",X"12",X"11",X"04",X"00",X"19",X"E5",X"21", + X"28",X"1E",X"11",X"B8",X"3E",X"CD",X"30",X"01",X"21",X"71",X"20",X"5E",X"16",X"00",X"2B",X"E5", + X"21",X"E8",X"19",X"06",X"28",X"C3",X"09",X"16",X"21",X"0C",X"20",X"DB",X"02",X"2F",X"47",X"DB", + X"02",X"2F",X"B8",X"C0",X"E6",X"40",X"47",X"AE",X"C8",X"70",X"78",X"A7",X"C8",X"3E",X"0C",X"D3", + X"03",X"01",X"64",X"00",X"D3",X"04",X"05",X"C2",X"B4",X"16",X"0D",X"C2",X"B4",X"16",X"3E",X"08", + X"D3",X"03",X"21",X"12",X"20",X"34",X"21",X"BA",X"1D",X"CD",X"87",X"1C",X"3A",X"0A",X"20",X"A7", + X"C0",X"21",X"E7",X"1A",X"22",X"06",X"20",X"31",X"00",X"24",X"C3",X"7E",X"0F",X"3A",X"44",X"20", + X"A7",X"C8",X"11",X"08",X"20",X"01",X"29",X"20",X"CD",X"44",X"1C",X"21",X"29",X"20",X"11",X"0F", + X"24",X"3E",X"02",X"C3",X"30",X"01",X"21",X"7F",X"20",X"7E",X"A7",X"F0",X"23",X"23",X"23",X"7E", + X"FE",X"17",X"D2",X"08",X"17",X"3E",X"B6",X"77",X"EB",X"21",X"72",X"19",X"01",X"77",X"19",X"23", + X"03",X"BE",X"DA",X"0F",X"17",X"EB",X"0A",X"2B",X"77",X"C9",X"21",X"4B",X"20",X"7E",X"A7",X"C8", + X"36",X"00",X"1F",X"F5",X"DC",X"54",X"17",X"F1",X"1F",X"F5",X"DC",X"A8",X"17",X"F1",X"1F",X"F5", + X"DC",X"4F",X"17",X"F1",X"1F",X"F5",X"DC",X"49",X"18",X"F1",X"1F",X"F5",X"DC",X"8A",X"18",X"F1", + X"1F",X"DC",X"1B",X"19",X"1F",X"F5",X"DC",X"10",X"19",X"F1",X"1F",X"DC",X"23",X"19",X"C9",X"3E", + X"08",X"D3",X"03",X"C9",X"21",X"13",X"20",X"06",X"08",X"7E",X"07",X"07",X"07",X"AE",X"17",X"17", + X"21",X"13",X"20",X"7E",X"17",X"77",X"23",X"7E",X"17",X"77",X"05",X"C2",X"59",X"17",X"F6",X"02", + X"E6",X"1F",X"32",X"28",X"20",X"E6",X"07",X"4F",X"06",X"00",X"21",X"74",X"1A",X"09",X"46",X"21", + X"5E",X"20",X"7E",X"FE",X"A0",X"DA",X"8A",X"17",X"06",X"01",X"FE",X"18",X"D2",X"91",X"17",X"06", + X"02",X"2B",X"7E",X"FE",X"38",X"DA",X"9A",X"17",X"06",X"04",X"FE",X"10",X"D2",X"A1",X"17",X"06", + X"08",X"2B",X"7E",X"E6",X"F0",X"B0",X"77",X"C9",X"3A",X"09",X"20",X"F6",X"20",X"32",X"27",X"20", + X"AF",X"CD",X"C2",X"17",X"32",X"5F",X"20",X"21",X"5C",X"20",X"7E",X"E6",X"0F",X"B0",X"77",X"C3", + X"D5",X"15",X"F5",X"21",X"5D",X"20",X"4E",X"23",X"5E",X"21",X"6F",X"20",X"46",X"23",X"56",X"CD", + X"EF",X"17",X"C6",X"14",X"21",X"7A",X"1A",X"23",X"23",X"BE",X"23",X"DA",X"D7",X"17",X"F1",X"A7", + X"CA",X"E4",X"17",X"23",X"7E",X"4F",X"17",X"17",X"17",X"17",X"E6",X"F0",X"47",X"79",X"C9",X"7A", + X"93",X"C8",X"5F",X"9F",X"57",X"21",X"00",X"00",X"3E",X"06",X"19",X"3D",X"C2",X"FA",X"17",X"7C"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/roms/romg.cpu b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/roms/romg.cpu new file mode 100644 index 0000000000000000000000000000000000000000..ca1ef588ef704157d501e7f228ca071508291abb GIT binary patch literal 2048 zcmbVMO>Epm6n^9J?l?`@@%}V8A?$jy6+fYrB@mP*&hAzeRTUB`h(pDtK}D!1y0>gf z@On`dKthp#OAm;IQ;t+zs5l^#Alj{JRLG@=QaO}1LanI#1924B!*iBGp=ptr`QG!) z``(+GH!~hM13rZG82H48G4LQ@VO_xLdJRcPq~sp>mya8iL;4>+)gTwLd-}Lu56*SB zaVq|+esN6mI_~gk3y4pTP>uDlX*xxYlTVlw*|2)VB`(;2LeYjfdGrMPm?dbOzC%k~ z;*Y=qs6j~fV%9Y%LV)c$oscJ#3DtxRd0OWagA*_T8}ckH*O9vmUki8$cjdKW0<$Ck zgHP^Ne7PnSX@DnmTRb!2GMpmslW$=^d`BcUiCNa5ika%TD-!ZPxa1U>f(4kSQX&IS zg8>4z!X$n*)FG6~h%_RPz@04a7A+@6AgUX%B;@6FZUZ(EP!sOO;=CKjDq1|C8?f?L zX;L!C5fb3Z+=?YJ^R@ouIEj@8HMNSp>O=Wu(ya|fWoYQDW5@ip;o;%3v2H*`HY*yI z?(CVpwOUtKE*teUjc`>}wLR5LCewp0Ri!;RizSFFm?t>G7r8&NobwjA*Whl0*$rwf z5MemO=juvBQnKxLze`H z2>v!;#_%#&0j-4Wz$z_a&a;AA0{5tuO_Weo&|=7n0WXH@@VV|WXu)P+F#rUG3I&S- zaH;FoeKcSj?zd6ViheHoM?$hf&eH{Up8u44I|orsKnIE;rEkSV5re9RFNO(+;2OC` zTfe<1@0SI=Wn=ZFm5`Y~?VLfo-;S%`e zy6SR~_Jqhqf;*s4B?I^af#HGhcNoEFDC!7s3sk|`W(l}o6My+x_v)x8>Ikq4659mb zcB5wV(JsZvED zm1J!8U8(Y+tnZfemld^7)&~`}NA|Ad{1x76x9lySmVYa@HBM_x!ZpJb%gc?%a#VzH zeoG|V_3mFqYW{Mz3=V-=xbhEQx?R`mi#!`8J-lz0F zY(JhvZ){v}PODB^a>;p9b&hl{egE~?D8XW^ z*$3z{zm-Rwp-uXny-1tahWW*Me@rj*g1+zo@27eJ<3{==y+rzD-HhxP>ufX*`8^M| znTxT4xfpLg30s`qsn6o+BCl1iuYA9VM|^}NY1tS!oY@n}6Wynv=l`4_vQ zA==Es>j!^vuBV*t`<>rAolBW$87G`qHakCdHuF<@vK_iEIA{10xdLJJ2ZzU1^V6f_ sZ-t-Ff61HXoL4XlQ{(HZnSUN9uy^I#^nv+|`b>7{Iel(Eq2?9+4;@L&cmMzZ literal 0 HcmV?d00001 diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/roms/romg.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/roms/romg.vhd new file mode 100644 index 00000000..1c8074d2 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/roms/romg.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity romg is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of romg is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"D8",X"00",X"F8",X"00",X"FE",X"03",X"B8",X"00",X"F8",X"01",X"F8",X"00",X"60",X"00",X"F0", + X"00",X"FC",X"07",X"FE",X"7F",X"FF",X"00",X"F9",X"00",X"F9",X"00",X"F9",X"00",X"FE",X"01",X"FE", + X"01",X"02",X"11",X"50",X"00",X"D8",X"00",X"F8",X"00",X"FE",X"03",X"B8",X"00",X"F8",X"01",X"F8", + X"00",X"60",X"00",X"F0",X"E0",X"FC",X"3F",X"FE",X"03",X"FF",X"00",X"F9",X"00",X"F9",X"00",X"F9", + X"00",X"FE",X"01",X"FE",X"01",X"02",X"11",X"50",X"00",X"D8",X"00",X"F8",X"00",X"FE",X"03",X"B8", + X"00",X"F8",X"01",X"F8",X"00",X"60",X"00",X"F0",X"70",X"FC",X"1F",X"FE",X"07",X"FF",X"00",X"F9", + X"00",X"F9",X"00",X"F9",X"00",X"FE",X"01",X"FE",X"01",X"02",X"11",X"50",X"00",X"D8",X"00",X"F8", + X"00",X"FE",X"03",X"B8",X"00",X"F8",X"01",X"F8",X"00",X"60",X"E0",X"F0",X"1C",X"FC",X"07",X"FE", + X"03",X"FF",X"00",X"F9",X"00",X"F9",X"00",X"F9",X"00",X"FE",X"01",X"FE",X"01",X"02",X"11",X"50", + X"00",X"D8",X"00",X"F8",X"00",X"FE",X"03",X"B8",X"40",X"F8",X"61",X"F8",X"30",X"60",X"18",X"F0", + X"0C",X"FC",X"07",X"FE",X"03",X"FF",X"00",X"F9",X"00",X"F9",X"00",X"F9",X"00",X"FE",X"01",X"FE", + X"01",X"02",X"09",X"FC",X"01",X"F8",X"03",X"98",X"03",X"18",X"07",X"1C",X"07",X"8E",X"03",X"86", + X"01",X"C7",X"01",X"9E",X"07",X"02",X"09",X"FC",X"01",X"F8",X"01",X"F8",X"01",X"F0",X"01",X"E0", + X"01",X"E0",X"00",X"C0",X"00",X"E0",X"00",X"C0",X"03",X"02",X"09",X"FC",X"00",X"F8",X"01",X"F0", + X"03",X"C8",X"07",X"9C",X"07",X"0E",X"03",X"06",X"03",X"87",X"03",X"3E",X"0F",X"02",X"0F",X"28", + X"00",X"68",X"00",X"78",X"00",X"FE",X"01",X"58",X"00",X"F8",X"00",X"78",X"00",X"30",X"00",X"FC", + X"00",X"FE",X"01",X"7F",X"03",X"79",X"04",X"79",X"08",X"79",X"10",X"7E",X"00",X"02",X"0F",X"28", + X"00",X"68",X"00",X"78",X"00",X"FE",X"01",X"58",X"00",X"F8",X"00",X"78",X"00",X"30",X"00",X"FC", + X"00",X"FE",X"03",X"7F",X"0F",X"79",X"38",X"79",X"00",X"79",X"00",X"7E",X"00",X"02",X"0F",X"28", + X"00",X"68",X"00",X"78",X"00",X"FE",X"01",X"58",X"00",X"F8",X"00",X"78",X"00",X"30",X"00",X"FC", + X"07",X"FE",X"3F",X"7F",X"00",X"79",X"00",X"79",X"00",X"79",X"00",X"7E",X"00",X"02",X"0F",X"28", + X"00",X"68",X"00",X"78",X"00",X"FE",X"01",X"58",X"00",X"F8",X"00",X"78",X"00",X"30",X"78",X"FC", + X"0F",X"FE",X"00",X"7F",X"00",X"79",X"00",X"79",X"00",X"79",X"00",X"7E",X"00",X"02",X"0F",X"28", + X"00",X"68",X"00",X"78",X"00",X"FE",X"01",X"58",X"00",X"F8",X"00",X"78",X"18",X"30",X"0E",X"FC", + X"07",X"FE",X"01",X"7F",X"00",X"79",X"00",X"79",X"00",X"79",X"00",X"7E",X"00",X"02",X"0F",X"28", + X"00",X"68",X"00",X"78",X"00",X"FE",X"01",X"58",X"00",X"F8",X"00",X"78",X"18",X"30",X"0E",X"FC", + X"07",X"FE",X"01",X"7F",X"00",X"79",X"00",X"79",X"00",X"79",X"00",X"7E",X"00",X"02",X"0F",X"28", + X"00",X"68",X"00",X"78",X"00",X"FE",X"11",X"58",X"08",X"F8",X"04",X"78",X"02",X"30",X"03",X"FC", + X"01",X"FE",X"01",X"7F",X"00",X"79",X"00",X"79",X"00",X"79",X"00",X"7E",X"00",X"02",X"07",X"7E", + X"00",X"EC",X"00",X"CC",X"01",X"8C",X"01",X"C6",X"00",X"63",X"00",X"CE",X"01",X"02",X"07",X"7C", + X"00",X"78",X"00",X"78",X"00",X"70",X"00",X"30",X"00",X"20",X"00",X"E0",X"00",X"02",X"07",X"7E", + X"00",X"F8",X"00",X"E0",X"01",X"CC",X"01",X"86",X"00",X"C3",X"00",X"8E",X"03",X"02",X"0E",X"14", + X"00",X"34",X"00",X"3C",X"00",X"FF",X"00",X"2C",X"00",X"7C",X"00",X"3C",X"00",X"18",X"00",X"7C", + X"00",X"FE",X"00",X"3F",X"01",X"3D",X"02",X"3D",X"04",X"3D",X"00",X"02",X"0E",X"14",X"00",X"34", + X"00",X"3C",X"00",X"FF",X"00",X"2C",X"00",X"7C",X"00",X"3C",X"00",X"18",X"00",X"FC",X"00",X"FE", + X"03",X"3F",X"0E",X"3D",X"00",X"3D",X"00",X"3D",X"00",X"02",X"0E",X"14",X"00",X"34",X"00",X"3C", + X"00",X"FF",X"00",X"2C",X"00",X"7C",X"00",X"3C",X"00",X"18",X"00",X"FC",X"01",X"FE",X"0F",X"3F", + X"00",X"3D",X"00",X"3D",X"00",X"3D",X"00",X"02",X"0E",X"14",X"00",X"34",X"00",X"3C",X"00",X"FF", + X"00",X"2C",X"00",X"7C",X"00",X"3C",X"00",X"18",X"0E",X"FC",X"03",X"7E",X"00",X"3F",X"00",X"3D", + X"00",X"3D",X"00",X"3D",X"00",X"02",X"0E",X"14",X"00",X"34",X"00",X"3C",X"00",X"FF",X"00",X"2C", + X"00",X"7C",X"00",X"3C",X"00",X"18",X"0E",X"FC",X"03",X"FE",X"00",X"3F",X"00",X"3D",X"00",X"3D", + X"00",X"3D",X"00",X"02",X"0E",X"14",X"00",X"34",X"00",X"3C",X"00",X"FF",X"00",X"2C",X"00",X"7C", + X"00",X"3C",X"08",X"18",X"06",X"FC",X"03",X"FE",X"00",X"3F",X"00",X"3D",X"00",X"3D",X"00",X"3D", + X"00",X"02",X"0E",X"14",X"00",X"34",X"00",X"3C",X"00",X"FF",X"04",X"2C",X"02",X"7C",X"02",X"3C", + X"01",X"98",X"01",X"FC",X"00",X"7E",X"00",X"3F",X"00",X"3D",X"00",X"3D",X"00",X"3D",X"00",X"01", + X"05",X"7E",X"64",X"32",X"11",X"77",X"01",X"05",X"3E",X"38",X"18",X"10",X"70",X"01",X"05",X"7E", + X"70",X"26",X"21",X"E7",X"01",X"1A",X"18",X"38",X"38",X"38",X"38",X"38",X"3A",X"3A",X"BE",X"B8", + X"B8",X"F8",X"FB",X"3B",X"3B",X"3B",X"3F",X"3C",X"38",X"38",X"38",X"38",X"38",X"38",X"38",X"38", + X"01",X"15",X"08",X"18",X"18",X"18",X"18",X"1A",X"1E",X"D8",X"58",X"78",X"78",X"19",X"19",X"1F", + X"1E",X"18",X"18",X"18",X"18",X"18",X"18",X"01",X"0F",X"10",X"10",X"10",X"18",X"50",X"70",X"14", + X"14",X"14",X"1C",X"10",X"10",X"10",X"10",X"10",X"03",X"1C",X"00",X"7E",X"00",X"80",X"FF",X"01", + X"E0",X"FF",X"07",X"F0",X"FF",X"0F",X"F0",X"FF",X"0F",X"F8",X"FF",X"1F",X"F8",X"FF",X"1F",X"F8", + X"FF",X"1F",X"F8",X"E7",X"1F",X"F0",X"C3",X"0F",X"F0",X"81",X"0F",X"E0",X"81",X"07",X"C0",X"81", + X"03",X"80",X"C3",X"01",X"F0",X"FF",X"0F",X"E0",X"FF",X"07",X"E0",X"FF",X"07",X"F4",X"FF",X"2F", + X"84",X"C3",X"21",X"04",X"81",X"20",X"04",X"81",X"20",X"06",X"81",X"60",X"F7",X"FF",X"EF",X"06", + X"81",X"60",X"04",X"00",X"20",X"04",X"00",X"20",X"04",X"00",X"20",X"04",X"00",X"20",X"03",X"19", + X"00",X"1E",X"00",X"80",X"7F",X"00",X"C0",X"FF",X"00",X"E0",X"FF",X"01",X"F0",X"FF",X"03",X"F0", + X"FF",X"03",X"F8",X"F3",X"07",X"F8",X"E1",X"07",X"F8",X"C0",X"07",X"F0",X"C0",X"03",X"E0",X"C0", + X"01",X"C0",X"E1",X"00",X"80",X"7F",X"00",X"F0",X"FF",X"03",X"E0",X"FF",X"01",X"E0",X"FF",X"01", + X"F4",X"FF",X"0B",X"C4",X"E1",X"08",X"84",X"40",X"08",X"86",X"40",X"18",X"F7",X"FF",X"3B",X"86", + X"40",X"18",X"04",X"00",X"08",X"04",X"00",X"08",X"04",X"00",X"08",X"02",X"13",X"E0",X"03",X"F8", + X"0F",X"FC",X"1F",X"7C",X"1F",X"3E",X"3E",X"1E",X"3C",X"1E",X"3C",X"3C",X"1E",X"F8",X"0F",X"F0", + X"07",X"FC",X"1F",X"F8",X"0F",X"FD",X"5F",X"39",X"4E",X"11",X"44",X"FD",X"5F",X"11",X"44",X"01", + X"40",X"01",X"40",X"02",X"0F",X"C0",X"01",X"F0",X"07",X"F8",X"0F",X"78",X"0F",X"3C",X"1E",X"38", + X"0E",X"70",X"07",X"E0",X"03",X"F8",X"0F",X"F0",X"07",X"3A",X"2E",X"12",X"24",X"FB",X"6F",X"02", + X"20",X"02",X"20",X"02",X"0B",X"20",X"00",X"F8",X"00",X"FC",X"01",X"DE",X"03",X"8E",X"03",X"DC", + X"01",X"F8",X"00",X"DC",X"01",X"89",X"04",X"FD",X"05",X"01",X"04",X"03",X"20",X"04",X"00",X"00", + X"19",X"02",X"00",X"7A",X"01",X"00",X"FC",X"00",X"00",X"7E",X"05",X"00",X"FE",X"03",X"80",X"FC", + X"03",X"40",X"FE",X"07",X"68",X"F9",X"03",X"3E",X"F0",X"FF",X"0F",X"A0",X"FF",X"03",X"80",X"FF", + X"00",X"80",X"FF",X"00",X"C0",X"FF",X"00",X"E0",X"FF",X"00",X"E0",X"FF",X"01",X"70",X"FF",X"03", + X"30",X"FE",X"07",X"30",X"FC",X"0F",X"30",X"FE",X"0F",X"30",X"FE",X"0F",X"30",X"F8",X"0F",X"20", + X"F0",X"07",X"00",X"F0",X"07",X"00",X"F0",X"07",X"00",X"C0",X"07",X"00",X"80",X"07",X"00",X"00", + X"07",X"00",X"00",X"03",X"00",X"40",X"03",X"00",X"80",X"03",X"00",X"00",X"0F",X"02",X"19",X"14", + X"00",X"34",X"00",X"3C",X"00",X"FF",X"00",X"3C",X"00",X"2E",X"00",X"7E",X"00",X"3C",X"40",X"18", + X"30",X"F8",X"1F",X"FC",X"07",X"FE",X"01",X"FE",X"01",X"F7",X"01",X"E3",X"03",X"C3",X"07",X"E3", + X"0F",X"E2",X"1F",X"82",X"1F",X"00",X"1F",X"00",X"1F",X"00",X"0E",X"00",X"0C",X"00",X"0E",X"00", + X"3C",X"02",X"13",X"14",X"00",X"34",X"00",X"3C",X"00",X"FF",X"00",X"2E",X"00",X"7E",X"00",X"38", + X"10",X"18",X"0C",X"FC",X"07",X"7E",X"00",X"7A",X"00",X"F2",X"01",X"F2",X"01",X"E0",X"03",X"E0", + X"03",X"C0",X"01",X"80",X"01",X"C0",X"01",X"80",X"07",X"04",X"0B",X"A0",X"00",X"00",X"00",X"B0", + X"01",X"00",X"00",X"B0",X"01",X"3C",X"00",X"F0",X"01",X"7E",X"00",X"F9",X"13",X"FF",X"00",X"FF", + X"9F",X"FF",X"81",X"F8",X"C7",X"FF",X"9F",X"FC",X"FF",X"FF",X"FF",X"FE",X"FF",X"FF",X"FF",X"00", + X"00",X"FC",X"41",X"00",X"00",X"00",X"20",X"04",X"09",X"80",X"02",X"00",X"00",X"C0",X"06",X"00", + X"00",X"C0",X"07",X"1C",X"00",X"C8",X"27",X"3E",X"00",X"F8",X"3F",X"7F",X"10",X"E0",X"0F",X"FF", + X"13",X"F0",X"FF",X"FF",X"1F",X"F0",X"FF",X"FF",X"1F",X"00",X"00",X"7E",X"08",X"03",X"08",X"14", + X"00",X"00",X"34",X"00",X"00",X"3C",X"F0",X"00",X"FF",X"F8",X"41",X"3C",X"FC",X"4F",X"FE",X"FF", + X"7F",X"FE",X"FF",X"7F",X"00",X"E0",X"23",X"03",X"08",X"A0",X"00",X"00",X"A0",X"01",X"00",X"E0", + X"C1",X"01",X"F8",X"E7",X"43",X"E0",X"F1",X"4F",X"F0",X"FF",X"7F",X"F0",X"FF",X"7F",X"00",X"C0", + X"23",X"02",X"07",X"0A",X"00",X"1A",X"00",X"1E",X"00",X"7F",X"8E",X"1E",X"9F",X"FF",X"FF",X"00", + X"40",X"02",X"16",X"01",X"04",X"08",X"1E",X"3C",X"0F",X"F8",X"4F",X"FC",X"07",X"FE",X"07",X"7F", + X"0F",X"FE",X"3F",X"FC",X"7F",X"F0",X"3F",X"F9",X"39",X"F8",X"7F",X"D0",X"3F",X"FC",X"0F",X"FC", + X"47",X"FE",X"07",X"FF",X"0D",X"E4",X"1F",X"C2",X"3F",X"C9",X"77",X"80",X"03",X"80",X"21",X"06", + X"24",X"30",X"00",X"00",X"00",X"00",X"0C",X"F0",X"01",X"00",X"00",X"80",X"0F",X"F0",X"1F",X"00", + X"00",X"F8",X"0F",X"E0",X"FF",X"FF",X"FF",X"FF",X"07",X"E0",X"FF",X"FF",X"FF",X"FF",X"07",X"E0", + X"FF",X"FF",X"FF",X"FF",X"07",X"C0",X"FF",X"FF",X"FF",X"FF",X"03",X"C0",X"FF",X"FF",X"FF",X"FF", + X"03",X"C0",X"FF",X"FF",X"FF",X"FF",X"03",X"80",X"FF",X"FF",X"FF",X"FF",X"01",X"80",X"FF",X"FF", + X"FF",X"FF",X"01",X"80",X"FF",X"FF",X"FF",X"FF",X"01",X"00",X"FF",X"FF",X"FF",X"FF",X"00",X"00", + X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"FF",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"FF",X"FF",X"FF",X"FF",X"03",X"C0",X"FF",X"FF", + X"FF",X"FF",X"03",X"C0",X"FF",X"FF",X"FF",X"FF",X"03",X"C0",X"FF",X"FF",X"FF",X"FF",X"03",X"00", + X"7C",X"00",X"00",X"3E",X"00",X"00",X"93",X"01",X"80",X"C9",X"00",X"80",X"10",X"02",X"40",X"08", + X"01",X"40",X"11",X"05",X"A0",X"88",X"02",X"40",X"92",X"04",X"20",X"49",X"02",X"20",X"54",X"08", + X"10",X"2A",X"04",X"20",X"38",X"08",X"10",X"1C",X"04",X"F0",X"EF",X"1F",X"F8",X"F7",X"0F",X"20", + X"38",X"08",X"10",X"1C",X"04",X"20",X"54",X"08",X"10",X"2A",X"04",X"40",X"92",X"04",X"20",X"49", + X"02",X"40",X"11",X"05",X"A0",X"88",X"02",X"80",X"10",X"02",X"40",X"08",X"01",X"00",X"93",X"01", + X"80",X"C9",X"00",X"00",X"7C",X"00",X"00",X"3E",X"00",X"01",X"0F",X"18",X"3C",X"7E",X"FF",X"E7", + X"E7",X"81",X"81",X"E7",X"E7",X"E7",X"E7",X"E7",X"FF",X"FF",X"CD",X"F5",X"0E",X"11",X"0B",X"20", + X"1A",X"EE",X"FF",X"12",X"C2",X"EC",X"0E",X"CD",X"40",X"10",X"CD",X"E6",X"0F",X"C3",X"EC",X"0E", + X"3A",X"0B",X"20",X"A7",X"CA",X"DE",X"0E",X"CD",X"40",X"10",X"CD",X"A0",X"13",X"CD",X"B7",X"0F", + X"CD",X"B0",X"14",X"CD",X"29",X"15",X"CD",X"63",X"10",X"22",X"52",X"20",X"CD",X"60",X"12",X"21", + X"00",X"00",X"22",X"33",X"20",X"2A",X"52",X"20",X"CD",X"2D",X"11",X"C3",X"EC",X"0E",X"2A",X"52", + X"20",X"E5",X"CD",X"D0",X"10",X"CD",X"09",X"11",X"E1",X"CD",X"7B",X"10",X"CD",X"98",X"16",X"E1", + X"D1",X"C1",X"F1",X"FB",X"C9",X"21",X"02",X"20",X"7E",X"A7",X"CA",X"FF",X"0E",X"35",X"C9",X"23", + X"7E",X"A7",X"CA",X"0C",X"0F",X"35",X"2B",X"3A",X"05",X"20",X"77",X"C9",X"23",X"7E",X"A7",X"CA", + X"18",X"0F",X"35",X"3E",X"00",X"D3",X"05",X"C9",X"2A",X"00",X"20",X"7E",X"A7",X"C2",X"2C",X"0F", + X"3E",X"00",X"D3",X"05",X"3A",X"0A",X"20",X"A7",X"C0",X"D3",X"03",X"C9",X"F2",X"3B",X"0F",X"E6", + X"7F",X"32",X"05",X"20",X"23",X"22",X"00",X"20",X"C3",X"1B",X"0F",X"32",X"03",X"20",X"23",X"3A", + X"05",X"20",X"3D",X"32",X"02",X"20",X"3E",X"01",X"32",X"04",X"20",X"7E",X"23",X"22",X"00",X"20", + X"E6",X"7F",X"07",X"4F",X"06",X"00",X"21",X"50",X"1D",X"09",X"7E",X"D3",X"05",X"23",X"7E",X"D3", + X"06",X"C9",X"31",X"00",X"24",X"CD",X"49",X"12",X"AF",X"06",X"13",X"11",X"00",X"20",X"12",X"13", + X"05",X"C2",X"6E",X"0F",X"3D",X"12",X"13",X"12",X"21",X"91",X"1A",X"22",X"06",X"20",X"21",X"7E", + X"0F",X"E5",X"FB",X"D3",X"04",X"2A",X"06",X"20",X"7E",X"A7",X"CA",X"9F",X"0F",X"23",X"22",X"06", + X"20",X"EB",X"21",X"51",X"19",X"07",X"4F",X"06",X"00",X"09",X"7E",X"23",X"66",X"6F",X"E9",X"CD", + X"F3",X"12",X"CD",X"1A",X"17",X"CD",X"F6",X"16",X"CD",X"EB",X"14",X"3A",X"0A",X"20",X"A7",X"C8", + X"CD",X"5A",X"15",X"CD",X"DD",X"16",X"C9",X"21",X"86",X"20",X"11",X"0B",X"00",X"19",X"E5",X"CD", + X"D8",X"0F",X"E1",X"01",X"EF",X"00",X"FE",X"70",X"D2",X"CD",X"0F",X"06",X"10",X"7E",X"A1",X"B0", + X"77",X"7D",X"FE",X"B2",X"C2",X"BA",X"0F",X"C9",X"7E",X"A7",X"F0",X"23",X"7E",X"23",X"86",X"77", + X"23",X"7E",X"23",X"86",X"77",X"C9",X"21",X"4B",X"20",X"7E",X"A7",X"C0",X"47",X"21",X"09",X"20", + X"35",X"C2",X"14",X"10",X"36",X"1E",X"3A",X"45",X"20",X"A7",X"C2",X"0E",X"10",X"21",X"08",X"20"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/roms/romh.cpu b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/roms/romh.cpu new file mode 100644 index 0000000000000000000000000000000000000000..b46c0406dc14e9f503a1db6c07e33570a8f01da9 GIT binary patch literal 2048 zcmbVLUuauZ82?UAa&PYK&Ash1X*xr0%7&~IS%!Pa^ya4Ew(P;-eCmVBGQpq^&J0=q z%Wp%R@ZW(KpF-VQYq@=l?bDIu)5K_N$ z?mg#z-|zQ3zw?CvOwM4t8&+=IzHfi5uCHIKbH2sS@++Evx&V41KI6}mFUl!+{?sBG zEj|O^4B9EUd}Mo}IZ%88X8iqyrd~b?40E)FIl?hV8D?bH@Wt}JR`vwX4zsMikFhwt z{3(p=x>!Ef0({5;=NMpe*ggp(V&<3aaPo5bM|e>0g1ErEz+Sa;vhTO=VAqzg8Qc;M z6|X>`I0^PPv>SG?I&-Z0C*NiAnbB(_#XE4nS4Tb9&4KdY{3?5TccLEB+ZXQ{UI;5J z%pKnre+8C!8sZnqj2}#x!CMJ5<7bjk9_Y#Zeig1AJebKGIIw@;3fX>PbvK$#{CNmv z!f!9?#RF*TR(~;t?A_@8ZKK(-I*4Y4-s1?#Af<{gqX#Gsro6H(JS;7zim#!c7s6~! zpzjTm^MV+WXv7P{V7Y9;6a+%}E;*9T5rcyW$+9q6#UwmucsrIiSS6oGMxu(s_4vc8 z{9VXq3kE!j2v0JdT+VDg#AGRf1!M3W4`LF+&hQ*;>;%EX4Gl4zhw-q6vEi9JW8qbY z%vj7E%6YO}nh@JwT5{bv+qQGLW5)<#GM-CM$vc;@)4VfyDo0-8UI-WAIKeD%WkS|Z zi$pvS$9Z1Z!hA6CIoDlU;%BgKu3y#LaTf1TGO98!)C&MgJCm&_Wbg}k6u*fl@QZjH zzluM?pW!cYAASm_u#V5F8{>3nWArQi$^;uz${$L1C>0tE9S`m7ARRw+R6D}T6rK%S z5g!KEB%i-axGRRF$K_}J&k1YdlhR)K9se1jH+V=IlyCTp!v5eJ(g|4ztO>6NC!`PL zOdu&v1iz9l$?pZ;5-$aBNk7S-2hNH&g7ea>d@XQZyc>Kd&C9o>dFdgm&C2sKehdO& zg}kZ3&GS%mfp!B;104gZgQWwAU};cGLt_l4T~u;$N$)P{YDwR^nvVY;0kNdVN_xJe z!)h8fCE%iIS1ajbjJiJC6$n~drRM4lSDSWQ)J+Ib5R;as)LgCM;!O)sOV5L7SejOI zaf4r>JqH#|AEskjswXTx31ZaJ)S4@L4$z|punp^hPpPCUX(vTT>2bP17o2Q9zh_S} zS*h@flcqW!phFCzpg;&zFj^d)YV1cg=_zLQ3X1Mohmfa&}4UQhw69U7aWY8aZIO>bC3Vqc!wGL--dm1 zP0VX~H6KkxlS))o1XVO*KDmKwxWWcy!@?G#$P&FQs(^!T;!i|X6z~}w(|lcr;SSVT l+pj_m)gTKMXyB&k3U#F(smGhBiT(qlxkf!(hdQ({{{W7Lu;~B* literal 0 HcmV?d00001 diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/roms/romh.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/roms/romh.vhd new file mode 100644 index 00000000..d1853f40 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/roms/romh.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity romh is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of romh is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"AF",X"D3",X"03",X"C3",X"17",X"00",X"F5",X"C5",X"D5",X"E5",X"C3",X"9A",X"0E",X"00", + X"F5",X"C5",X"D5",X"E5",X"C3",X"B0",X"0E",X"DB",X"02",X"E6",X"10",X"CA",X"62",X"0F",X"06",X"01", + X"11",X"00",X"00",X"21",X"00",X"20",X"D3",X"04",X"70",X"7E",X"A8",X"CA",X"3D",X"00",X"4F",X"7D", + X"E6",X"01",X"79",X"C2",X"3B",X"00",X"B2",X"57",X"C3",X"3D",X"00",X"B3",X"5F",X"23",X"7C",X"FE", + X"40",X"C2",X"26",X"00",X"D3",X"04",X"2B",X"7C",X"FE",X"1F",X"CA",X"7A",X"00",X"7E",X"A8",X"CA", + X"61",X"00",X"4F",X"7D",X"E6",X"01",X"79",X"C2",X"5F",X"00",X"B2",X"57",X"C3",X"61",X"00",X"B3", + X"5F",X"78",X"2F",X"77",X"AE",X"CA",X"44",X"00",X"4F",X"7D",X"E6",X"01",X"79",X"C2",X"75",X"00", + X"B2",X"57",X"C3",X"77",X"00",X"B3",X"5F",X"C3",X"44",X"00",X"D3",X"04",X"23",X"7C",X"FE",X"40", + X"CA",X"9D",X"00",X"78",X"2F",X"AE",X"CA",X"98",X"00",X"4F",X"7D",X"E6",X"01",X"79",X"C2",X"96", + X"00",X"B2",X"57",X"C3",X"98",X"00",X"B3",X"5F",X"AF",X"77",X"C3",X"7A",X"00",X"78",X"07",X"47", + X"D2",X"23",X"00",X"7A",X"B3",X"CA",X"CC",X"00",X"EB",X"F9",X"11",X"00",X"20",X"06",X"00",X"21", + X"00",X"00",X"39",X"0E",X"10",X"AF",X"29",X"DA",X"BB",X"00",X"2F",X"12",X"13",X"3E",X"08",X"12", + X"13",X"0D",X"C2",X"B5",X"00",X"05",X"C2",X"AF",X"00",X"C3",X"1A",X"01",X"31",X"00",X"24",X"21", + X"00",X"00",X"11",X"00",X"00",X"0E",X"04",X"AF",X"86",X"D3",X"04",X"23",X"47",X"79",X"BC",X"78", + X"C2",X"D8",X"00",X"E5",X"21",X"1F",X"01",X"19",X"BE",X"3E",X"40",X"CA",X"F7",X"00",X"21",X"00", + X"20",X"34",X"21",X"28",X"01",X"19",X"7E",X"21",X"29",X"20",X"19",X"77",X"E1",X"13",X"0C",X"0C", + X"0C",X"0C",X"3E",X"24",X"B9",X"C2",X"D7",X"00",X"21",X"29",X"20",X"3A",X"00",X"20",X"A7",X"CA", + X"00",X"00",X"11",X"08",X"30",X"3E",X"08",X"CD",X"30",X"01",X"D3",X"04",X"C3",X"1A",X"01",X"00", + X"CA",X"40",X"19",X"47",X"E8",X"B8",X"00",X"BC",X"48",X"48",X"47",X"47",X"46",X"46",X"45",X"44", + X"F5",X"7E",X"23",X"A7",X"FA",X"31",X"01",X"D6",X"30",X"F2",X"4D",X"01",X"47",X"13",X"7B",X"E6", + X"1F",X"C2",X"46",X"01",X"14",X"14",X"04",X"C2",X"3D",X"01",X"C3",X"31",X"01",X"E5",X"D5",X"3C", + X"FE",X"0B",X"FA",X"57",X"01",X"D6",X"06",X"21",X"71",X"01",X"01",X"0A",X"00",X"09",X"3D",X"C2", + X"5D",X"01",X"EB",X"01",X"20",X"00",X"3E",X"0A",X"F5",X"1A",X"13",X"77",X"09",X"F1",X"3D",X"C2", + X"68",X"01",X"D1",X"E1",X"13",X"F1",X"3D",X"C2",X"30",X"01",X"C9",X"3C",X"7E",X"66",X"66",X"66", + X"66",X"66",X"66",X"7E",X"3C",X"18",X"1C",X"18",X"18",X"18",X"18",X"18",X"18",X"3C",X"3C",X"3C", + X"7E",X"66",X"60",X"7C",X"3E",X"06",X"06",X"7E",X"7E",X"3C",X"7E",X"66",X"60",X"38",X"78",X"60", + X"66",X"7E",X"3C",X"66",X"66",X"66",X"66",X"7E",X"7E",X"60",X"60",X"60",X"60",X"3E",X"3E",X"06", + X"06",X"3E",X"7E",X"60",X"66",X"7E",X"3C",X"3C",X"3E",X"06",X"06",X"3E",X"7E",X"66",X"66",X"7E", + X"3C",X"7E",X"7E",X"60",X"70",X"30",X"38",X"18",X"1C",X"0C",X"0C",X"3C",X"7E",X"66",X"66",X"3C", + X"7E",X"66",X"66",X"7E",X"3C",X"3C",X"7E",X"66",X"66",X"7E",X"7C",X"60",X"60",X"7C",X"3C",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"18",X"3C",X"7E",X"66",X"66",X"66",X"7E", + X"7E",X"66",X"66",X"3E",X"7E",X"66",X"66",X"3E",X"7E",X"66",X"66",X"7E",X"3E",X"3C",X"7E",X"66", + X"06",X"06",X"06",X"06",X"66",X"7E",X"3C",X"3E",X"7E",X"66",X"66",X"66",X"66",X"66",X"66",X"7E", + X"3E",X"7E",X"7E",X"06",X"06",X"3E",X"3E",X"06",X"06",X"7E",X"7E",X"7E",X"7E",X"06",X"06",X"3E", + X"3E",X"06",X"06",X"06",X"06",X"3C",X"7E",X"66",X"06",X"06",X"76",X"76",X"66",X"7E",X"3C",X"66", + X"66",X"66",X"66",X"7E",X"7E",X"66",X"66",X"66",X"66",X"3C",X"3C",X"18",X"18",X"18",X"18",X"18", + X"18",X"3C",X"3C",X"60",X"60",X"60",X"60",X"60",X"60",X"60",X"66",X"7E",X"3C",X"66",X"66",X"76", + X"3E",X"1E",X"1E",X"3E",X"76",X"66",X"66",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"7E", + X"7E",X"C3",X"C3",X"E7",X"E7",X"FF",X"FF",X"DB",X"C3",X"C3",X"C3",X"66",X"66",X"6E",X"6E",X"7E", + X"7E",X"76",X"76",X"66",X"66",X"3C",X"7E",X"66",X"66",X"66",X"66",X"66",X"66",X"7E",X"3C",X"3E", + X"7E",X"66",X"66",X"7E",X"3E",X"06",X"06",X"06",X"06",X"3C",X"7E",X"66",X"66",X"66",X"66",X"66", + X"66",X"7E",X"5C",X"3E",X"7E",X"66",X"66",X"7E",X"3E",X"76",X"66",X"66",X"66",X"3C",X"7E",X"66", + X"06",X"3E",X"7C",X"60",X"66",X"7E",X"3C",X"7E",X"7E",X"18",X"18",X"18",X"18",X"18",X"18",X"18", + X"18",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"7E",X"3C",X"66",X"66",X"66",X"66",X"66", + X"7E",X"3C",X"3C",X"18",X"18",X"C3",X"C3",X"C3",X"DB",X"FF",X"FF",X"E7",X"E7",X"C3",X"C3",X"66", + X"66",X"7E",X"3C",X"18",X"18",X"3C",X"7E",X"66",X"66",X"66",X"66",X"7E",X"3C",X"18",X"18",X"18", + X"18",X"18",X"18",X"7E",X"7E",X"60",X"70",X"38",X"1C",X"0E",X"06",X"7E",X"7E",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"00",X"00",X"C0",X"C0",X"10",X"38",X"38",X"38",X"38",X"38",X"38",X"38",X"38", + X"7C",X"47",X"03",X"51",X"03",X"79",X"03",X"6F",X"03",X"8D",X"03",X"5B",X"03",X"83",X"03",X"65", + X"03",X"97",X"03",X"A1",X"03",X"AB",X"03",X"29",X"03",X"33",X"03",X"3D",X"03",X"1F",X"03",X"89", + X"0E",X"89",X"0E",X"89",X"0E",X"89",X"0E",X"89",X"0E",X"81",X"0D",X"81",X"0D",X"81",X"0D",X"81", + X"0D",X"81",X"0D",X"2B",X"0C",X"2B",X"0C",X"8D",X"0C",X"8D",X"0C",X"C1",X"0C",X"E9",X"0C",X"17", + X"0D",X"3D",X"0D",X"57",X"0D",X"71",X"0D",X"28",X"0B",X"7E",X"0B",X"CB",X"0B",X"F3",X"0B",X"13", + X"0C",X"C1",X"03",X"D6",X"05",X"B5",X"07",X"ED",X"08",X"FD",X"09",X"02",X"04",X"11",X"06",X"D9", + X"07",X"0D",X"09",X"1B",X"0A",X"43",X"04",X"4C",X"06",X"FD",X"07",X"2D",X"09",X"39",X"0A",X"84", + X"04",X"87",X"06",X"21",X"08",X"4D",X"09",X"57",X"0A",X"C5",X"04",X"C2",X"06",X"45",X"08",X"6D", + X"09",X"75",X"0A",X"06",X"05",X"FD",X"06",X"69",X"08",X"8D",X"09",X"93",X"0A",X"47",X"05",X"38", + X"07",X"8D",X"08",X"AD",X"09",X"B1",X"0A",X"88",X"05",X"73",X"07",X"B1",X"08",X"CD",X"09",X"CF", + X"0A",X"A2",X"05",X"89",X"07",X"C5",X"08",X"DD",X"09",X"D6",X"0A",X"BC",X"05",X"9F",X"07",X"D9", + X"08",X"ED",X"09",X"DD",X"0A",X"CD",X"09",X"DD",X"09",X"ED",X"09",X"CF",X"0A",X"D6",X"0A",X"DD", + X"0A",X"03",X"15",X"00",X"05",X"00",X"80",X"0D",X"00",X"80",X"0D",X"00",X"80",X"0F",X"00",X"C8", + X"9F",X"00",X"F8",X"FF",X"00",X"C0",X"17",X"00",X"C0",X"3F",X"00",X"C0",X"7F",X"00",X"C0",X"1F", + X"00",X"80",X"1F",X"00",X"00",X"07",X"00",X"80",X"0F",X"00",X"F8",X"3F",X"00",X"FC",X"7F",X"00", + X"CE",X"FF",X"01",X"C6",X"FF",X"03",X"C6",X"1F",X"17",X"C6",X"1F",X"0E",X"C6",X"1F",X"14",X"FA", + X"3F",X"20",X"03",X"15",X"00",X"05",X"00",X"80",X"0D",X"00",X"80",X"0D",X"00",X"80",X"0F",X"00", + X"C8",X"9F",X"00",X"F8",X"FF",X"00",X"C0",X"17",X"00",X"C0",X"3F",X"00",X"C0",X"7F",X"00",X"C0", + X"1F",X"00",X"80",X"1F",X"00",X"00",X"07",X"00",X"80",X"0F",X"00",X"F8",X"3F",X"00",X"FC",X"7F", + X"00",X"CE",X"FF",X"01",X"C6",X"FF",X"07",X"C6",X"1F",X"1E",X"C6",X"1F",X"70",X"C6",X"1F",X"00", + X"FA",X"3F",X"00",X"03",X"15",X"00",X"05",X"00",X"80",X"0D",X"00",X"80",X"0D",X"00",X"80",X"0F", + X"00",X"C8",X"9F",X"00",X"F8",X"FF",X"00",X"C0",X"17",X"00",X"C0",X"3F",X"00",X"C0",X"7F",X"00", + X"C0",X"1F",X"00",X"80",X"1F",X"00",X"00",X"07",X"00",X"80",X"0F",X"00",X"F8",X"3F",X"00",X"FC", + X"FF",X"01",X"CE",X"FF",X"0F",X"C6",X"1F",X"7F",X"C6",X"1F",X"00",X"C6",X"1F",X"00",X"C6",X"1F", + X"00",X"FA",X"3F",X"00",X"03",X"15",X"00",X"05",X"00",X"80",X"0D",X"00",X"80",X"0D",X"00",X"80", + X"0F",X"00",X"C8",X"9F",X"00",X"F8",X"FF",X"00",X"C0",X"17",X"00",X"C0",X"3F",X"00",X"C0",X"7F", + X"00",X"C0",X"1F",X"00",X"80",X"1F",X"00",X"00",X"07",X"08",X"80",X"0F",X"F0",X"F8",X"FF",X"1F", + X"FC",X"FF",X"0F",X"CE",X"FF",X"00",X"C6",X"1F",X"00",X"C6",X"1F",X"00",X"C6",X"1F",X"00",X"C6", + X"1F",X"00",X"FA",X"3F",X"00",X"03",X"15",X"00",X"05",X"00",X"80",X"0D",X"00",X"80",X"0D",X"00", + X"80",X"0F",X"00",X"C8",X"9F",X"00",X"F8",X"FF",X"00",X"C0",X"17",X"00",X"C0",X"3F",X"00",X"C0", + X"7F",X"00",X"C0",X"1F",X"00",X"80",X"1F",X"C0",X"00",X"07",X"38",X"80",X"0F",X"0C",X"F8",X"FF", + X"0F",X"FC",X"FF",X"03",X"CE",X"FF",X"00",X"C6",X"1F",X"00",X"C6",X"1F",X"00",X"C6",X"1F",X"00", + X"C6",X"1F",X"00",X"FA",X"3F",X"00",X"03",X"15",X"00",X"05",X"00",X"80",X"0D",X"00",X"80",X"0D", + X"00",X"80",X"0F",X"00",X"C8",X"9F",X"00",X"F8",X"FF",X"00",X"C0",X"17",X"00",X"C0",X"3F",X"00", + X"C0",X"7F",X"00",X"C0",X"1F",X"C0",X"80",X"1F",X"70",X"00",X"07",X"3C",X"80",X"0F",X"0F",X"F8", + X"FF",X"03",X"FC",X"FF",X"01",X"CE",X"FF",X"00",X"C6",X"1F",X"00",X"C6",X"1F",X"00",X"C6",X"1F", + X"00",X"C6",X"1F",X"00",X"FA",X"3F",X"00",X"03",X"15",X"00",X"05",X"00",X"80",X"0D",X"00",X"80", + X"0D",X"00",X"80",X"0F",X"00",X"C8",X"9F",X"00",X"F8",X"FF",X"00",X"C0",X"17",X"80",X"C0",X"3F", + X"50",X"C0",X"7F",X"60",X"C0",X"1F",X"30",X"80",X"1F",X"38",X"00",X"07",X"1C",X"80",X"0F",X"0E", + X"F8",X"FF",X"07",X"FC",X"FF",X"03",X"CE",X"FF",X"01",X"C6",X"1F",X"00",X"C6",X"1F",X"00",X"C6", + X"1F",X"00",X"C6",X"1F",X"00",X"FA",X"3F",X"00",X"02",X"0C",X"F0",X"3F",X"F0",X"3F",X"E0",X"3D", + X"C0",X"79",X"C0",X"71",X"C0",X"E1",X"C0",X"E1",X"E0",X"60",X"70",X"70",X"34",X"34",X"38",X"38", + X"F0",X"F0",X"02",X"0C",X"F0",X"3F",X"E0",X"3F",X"C0",X"1F",X"C0",X"1F",X"C0",X"1F",X"00",X"1F", + X"00",X"1E",X"00",X"1C",X"00",X"0C",X"00",X"0D",X"00",X"0E",X"00",X"3C",X"02",X"0C",X"F0",X"3F", + X"F0",X"3F",X"E0",X"1F",X"C0",X"0F",X"80",X"1F",X"00",X"3E",X"C0",X"7D",X"E0",X"78",X"70",X"30", + X"34",X"34",X"38",X"38",X"F0",X"F0",X"03",X"13",X"40",X"01",X"00",X"60",X"03",X"00",X"E0",X"03", + X"00",X"F4",X"17",X"00",X"FC",X"1F",X"00",X"E0",X"02",X"00",X"E0",X"0F",X"00",X"E0",X"03",X"00", + X"E0",X"03",X"00",X"C0",X"01",X"00",X"E0",X"03",X"00",X"FC",X"0F",X"00",X"FE",X"3F",X"00",X"F3", + X"7F",X"00",X"F3",X"E3",X"02",X"F3",X"C3",X"01",X"F1",X"83",X"02",X"FE",X"03",X"04",X"FC",X"07", + X"00",X"03",X"13",X"40",X"01",X"00",X"60",X"03",X"00",X"E0",X"03",X"00",X"F4",X"17",X"00",X"FC", + X"1F",X"00",X"E0",X"02",X"00",X"E0",X"0F",X"00",X"E0",X"03",X"00",X"E0",X"03",X"00",X"C0",X"01", + X"00",X"E0",X"03",X"00",X"FC",X"0F",X"00",X"FE",X"1F",X"00",X"F3",X"7F",X"00",X"F3",X"E3",X"01", + X"F3",X"03",X"07",X"F1",X"03",X"00",X"FE",X"03",X"00",X"FC",X"07",X"00",X"03",X"13",X"40",X"01", + X"00",X"60",X"03",X"00",X"E0",X"03",X"00",X"F4",X"17",X"00",X"FC",X"1F",X"00",X"E0",X"02",X"00", + X"E0",X"0F",X"00",X"E0",X"03",X"00",X"E0",X"03",X"00",X"C0",X"01",X"00",X"E0",X"03",X"00",X"FC", + X"1F",X"00",X"FE",X"FF",X"00",X"F3",X"FF",X"07",X"F3",X"03",X"00",X"F3",X"03",X"00",X"F1",X"03", + X"00",X"FE",X"03",X"00",X"FC",X"07",X"00",X"03",X"13",X"40",X"01",X"00",X"60",X"03",X"00",X"E0", + X"03",X"00",X"F4",X"17",X"00",X"FC",X"1F",X"00",X"E0",X"02",X"00",X"E0",X"0F",X"00",X"E0",X"03", + X"00",X"E0",X"03",X"00",X"C0",X"01",X"01",X"E0",X"03",X"1E",X"FC",X"FF",X"03",X"FE",X"FF",X"03", + X"F3",X"0F",X"00",X"F3",X"03",X"00",X"F3",X"03",X"00",X"F1",X"03",X"00",X"FE",X"03",X"00",X"FC", + X"07",X"00",X"03",X"13",X"40",X"01",X"00",X"60",X"03",X"00",X"E0",X"03",X"00",X"F4",X"17",X"00", + X"FC",X"1F",X"00",X"E0",X"02",X"00",X"E0",X"0F",X"00",X"E0",X"03",X"00",X"E0",X"03",X"0C",X"C0", + X"81",X"03",X"E0",X"C3",X"00",X"FC",X"FF",X"00",X"FE",X"3F",X"00",X"F3",X"0F",X"00",X"F3",X"03", + X"00",X"F3",X"03",X"00",X"F1",X"03",X"00",X"FE",X"03",X"00",X"FC",X"07",X"00",X"03",X"13",X"40", + X"01",X"00",X"60",X"03",X"00",X"E0",X"03",X"00",X"F4",X"17",X"00",X"FC",X"1F",X"00",X"E0",X"02", + X"00",X"E0",X"0F",X"00",X"E0",X"03",X"00",X"E0",X"03",X"06",X"C0",X"C1",X"03",X"E0",X"F3",X"00", + X"FC",X"3F",X"00",X"FE",X"1F",X"00",X"F3",X"0F",X"00",X"F3",X"03",X"00",X"F3",X"03",X"00",X"F1", + X"03",X"00",X"FE",X"03",X"00",X"FC",X"07",X"00",X"03",X"13",X"40",X"01",X"00",X"60",X"03",X"00", + X"E0",X"03",X"00",X"F4",X"17",X"00",X"FC",X"1F",X"00",X"E0",X"02",X"04",X"E0",X"8F",X"06",X"E0", + X"03",X"03",X"E0",X"83",X"03",X"C0",X"C1",X"01",X"E0",X"E3",X"00",X"FC",X"7F",X"00",X"FE",X"3F", + X"00",X"F3",X"1F",X"00",X"F3",X"03",X"00",X"F3",X"03",X"00",X"F1",X"03",X"00",X"FE",X"03",X"00", + X"FC",X"07",X"00",X"02",X"0A",X"F8",X"07",X"70",X"0F",X"70",X"0E",X"70",X"1C",X"30",X"1C",X"38", + X"0C",X"1C",X"0E",X"0C",X"06",X"0E",X"07",X"3C",X"1E",X"02",X"0A",X"FC",X"03",X"F8",X"03",X"F0", + X"03",X"F0",X"03",X"C0",X"03",X"C0",X"03",X"80",X"03",X"80",X"01",X"C0",X"01",X"80",X"07",X"02", + X"0A",X"FC",X"03",X"F8",X"01",X"F0",X"00",X"E0",X"01",X"C8",X"03",X"9C",X"07",X"0E",X"07",X"06", + X"03",X"87",X"03",X"1E",X"0F",X"02",X"11",X"50",X"00",X"D8",X"00",X"F8",X"00",X"FE",X"03",X"B8", + X"00",X"F8",X"01",X"F8",X"00",X"60",X"00",X"F0",X"00",X"FC",X"03",X"FE",X"07",X"FF",X"06",X"F9", + X"0C",X"F9",X"18",X"F9",X"20",X"FE",X"01",X"FE",X"01",X"02",X"11",X"50",X"00",X"D8",X"00",X"F8", + X"00",X"FE",X"03",X"B8",X"00",X"F8",X"01",X"F8",X"00",X"60",X"00",X"F0",X"00",X"FC",X"03",X"FE", + X"0F",X"FF",X"3C",X"F9",X"60",X"F9",X"00",X"F9",X"00",X"FE",X"01",X"FE",X"01",X"02",X"11",X"50"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/spram.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/spram.vhd new file mode 100644 index 00000000..d8043481 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/spram.vhd @@ -0,0 +1,55 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY spram IS + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clken : IN STD_LOGIC := '1'; + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END spram; + + +ARCHITECTURE SYN OF spram IS + +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "NORMAL", + clock_enable_output_a => "BYPASS", + intended_device_family => "Cyclone III", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + width_a => data_width_g, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + clocken0 => clken, + data_a => data, + wren_a => wren, + q_a => q + ); + + + +END SYN; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/sprom.vhd new file mode 100644 index 00000000..a81ac959 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Boothill_MiST/rtl/sprom.vhd @@ -0,0 +1,82 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY sprom IS + GENERIC + ( + init_file : string := ""; + widthad_a : natural; + width_a : natural := 8; + outdata_reg_a : string := "UNREGISTERED" + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); +END sprom; + + +ARCHITECTURE SYN OF sprom IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + address_aclr_a : STRING; + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + clock0 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(width_a-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_aclr_a => "NONE", + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => init_file, + intended_device_family => "Cyclone III", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2**widthad_a, + operation_mode => "ROM", + outdata_aclr_a => "NONE", + outdata_reg_a => outdata_reg_a, + widthad_a => widthad_a, + width_a => width_a, + width_byteena_a => 1 + ) + PORT MAP ( + clock0 => clock, + address_a => address, + q_a => sub_wire0 + ); + + + +END SYN; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/OzmaWars.qpf b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/OzmaWars.qpf new file mode 100644 index 00000000..7344eeb5 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/OzmaWars.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition +# Date created = 16:15:41 June 05, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "16:15:41 June 05, 2019" + +# Revisions + +PROJECT_REVISION = "OzmaWars" diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/OzmaWars.qsf b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/OzmaWars.qsf new file mode 100644 index 00000000..cb54b9ca --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/OzmaWars.qsf @@ -0,0 +1,180 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition +# Date created = 02:57:11 June 09, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# OzmaWars_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39 NOVEMBER 20, 2017" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/OzmaWars_mist.sv +set_global_assignment -name VHDL_FILE rtl/invaders.vhd +set_global_assignment -name VHDL_FILE rtl/mw8080.vhd +set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/OzmaWars_memory.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/sprom.vhd +set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd +set_global_assignment -name VHDL_FILE rtl/pll.vhd +set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip +set_global_assignment -name QIP_FILE "D:/Github/Mist_FPGA/common/mist/mist.qip" +set_global_assignment -name VHDL_FILE rtl/roms/mw01.vhd +set_global_assignment -name VHDL_FILE rtl/roms/mw02.vhd +set_global_assignment -name VHDL_FILE rtl/roms/mw03.vhd +set_global_assignment -name VHDL_FILE rtl/roms/mw04.vhd +set_global_assignment -name VHDL_FILE rtl/roms/mw05.vhd +set_global_assignment -name VHDL_FILE rtl/roms/mw06.vhd +set_global_assignment -name VHDL_FILE rtl/OzmaWars_overlay.vhd + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name TOP_LEVEL_ENTITY OzmaWars_mist +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# EDA Netlist Writer Assignments +# ============================== +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" + +# Assembler Assignments +# ===================== +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# start EDA_TOOL_SETTINGS(eda_simulation) +# --------------------------------------- + + # EDA Netlist Writer Assignments + # ============================== + set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation + +# end EDA_TOOL_SETTINGS(eda_simulation) +# ------------------------------------- + +# --------------------------- +# start ENTITY(OzmaWars_mist) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(OzmaWars_mist) +# ------------------------- +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/README.txt b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/README.txt new file mode 100644 index 00000000..9db1c4bb --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/README.txt @@ -0,0 +1,27 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Ozma Wars port to MiST by Gehstock +-- 08 June 2019 +-- +--------------------------------------------------------------------------------- +-- +-- Midway 8080 Hardware +-- Audio based on work by Paul Walsh. +-- Audio and scan converter by MikeJ. +--------------------------------------------------------------------------------- +-- +-- +-- Keyboard inputs : +-- +-- F1 : Start +-- SPACE : Fire +-- RIGHT/LEFT : Movement +-- +-- Joystick support. +-- +-- +--------------------------------------------------------------------------------- + +ToDo 60Hz + Color + diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/Release/OzmaWars.rbf b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/Release/OzmaWars.rbf new file mode 100644 index 0000000000000000000000000000000000000000..e0d5851720355b326efabe89fc1e1be120bb0891 GIT binary patch literal 250660 zcmeFa51bs=Rp(nhsW@$A;&gY~Ls?Pm?n#d`isM)gCQq<@a8;{XZrc+)60>4H;C+@9 z**IB(=k{BrpDhN&J=tJH-1oY#`R)5mvx_EE5MDK0xe{&t_ql zxD~>pBm}?j@7$`H)@bx+q%o`Dxzco1-GArLJ@?#m&b`(B;)^Fv@BT+ifB)^j|JJv@ z)jjgf@BGs@kG%NpZ+`Q|Z+-ip|LMq)?;QCj5=Gy7?PVwK=wE%QN9vGzuex7Or^f+5 zOTDf0yfe9~zapvk+6!a;eGV(n4@og8&(~GYi%sgMH|6~w@0!EQ%hgse^L$+wi-YR- z;-LGy|KnYAczLxmai`LpWkxlIyIx}TqV^YeSv@2#i))R*S<3Q|75b2!4IpQJjIB=s{wN=eFB`45vM z$Hz4lIT@ZUY=Zz`xG9!%deta_qr-yN%zXjlk##ra(Mat$mz{tr>kTjPdQ#W4Jyy+P=Dg%eWW`` z2T6ZI%HbUE`Wz`Q%i-&~nN-V?;PfVC>-j&Crbu;?a8sKnNqN4?^!yiD(tV!tJYD~a z)cZU-FYP6X=Sq?XcULOqIB8BODL?0j=3G9vG>7yop6IHi`|&Kf9GCa!q-RMgnuo@y z`tOCW=bs^cgCtz^oTrawN%@iu@l^7kkKJvgd_J6Lt~`^aysrAm@!Cidyd0B{#Z|zBM%hDi8w<^+oo_;G!dVVuW*N>CLhu+l78|8n6l$VP?ca!pG zT{VA|gpbBtDWA8x3Kxx!;OY87l2B2ZGZF#=fB^;EOr<38N@*IAC)f$`6h55V@Z0SxV-AjMGlk`=RWKHX@ zu9C?-Ne3zEIlty*x@wN?BB{STU-Py%sjN4N_TFcQ(Hu^~TX^K@6Is%;aFmQ{9tobV zkCKF&?(?KP>7+cZSs;mLf|aLxNzxbjv(}>=w}q}xk?tZ%K2@&uDbG{>V;K5o{5;{I^u8>;u_xv5d#}P@ zDbEugl6^yt56P^a^VB;}7rIyQ;{}q&KTpD^2aN@9AI_5SPz9l{ev~cz#QR=&IX=4f z=Fh*+amdxY_?p`w(w}*fUR9Efrlfp5YpvQu8pzVeNP3ptq3ak)IOwYMZ%Mi;Pf7U5 ze$4R@e|4YFjhq>Jmj2RJ_K(wFTL0K_qkk&4|&oY$n7-IE?7ApD$}#G()#0WtxQl7>|N%)9H z+0XLD^OTQI{`^{!Vj_9I#_a}@@|3iG=~?yu5OS)CMMoIJjFG0uWJ-Knu{UUFlx~qSYEskHk`=cA?6^2K}jOP`e__6y> zN9pzxS3X(kt>?e;WK~YN{8%bax#_VLmmaae^J?OHyE@Eg$wZ~YXVar3PhlT-kw;d^ z@AOqX6QFQV?bNt7>CU^|( zucHdy@ZicqSbb)&@!%lcZ?0bwdn@Y&@4kNv757iJn`*k5+&D z5A;zhcpam-TBqL-xFqmtt7J9_TCB>*@}T&olGXZD<4&;&g|&7c{3=!X{MzrTd}-3s z3&+yn#%%ILm@lTR^z?6ODpfiKuRMrP zf|r5yye8eBS}(N%Hg&z3^m&cu-lpfRD~`CCx9A4lpZnlq@H%nbrJiR?CW1RYb?%8V zUqtCr>&!)fK5^9yF&x$q!SEy(UM3duV$US=vEO(togs{#`NwkPGD$qs%8Y1zvaz! z>K=HYa$&lCt=b%Y9sF{17v`|yK}K~Z>3_VD_DT(T9}>%QSPPAq?m zDMeE(nXdG{vvM(@Ph5AYRoIE4EuwT8u|+V;s=jPEwp7bxSh(zCFJ)YNu>;ss|7A0l zJv5)$?b*n&P!Zxo1N}=Su%7p&Pp(+1btEj5ulzMdxfX3hFSbF|+y0d^45#(T#!}m( zOJ*^=tbF*F!hpp#);OP`?Y>}h40=t%1*SHgz$+pEvWmG58-z6TpD$$-SzT|{|V1+DU#NOE587pSqjgDT%>0c1)8D@g?a>QHbgO(;Ob;zT$WXhuacXuoeiRxvk)?|Cn?LEuk?&FQj{PzH} zdY`%Bcnubxzf?mh$fxIA*v9&?h(Ge}r45}g)k5jLoX%q&J1nP@^S@ulj)V2tjM$RN z>r$RG@!WaEo*{k)}pbX;e3Xf%kNY+mfxv7p_W~s@N8a@7eM#) zvX%|y#qw>LW6K;{hy%;&Vj-@aDDSM~m^R+JzpU@Je2GKd_QKD9z3@Z~T3p##$xcY9 z9vWEw8k4j3YfL0#3mW=on7Mqs==ZM z@Q~Ljcl`BhPQZl46`cvoj)8QxD%T}DkRythId;srpCm&ZTdL61%j+EGNf>*I#Y;Rb zmu%C*Tikm%C!rQ8J9{zfEb&3bm)PtUtC!!WJc+;^TfD>*?N|V(o8u5W!}#!m&6nS& zT>kpNCD-Fitu0S?+RSTrmQU|_*q-L&vU$5$#=R^!_OgmkEmi^+u79?wi}3I-?^_t- z)5%>*Ds@uvbZ}U(%~DRw(&0^d3+H8SbuY-~)5r`9?>S2aa4BUb3py=mHJ@STOKWs9 zqGyQTg3XtYbvKtZ*nPGu%hON{3pH8F_2ng)-V33;_`GGr7R$4j1;>_+?!}75S-aD- zY;-SrD9z|jkMo_~NmyLi94{45v&r_m&RaB!$7`_E+G*)FHeN2@MT!s{dtw8bS-`Yi zWYrt$g+;bF=8(wo@u2hDmIBEIL3VHW@0+8)}?=8u1>c?}q*w=VZANe3n^flhPzBRbZeXsY$M*{msTL2RiGqbz^d$zo;yv}6Shi|9wfYzqJP<1BeoD%PL#LIu@iA;p)$v@mt-~ff{T9U zRSUs9t-O~?@tzhky^WR;>*dC&+`kkYiv>7r7i|ISS(y^8Og!6?5*F>zEic)U73w^b zHBd%sw>*B@i##uiOTNX>XhBQsCXdgRSg_PgMO@s6>sgPpsnjmAQmS#H)%D(8K1ER+ z#RA|ZpiHBbF02=_Kq&Rpd)74_7^>>qZm5&P0V&}R0Df2~ocAiWSQQ=L z$`*MV*#EpU*GiwNAgmk);gR2YLYcAeYNSaR(6fpyClm#9xN&Qw-F@5J%GJHMj9js>u-MXeZlD7~kGU_CZj8x(s`c!W?TJUBE0jX1a)$B!#n5{Y2FvCFO2q1NQY*HOp0Qgez z#c%ZA7FVmWkH)gfqC?XkF2hc0h_@2jpxtfZ@cF0c{qm2GuAf_!9|arZr+AOnq>3#w%Qj|QV&#wWcA^)z9BVn|Xt{F`e>;~4>}9Evx@ zZa04Pq2}J^MA2I}J~={N&r_Sq{=iGvtlu-7coQFJ7gvvwxhCD8s!&yG8z%Qq(5)0I;BiqCkAtkz#pjK<4DV?SWwheO+>i0HchJCi~h7E z;qWs~x$aY=z~lr|=hT;ZqU)tG1flyHiYRRsGNjy4WKD2VIdSUeShU z;h!frQ2Eo`6_JD5OePtI?pOby#60z~z5y!%G0GkH1+AA68lJplu3N*Y$g^-ryo;LW z&7iJ21@y}>^(A}WND-_hDtWfI+6R&S>P>%m6G?R#SXph5I=Zsw9g=h^xBKB+!+tN0 zI}ykmh;+4&{yjLA&Gp2aDnmwfm^m5-_cRey5XicWT#2_ZB(Me1(m}D7o7CHJ_c^x( zesAznEX;djB8EXb!GxNRcZpp1v6`m6MB3NsCCU{!Xb1RPeeuh$8F=Q09*w@d^AXzdtQ=&=x^a9 zhNJ%VPZg^7HWuS;&RPr$cYfv2Ig_ZF$d!WIgZbo1g%j&hHk-J2b!@?0pffH0V5*4@ zk&1??2F=zpwL`REYCEV$%(KqugM%IYS18=DwKxn zgmpAkf)Wh{W&(Bx%QxuLmOtzUXT``& zAt$7GS0TJP*&Q*xTBo9XHIWM=2Fesia7+ENGF|;( zxB#YxmzW}o9Kpr?LE`DZwbv z=CP?}0I$4VktDB@jc(r2b*X*<5&SJfdY43xVk#FUdfaI4(i?n)iq-jrQS*5k^lJnvxb2o>OS0RYRx2) zs(N%%uL7s8I|W8BsF|!9#dLkw4aFKLMUKmEU@#|L16x;^vvd7s{Ltvah)Uq?4?2Zl zR{?xAze>XqBNEi=1&2l0E_~@LD`NMcPnub0lBm32S;EMr6Am!c19VA1b(b|pZrxp2 z+-y_XIO?U{zxpuwJs`6Bz(Lez6|dwr@5*YRxd_W6eTay|sm64s$XFj9X?;`ozU$3e z+6TzZdfVbbo+y;)&;(r&z>!YDHPUCTP!Z)6N;_QjphYnv*A#G?cw&vJ%#!I!mBpX9 zAifE|uo##$Nv3NB^I2S7ulvU9xihV1IjLY9+^m8wvl=&J2msTLjaS7>rCJiN61FE9 zN7*Q<&mA-R$Or#ttr+6jMR^ED$U3wPhPe`&`;O}()%pFV8El0}-7@ItRnv+f2u0Xh z{p`1;jc1cOr87wtcc#ParU#_z(nBgm;sy8-q8JK-j5ha3rRyF&Z(R_Bd6+IhM9Cre<@NTzJV{);vEVePf&xCM^R9$Bm?c>=44W{63tpTKU<@!sw(q ze$C?OL$_nk;y-2Xotz5uA1CH&;T}%B7ZPK++R+;3z5Kz1SC!GD_7FmEy!1e)?HzcG0fmU_vi|9B$=fx-w=@7sLsuk zLhOWr{7X5Ml6pW&PMv@0Fu`-A-Z<3n2~uwlAXX*?K;2mucAX8Aoqd59ScS|dl}s|7 z@4EE0@y?@&7j6_~w3(dXJGoqOK#ml6aM6?41?-jgmlN-HJPl||>y zGQb&9M?d+SleG3c_&Bym&lbDi`yKOkGaYVP#K<%n04TC;NF*3WnO)R}GGM0}djMNm z@RIw=Of-h3g3xt7U(A=ezy`(UIxM|VN1#3k*( zQ55ohe^ocY*aF>0@AUWD(4S5@cSYwL4-+ab$V4 z9`{&Qfa*vFihF~Er9}t~Px)>=W7yX}Ps=@XEYOSj8K^_=5M zx8iRKCme<)yyhZ`$T_;?iZ(pmcS1dwzyWbdNP6Mn|MK+m37nIkz$y7zKonMsZyNhN z86%~UEKg5aVP;p@lk}A{#dB+;`rzDs<`$ z5Ky#*S}U$gnr)cEx}dsbg~&*;1`t4Bn)+ez&2@Je2C>7#Xrr#K2F!@hNwjFT>FSIp zfU|Zy4&xv&TWD(ue6IU1eF%KkF-tu~QUFXOOX8q#a{mPqF#Hz@$&A(nFR3vDY6YQh z2-86G!qua*r2C;i_iBARJCl9)?eqrK?VvZ<$$V!$9+M(qVuD3;|2D^7(`!a;ea5w_ z-;8R0x!I|f<3bdE<*Gg?+tR$W?OjlBZcRtdt-fW@zb=>__Euk!R(Jp6M&^09676{~ zq2BY&XLtI0%Y%*e2k#E22bRiPbBpzwWo*?a}qeQ@^__c;lZ852shhpL_Fq|AXb> z(lfVRkxnGPc#Zeuxw{V2_e$c*<+o0uhc2jZ99}eD?JH&T}Uc{2L6%5KTSM3U@B2YAeW`cfuZMMmz-f{ zR=`ff6oGJrtPay-uXv2I~$E=ZOiN+Mbpv5a1oh)6&@ zSSmE3NQW}RBM)Bg#e~gya=bRC(jFl&g`?~|j|OtXHP~*~R&W9v7m6SOYseDW!l6`r z>H@t_Vi6Rfq`#~R*&@VhrnAtkwMtaRBCQ7G>5q2O#^4@6(nWXpbnB2dN#s_wvgCN= zK3$gX^#_(Db21svGT}L56Z};wve@+ZrJpztCzh&8Y~#&t;u!!5N?xc6+5K#Q$$6_d ztrTcy%A;>ck?~dd>N8}>>M1W)}b-OI!ftE%Y;G(N*GFX#9v7_74MN>UqL;F&D4UH z7S&S6WUIt*SDp=%-B_6esnDdWSrdN74M`xCyMO(4-Kd#iLa$h^Ew$7*IfrGkOT@K@!YWK77O!IAbAHI-PX2mTUcwb%WJ1MC?()-o&#j*qIKzm zd@^Vjg8@Pwmuv`&D-WjuHCJw!TysGM$CuE;uY8@*(&&tr9Kgetyvn_W_b%Xo=a|J6 zvS5Pk^{NX0VZZ!z_o)VLmL|E^=G>MZDjT<0*@C+WcvaxYhRFmEJRz_l)xn;9?L6Xu zt^U&Zlj;x}kuMp(7P!y@5e*_GjMBn@ZMqUlIE>2+!BLTMwn&H^V4e_&ib4!RU?q?h zZ@8~4w|r%xd+p`nwzi@Qqp`Sa(FBdMZZ+oIL6w|s_|5}TrveKwxKC@6dbsv0>re=6 z3Dt7|;}U2(|mJ74HKn}It2w7=wfBLT_j?Z)SjLM1~8Sch>8cBZ%^RzW#306&ud*D zm&Qk0zVX%tft&`k?$I_mrMYa;x4X4a5Nt_3i_~HNKn^AlDBcNk%TNz zVItfx+22~_kB)d#oGzI-Hn0H^%w0tbXtdf_%Vf`#_2By1y#cYj;6Fx;l-JHDV}| z114_befHn*{*f)t0*piweqmm_*oG~zj_ieZ>qTj>pCFF{v(VUKC!#{s1zlQL?Xz1j zopPtL!0W#0{)IvzSAQ3N6W5Y_vDo~Vkv3lQ^%sH~lP6D3=6TXU_vB~g3_O+|CX~iY z5AvI2?l7u)QmUcO_zSw@3m*=3wPrsXvv()D>27OxieXjTQZe$Wl@*ZEQbJPhk+i+6 zDzgBzI+L^ z6U8#Q7?}PngIB!k$g(&ya7Og6S^1vvgoV-DcH$X9H%J+?1rc5<|Mfc zw+D*bK6!8~BH(AN<4i-wL=8R?1sH%)r2{AZRM15!3|pf!87bK&8GMTQ)?24=>-%5J zZYF0y=v;WH2sGWJ9DSZGM;Gf&yrZV|AZyixUn?ME0x;}5T`O1hp(9lA4H^Z& z(D3PzKbvukGXOdTgPtLwil#WMPhk#$YOW6|8vIAzca8vBj&o1llT|c;vWVq)AQU*O z>3&8WXPAxAfwsadV49Hv)7a9K_k-2VAYpw+xLut>_nx(?G>UmYlY)brXmoC~9&|Jx zoeD5a=tAQJ3iL&9C=VtItB!;zO)6|#LdA5iZlrFM6#jKiArGB;9mMEw zS3#pd&o&rPXWB&ADsf)_?_Si6d(_Z^zhUac!m*!o0KyQH5quWq72X-kr72={6{ zy{Q6&jGAS<)hVe~xbjo>bt9DW-~IrSvBm&_w*GYrdueHnoS+-2>Zw+!!D$kqkxFT@ zuFlO>-yc-3x|crFB=prem29PPOj3?xI$&JLM#|7j(W_KNaHMWvuVcS8MoZF&A;8s@ zkXF!mJASr+*y1-w(L}W$y`=SAD$~vz!4C0@9+gjl`mS&;prAEXfyK$o5!Qf}f>0Ei z5Jx&Xh~SbpwJ+#k+Y{Q*L}zYRc14r>I5ndq1;jhHBmsftecaU(A|FBZg(?9;+>UlQ z*4A1jHH3?=a{>xEO5_m>J4hh<6lI+(pkYh*fWl_NG=xvu!7ykfQBP=U^m!M zWplDWm_ji~j-Y7`I86dGC1zH>C%^?+6YMs;DwP@;-OpSJC!uws>g#gUf5z7w?V~c0 z6g`)Qk@?$orwsn^c;#Q}@AfQ%^Aw%SwJ3tJ)yj<3te%b_z`*jA>wE^(dE6WD|IFoP zUw-y{x!drUUxW|Pd%`?FXrS!FQvvS#UK~BN-dzd4mpS=+f)5RUxqLWSYp&_a^=u*} z_^0OUuPkfJ9rx(MfXV@0%lXvZx0dn?E6u$dAurJJcN{sS3RAyw-Ioi}NVqsHc^V29 zpe6G2^s3}MLX944HpQcpxZ1#eT07nHb~QJV#+8LchYTo81YcY2NeAZ@pH1qC%mE>X zrw#|TNezY*OfGay_aiqu=XCs_yk%yI9HtB%-O6({M4aq3u+GSRyqbrx|t# z6|^a97I$>6@Qmrj=MY)Bm74+SSOu}*WUK&V4|TzOgb4^TyV?pRS8yvk$P{Q4s@=c; z8x*)0QH&ab8!wO!4BI0%Yjm%vqpQ&g<~&1&NK>DXme39(%u5(apskcK&NM~F zkdcC5d(i9#hyXx(%P0Y@CM$+@!kKf(%3$^&E?} z#M1M0w@37HFK~bmO(2y^nH~7h0@ERe<9+QqzBgSOYXe!+P0CLCEhM;v1Yn8Cc69m( zLyo1LSy4%tRjlACMwT2nNjJ}Ig%E4A7vs%^Dc|{(S)!fknFH2|_~06c4ijb&u9dpZe$uue8ee8|=M-}_ox zO!%n|y+ED1G=j}nbF7B{;v9@%Kf{0mF7VS*%ve_aV0w39v`sV2;m<{Q{w+eQVn|v6 zBdHY+u0Ha)6*1WQNgPF(V`>UA0DytMjVK5(UUu3Pu43nj&0??kIkm4ELVJ>oY-lGt zsy8S29f23`Cx95OYWpJ?ka$;$-C#Ozk!}?NN%xDtjZ%w!PYCK?0#_Mx{)yNSJV0E` z6kXY`W=*S&^ zDe~!-6#9GsLt|EI`x-vMlhw?9tSXSHYeMhvgNjZLWszc#BOm5lsyEFGB=v^|-2|dP z5GBk)GXW7DP7TmjkV^1LNyQ$%ukPt=fOBQ?D_Byk#4Kj9%xW_ayMKL~FrVPeuo|l? z2Ev-Fi#(-_kDDIUYO`;xsUtrQMwEktRmeg-2jqp(xj5wd`0-ye3D$$bw-4izVhqAU zIRO(Vf#9r^3z)Q1Iuf^1uT`AV-dQS@07x{1t{SboZYtD@X)OOXHloEOMqlK)pqHac zz%p1i3Ytqq;QSdNA(+S|L`eX_UY?N+hxP+mMhlny)oYAj^lF2U(IOZmLA2BFQ`WZ(DkEF$31sr`8rNi1~yZ;RT`A3LPt)dg&ufDp?TdsTdeb07*w}JKL(4BAmsHM5srTX1tD=g zkhEI7prN5AlgL|w>8*TgCo1pyLKdZ=cQOTo`7Z=@(cf$?7T7Gm6u)c7;`;=DN)*XM z<5M3>JN{q=%^67)hl-8$!aaXv&Z_{&U!@&fI2AJE`eT45n^o7ly1)UE;*4%x&xU&7 z{p0IuG*&}cnu@7(%TQY*)n*Y>lwohMn}a}-FLrbIge|TS8@7ozqpfCOA45~8zzXGSSf&ABz3J-Jl7t1(hJbPX zc#RQhX;_kJ5QiGkElS{wI8Sd{jcxgWKS&X~-Dn8T)A6Y#n$-$ItAxOkfqPJe6Emx( zTf>pRt9)~W!m3mTII@MBVO8c;7-Se33DVc;vO78aiG7SgI~Y$>Scp;wq?7}Hx@Zk& zB|&46r3eCk@KiLsFW9|>J#dz&U}_rWD(04|@2}E22>jjqg4SAG=J9mm?&^#e4E!K( z^Z2zWtrKggfId>1fQEuU%umSf{{Ck=E;x}ypkP#)pMjr*Hzf@4r+6@@&y?A$ho0<( z75hZaIIOwnT z6Yp`o=dGma#G3%P0rs9ZC;V%NKgxFZLu^apOR{sf^7*7tnK&3|fAT}`Z_H4zuI*n~ zxjl|A*)V})Tlu34bj<(B1O0cFBkU!=a%if6!@hg)LhAkqzUrQpY{~yL;n0=zozVB~ z8oCJIAGfsf@SYXCrr#a|$H2$O)bt@qHnSuFm3N9)`aF_sAM8c5ca6`BpCm`Qk{*a3 z#6vt7;||6#`^bs+)bxh96OF|?f={o~cINf*A);y=)n}iVO_7M*W%i-v-N_^R=xf+= zjfoZ%<*OTbdAIrN0gM!2v}J0W%w!j9cwf#dH;-|pu<sGolhMk;bTm2{#YC8j z-D>rKUs2yjRt3Dweh?=^c(5~yqDVE*w1`VjcK_EWN>`-bG`r1JKS^xjgAQm&R`N6c zSdgkM}ji=;TUfiX{FC28$M$=6=|P;+A)L;sqQ!Sq@Xt0oy z(dmBYW80>G!Mi=#6&2p`HC7>vWp;#Z0A#ahRG7a`oSE91Lk5*tj*+8rF&^R8wtSA6 zfO;esJ$O*#&ZhR0o$?qP+Xq|p-1sEn4URTITi`J|wjHh!Mc3>I@TE7d3w5S(B9Oin ze^DS*hI*#2V1t3!1ba1)pq)*_~?;y0fBRDw40Uh)*5N=MqYpY?*?w6nK&O;=T2DqQ8 z5(ZEXI{H<+;cEiCdj_9<|J`!L3$-MY^It<>u1+rx;wa#Nu6H$o#V5;t`i=nl(m3#{ zYZD!Ju{ueo%=`L`Gh6$}XLKuD^r;6)Sg>d;qjT=f`6-4j4+Ain4#{%rY$0$!i=_ZHhBg2@gNBP+Ib-I9!Qv$P%Ippd15_BIYttB0z)x6jq(HzL zyovu?c#;@AF3M*4TGQ;j;%%llw#1cnJd}WZT^g6;qn!e#%ICgBnjtb%mP6g;~ zS+boksX$5+3yXl3(2jG=p@SsGLZkzRN?90ajBTxO*Jt|8taV>)G7a{~Lcn`>5Xu0HHwK9Q5A(cjMtKIl8BKl z71`_`7YAyETJ-+QRxmzeK^lABgY<<#8c7aeX`+)D0#PbXYk5OXWi<~MFcR!!1Y!tU zX)>KAd|g7aIRb18nQfq7eWD-|=SpP?6yQpU*NG<~eGUBS=vZ5F(a*>;GHKD$uC5S` z(nz}>I8e_ZYbuZcPDO6yCVJZW2U`sx?Db_)E3`ugQtl>b18^023cBz4g!sy&q<7Xy zCk3Dj=kz z!ww#zY*IhE6JF3YHcDE+j)j^24*G}V3CxT`KV>V_s7`>R9&3dQf5O`-c(EG^gW^!3 zGdu5-QANp+s3E(buXqcqZNCHAMEE$fQ$Q_2gTm$7%T+HdSp+7^&;A}~Mtpe0Jg}j% z?lQ!6v0G%8*(lv&JQ6n%-Hy%y3pedfrV1?8#CNLj^#Z)4!4s*{ePRNv;u-Ol?kxPH zf;oz$0UKf=bEt0BIJg2*!WL7jhHDxDf|=03#SmGt`ZUCPC81L|bnsO%jeP;&f1cn5 zy;+hXs@F4C*(Pj+Ydeh)rKlT2lvtS(x@C(dttf?2n#SFqdOJcR^e943B%bO!NsH0$f}y zAn)GCZCgIdh!HX-sG8p%gML2+5)d~_h5ebH|-Gd!hbV0a609gZSk<2u3ha`-@ARZ~i(opPig8)lhCqevJ zQr9TTq5uL*oi0E1=916SJ2Nvemh#^vATki*moW;VtAk%%Xo5!_mvXJXAE4Y`F|=Yx zN8D8sZI060qiFgaLFp~~stG@#I#rm!F9|9vf7QxW`pSZVv|e6I{OfYCNRnOC!R~2= zBz70pC~`$ep-_F{;n(gYI>hoBFsD+q384ciOc(&8QA$C3d{{j0C$>fD#I|H2WdQ?Ee_aA{@8EcATDqdT4yBiZgCY@%EpRj_ znM&xg&UE2yLg9r2ui`uB>?pu-jssvK_oa#F{y)gguUGm8#_zx&Cb%&A08>)`@r$s9 z2`gkDom+@^XcLSLf9;>8tkZU;HBrOaKlC#v#W+b*C~v>*)vd7^?*LBkvuSoFz`juK zK|6+@a#nx81`Q?9ep@BoLj?FkgUw{)aD8-AUt2f6)4OiC{D-Nw)3xKNBWWCjUb$h< zRn1lR*P~YY^h3AA{v{jCf!xI&|3l^Lq79Re1kXp2k88CmCOT1#@jc4~99F))`2V~_Xa$c;XUTRwv;j-zA_y*YB(9{5DNUD-I94po}tlS7rh zkOyrJ_u=;6$7|?#hj+5Ut;6dR{cQW{^@LXcj-V*Nib%ly<(9v{8Xuaxg|I)1JGlVI zDMgE-Y;~G~eQ|;+`2LSP>+9gniUJxRbLY1A#~FtoDo zLd1zP*3i@CJ1?lIqY;s#u6T94jxYEl64PGgqgwDZg-fPo!b)GmOB)_n3t53z%G3oDRt;tW z;Fv%&wZef_{zQ8fzAx_)To)BQPypA@;pN55Y(*$4w?jshz z)#)^*bx?V-SQ#n%!9dlY+7d;46=2HRknnmyCD0)Q#(V_4fl%X(iyzp0Fk-Epia1`S zlly`T!Ne#s!UebwHFmJcJl#yxV{^jX80ynW3U0#WjRjn{clo#v2Z_kRKCz3w^}+*3 z3{qA*&R;ME@G&Xxe)vaw0t=|g@J)f) zD+w+*@zBSKZ5;0x#xF{b{&qnk8^`%}K}AUD#SxVKPWcT}_8o<@U+Q<~+%J3o=^xij z_~B(H0Zt)=D+AOI^HN;KT)M_;@l3Ik6z;IqXoZcSI!C2@A8=OoQJJUtU|)(*9T`jG zXm$x!B1zXE2Jha@EIe)1Y$H1jy|gRs~dZ{wNY9VDY| zHpy7*lZh&>sJ>$eyCK1;L*&A>oF&wTKJ<+zA2>Ix2HLWkPV782lLs>NrwJ7TR@y@x z=@iJd50zlkg?_rDijk=)5GTavhRrV~D4@OQ{g^^@WNlbyD#_1%A7)`x!tQ`NQK)VN z2QwaERMz^XQ4$Vn2>%%XPOeuQD1X}qUl$b*wUdIHjkE!7^`Q+XCSmUf>fqQ5H~C!g zgSCz7hed)GkyS)9Qi6r0m;-=-8U`|yvnLPVoo2*AZ;qIeINs5kYN?;CbiLbvW683B z7g@m;;WanZtDEcTK=n9`rJp^ujKb z9zXzJRd-nM-5*-3zTz1+u56cjf^AHd%@B`H(K(?+QC%V$X{jPk8s|WnO+ufYP99^N zvSc6#`mZj`(7iuh>c>v5p}v#KUcI|Zj2ATx`0Wod-gO!>zTt=u0BuB@&c{}ay|fX} zq|+9h!EiP4z@kPZ8D*(7LKSd^(ZznJ{Btau#DH{+Ub;=Bk-_JDdG-46<(%JL?k?p(c&YyDWA#X=uwFc-ZEEcgktz-wndW4 zrH02rcUZ%2&5{ZF5Bo&{V=|+>X?jL5kwaHU-oIR-(X@sw?<5BHf|$;m`9NavP(x1t z9E5kO5xk|4-q7s#8hr015(@U@(_N%`pjui1k_?Fr7&mAa_X<6^5U2wO1{|*@QCs=U zYM`aSIq8r5ApEn=8I@9hlp=nd24N_v#;5^F9r2)cN}wgFD^=xyFoyDD;f5k8ROB2n zCI*kPo`Ir6Hr{1#e+3yPX-UiophtAfMk#5bFX*2&RS?yEhO>w?rD;S1B28g%j)i%M zRINVuw|uuQHxVw5Ki374s;U|m@Ur~5p%5k{6I0#r4hx4gv@?wmc>%&~A^~CB_Yvqr zsieq>)aSHgwxmixXUCs%1egD0f}?~vm1Y8WMWzV!Aw3abkt-1E07m1D>xqK%y8rp( zJc~noXC}gq=zukvmyj<9RT;7*raPfv_3Xn21!;nG7Yc(V^yLw>bJC+)IJ49vuG0N^ zKp5Tn9&#NlkW-7ErxH+Fx{BMzDIuOiGLR7nA-{^^N%NrZjsL*WmAa+k4fnp1Teu>= zh(>xM=oHzLecFb%J?aC75s?C4gyd?pFdd=%YXvUw1mV;ziTqpd;FTjhT$T_%lo_dU zYUD6499J}rnQ%a+bH)rQbp_zpVYYHUDdNyOfvOqaHN*AQNfwDfEvai2s6O_W=hBoO zv`irX5CUZpd5$F4we{)PCO|f&iEn{#ISzax7h=9bF!Uq+t|x)t5u8IeaXKUJ7pEuU z_6R%pF|5bm1y~IJaZ8)}e0g?k9=%RoAVko@TAN6?;JywCaL^9%Kq#UJIq%d79t<4h zb%h;OKI!LkPh<6S&I#{aepxUDfee}43SI^M4Pj(WJ0Wpv7BPq+NWRdMU?X3A^7 zPfYU8ZG3=lGGvMnRG3suK_?V8vQew|3^<}dOo2-B4~g&SZG?MJ?O#~isP5j#p}BX* z5ib|xfBtG=Wb%{M4O44^Ys;-7U#3uto^2NhG?cTm5c*C-7O%>6yf$Dj_?wT9Ls&cf zg&$(!oox9!Ew6oAfbqe5p5w8u-ht~U^<{p^L_gcWRxI~SC}kHN9nf^d$>Esd=v2gb zc?a4)uL%&i=&xL8VS-iHL*0RP<9YNq?qaPVjmA8rlMBnr);?iiB2SAhg`^1;wz&7I>% zuGi={Mp>a)#xR9ABH>lmZQ#w5Ds2e*OpH&(dQn^;Cs@^xdRmAG-bUa{06uV@Izz61}b~TjfSFHxQne~rQ{Dh8)M-_ia+5= zGhCYSoq~?q6WUOm<-oO`#vFR-oVAoYG7?4sD5EhA#8C|rgJ-7#-0H1clL59Wd~_P5 zx7a;LCrtR2(BGXf1Ngp92=4I439=*clfw=kdXECHx_ie@>9+$8Xsit?XGC>IB{dN+ zWIgY|hz}g&6PHxv8_7VQF_05t_W^+p)^Q?cAEUjas_z!i5mS5p!%2wV-Pf@n)TzEw zqx(M}4X@WU^!Egkx_F|G%c1o~Is<0l0rzBtuH}G+rfB}ozp3#=dO2=Q^bzPv<4eJ1 z6`=r~$mwih((hO`7Vi%xVqW!M3(Gf5u70r0fN$0p3h<5vU%unro_Ih0D1s~X6i7|Q zt)vf>CZ1{f7*~fF-*yXQeZtp9K8uCU`U?qGjQ!le4HjsSNr*$IhniMxBxsb;_p5xO zo-wZ>(J;Kfj*d-ufgnvep#W*b>R8dR2`~HNxiSpQ$4^>G6UE6FAIiwlxd*uee#ZhD zSn)deki82bAAtZDt7jHV2z`A)z(BP>80hDsV+Vu=hNTwW8xMq0Jk%!Wc0ck37a6#2 zr@rj}8&Si(eQ;5{{2c*r4fLA@967jyp(Re{Hg91&W28@aHO1>5kMkMN&+i87d$XdR zhepr+>}_v_+05CS?%_YvwzXDLS&(3fPViBxvTIO87_0h}(Zr&T%5@2vur3p(?R1Ns zXq+%@%BN|mzg91^%^DWjhsFz>jM#eM#YJ{la0@-XDU^1~-@N~BoNV!dKl}ul!UMCQ(?$aK-IP6AZ$brX9A7^-ucLVr8QUX#s!dxzC@= z=AO|hBvhFcYSHn70;CRe?=whp+rJ9rrUNem#ytpDE5~D;R4dXKfYa#Fo(z6{^%>cItEtI zuMk7%i$aNDlzPw1D9kVf8(9%bIs+i-kRwiKkfO1JEAj=3d}9^c>id-qh^vw+5h?|y zsHEVp$5t6{TXP6xnsx5ETV5F|wgJEh^WF#H%qk)?CLiAit;>Va#izikYnY`%%ch31 zYS1L&hYRLHcK7`))gi#~gxIDMY+jXNYah@^fF5gJX9<`)j8?nAKxwl$ zk{B^=`r}YT^!^84Lli>}19{BLc8Nn0h>N~je6%@3?P@Q*Cc#-1c(r-~%(@?Y+<3^up#_+^L}NzPw`ZpS)DHqnANtcL zs3ObwZq|YMq2?rV%&JaI5aE(z>iUDPa&qa`{%FpV>yE3+9q5qH^F z7yID_uvBh0So5VLKl+CRAaOOqk?Y%~B5q#Biip4-9-cYX)&M@kUqhP@-L!188-6E* zGC(S-cp7^9$~NSb6F-PCuCGDc{>4}7FakSdfC2M<8YqZ$bV~J@@K10u*a0UbE)OCm zu}(Ho16Lik%TrgJ0DC#zkGI=>(?+4L&NWxzjT>KPRTU{TzF7B}{7{XdiI`i!sTDZ! zhV&DIp^E@fC)USQMc)8I0fOPeWfSLVBD!8BJUrN6J_5oS3=F#H0E?UiQxr4&41`Yw z2;n!-SjGfI>ls;Z`T+VB!Xq?niY33QiXTmLR4*Yh#6OMGnO1v*kQc0XL(Mv-8K4zQ z8Pf^p0WqA>8|~rCtNOB-gLvM%FRuob0nV6^(Ng5JmeeoDGan#MKfnpFU2K{2et&^T zEyoLz^vaL*@6_=)+2ClTCk3e~K~Q3u)P%um0GsJ_!nZMC zvkQ#*UV$p%TGsu_J9v(!1xjy6BzDeE?>F$41y%z)`$Px^*hdJutGDgP3qa~-eSQ}V zz#3q=(>KVY^g+Xiec;veU)Wei9zI}6k@J6*4hry&0$Xkb1PJ_7uAOg%2nb5(Hv6+P z1iK2aJABcv^80T6I6j3ZBR^48U}~fMx(|$u$E*D))^8Kw-X37+ISgG%{}?5qm_VQV zU4pSmZ^smGG_a3}Cdj{dU}Ai?g%=JK!}rF#^}u2DyLJ;2IIP3?cj^$qjJzGX<4FFU zoE{js|MEnq2X^_FMD}v~<5wRPsoUpr!hQwoh;rq`uKaVgnvdIx{UNs`}19B@h+Si}M&lr<&O5d=alTP<%4vVI88y>j9qjdlkrG>==>fk}}xQo4y$l zV+oV<7NlP9+2iWNf;;&hhUz1qI1gBmuTa25+gQMB4IWGYBHREC5U`a(3~+x;W1x#c zlMF1O3MfqtVQj)0ZzGJ;ipdQd>tnJl-wwwtun@TA30wmj+4f zzx2#PZ@c`%q-wgTU zubg9iYr$9`1yYVs%g~Qb(J##5-~wRg|0N=jWe2?>ip4}50h3Ee^}Iu91)8}p@;-eo6xdXvp96btxlHFR<_(d>bcGyYGU@hYkk*1gA#{$hG<20x(peXU?#_rEdpY z0FEJCaxWP0?R;nzCf7hf=>55blSXPc(Z2t3Uc{&q3DBX5`^x)es7Tx=h(=7_DI)N- zvEL?~vrVUy*&;0}s>9G}Ul@pME}Fd#Lx=AVl;Cc@F0fxPXS~hR3f`ls>4{%PAV|5o zfu!@sgv=$SwJBKVODl^sXvxTI|@K9j|2;poeJ1!8yq5U?|Rmlpt6Uq zrSbG#Nu9`dCjsCKwg^EEMqd^)XM?IAFZBMl-_`GJyx)G~FZcFuxk5kg_wJvnUS+@T z_vQ7sRQ21XMg1H;n%+!ZYyPrr7f9$!orA@vzqF>po`?|e4hPNK+on|wrtvTaGfmt zS^d91STi|TxcHdd%>FngzgAFI_p5)?;f3II#*8Ighc+0FvEGB0To$In3<6b@=Ytr5 zYi8_Aa}oQ(GQ+q;$rC8hhI+zReb8E8+%==Hf65oOa@eths%9eXF5e6*u(XP!$z|hw zN1Zw(W(ba$sxki2EL7|&C+>;rU@vQWryTy0F`zeY%nCCLU3OZES)5{a@;~iF{2~&F z6cn8h4(xXE%H!w$0xwp3lv0g~f1n>7bMQ8&l_dy?6&iyfkOdVrs{R?bV%U(&RKXNt z@#5sPW(f1GR@f|P`r?J;x(m66KAos*kg}cBB&IJ`K2Ze2`rLpwsM&{cl`5Mo#RF)E z=A<#+k1&BDbS|4zRy6zdxBOWNe?RuOarV01CkU#<&naO%O4Wzl8fdcX^bayvzJ0jY zNvYyT0BHcW$;b+b&nQL$2d;v~k9rbUfAk#ORX?hGjfB3UFs5PXM?-`kw&+(T;<&_5 zLxz1bkWv~OX5}EXSl1ZDBW+IC_AzD^toxGRpxcS2z8Hf2YEc7oEW{d8hrU5x{O)?5!bQB36reL{Mq1 z>b#lF^Szh45#UxyvMq0!MDKK_Bx^cPIT-pAyBKWN2tTDbiCFldM}w~4S$v=Cg1%z* z55%k(s3}D1m3gu?c>s`#OKQS>qM(#{LV|86sGjao;g#3}gdV)>eyFd(g)`UmYU3ot z5(nGbx;|YWshTiHbulk88(1DQdiYHpUT^X5{juUURYD{fFaXCOm7$@!hJ2_92?-Kr zlR=n$GMvEzbeQE{_ifLpu|UBxD6YdZJ-Cjzg_&w&$TViV5o}8>vD!Ly9VnBRbcZ=pXJ)v z&DC&svoezxbpQTmN_>@8=<8dlO1IP@hM$@H?IsY`9ZBid=EZRe8}dY;Ro|#q{++Tu|pC3`?WUY^9IZYAZ6KOgzIeedH255F_pMnAhMeKiIw+g7-tN$yjC&y6qpgE2J*WAWdg;iJ(xi`wPEh z(^FnW`1HO92I=h5rkJoleM(Fa6FH$x<2S5^L$ig(p`OC}LWKmLtl#njkb7wGQH{%p zjf(+&?DMY?&W=s=or$}ng50CIWcuS6E@d4YTXn}Bd{yGH6D*gU`B&&ZK}x&7b1^GN zj8w|zaWxa>U!B`naOPH#QUy||2#G>&F0rJsOwLtQN#u2J<;zV-p>MNGw{y5?W8oOY zGOezfxrWath7_Fl$ZwqcJ%g7G++F9Fh~k?XSH+h$o9R`P>ALq%9Zc61cPHgf6Ip8? z4(h|-Q~rUS_420%?_QU+*!IKePu|?PZsgg)M*RM?y*7Pfa%62vL^Z+XN~#y0xQTx( zl;_Jk-&?-_jX|Y+N%Q-Ey8iX8(FKFe{}vy-ZT;70QV`p5d?1BO)~(()c**+VL1A^| zP5%Ll0TC(1ee19fEsluaBuyFiX@*4&R3balFhlR=NhDkY|CoH6kr5iNr=ObBxZU@? zGu&ETz5bc4S18!?o_K%y_(6{2O@(WTZB7S!%Wn(H7bibbdBfmMNz-Z$UNN)UU-xXY ze`M_xVV@_9Dc(8nJYG=WRo+rrJM?sY>%eeh{l2Y?#JZ0**QA%uq)%GaJ@a~9cj{GN z@s`2cnuB*|eZFCJJ+C}88ug)OWo#ROhx&%ZQy4c#oQyX?;w?#hf?0qdAOoEui1fYg zul<`0AaC|H!U|AsYQ$Sg@Dq5%HnI*yo(C9)VAIy2P0dpC99)f_ez8K?(}DsZ&JqWt znAOpYUW%^#B&x~MP!pS?9y22GwryL`Z2Tuil>vkHQr~DZu5TIIbW>|=eZ2vnk&BGg z^q^slIbq`4n9@4ySC?34L>NP&VbJ$8Kc5xx_7HB!z*szV4sBbAreJ0*>-C|&(Lv;i zg25X%#@pbmhPSt84Ye?i1RU9zBU9WZTxF6ACNF*@6Hq|bk%llHyD4hKH}=seq5}kZ zR%rSdNF;zEZ0eObBrh)mZONa=h+{z%vocy>0H>(HUHCa7E^F!Nppx-6+!#kgo3=%* zzNl_|%_M;N($|3LH#XPDV;3_A!zzN871B61_PLJdjBq>*#5O`mIeH@`UL1jBC76b@ zPy!lay-hQpNuBk_bdb!5XG6%-ruFfS%_g+d$s8e2z$nVf&boH}!UyCCyi7{@`k)_m z`OGucw{XB8+7#Cr3aT;5GIrJ*C?5ppMu8Zr_DTH3wK?e!6vRRUYeJcIsxYl|k%eo8 zTlaNu%Zj99yzrc`x=C|=V-so4X0H^?P@gmmts`%n*h9Z_LaNagn?k{x!-3%^7t+j? zz6{^jC8m2{W9S^Tv8;~kd>0S3mJCn;U=S>cUi|yf}_<<%_yvH zyci-Fqq$xs3GlKcG0c^O^^9~gt}s<>g`vCOlmXOC7lCMyn?_NWakLG9K2%r*nPqiQ zZL|iYUJxXSB5ci?qd_3fNQSLPfz)~gZTSdv|Jc51ly)I3WfA~z3&4k(nuW}XY?vB^ zQ%pFwwKnlTMlXPMFY7eH!9XZN?wk_fc@%w4KC09h_QF#-KCi^sF{w3xLz@_?$`~u1 zuya((;z2eL}mdK`*leX$thpFGDNdqd!z2Y5Jag9c-}rcy-2Z)5SwE zAR94!n3asWmXV?LD1t5ZXvP}-u-U|0pKSQ>aG?4RQ)E*?`K2{JL31BPA)p z*tm75uhkqIl=1+o7>^x;lr~u$;=XO$B32Iy=*o)p0q@bbYQU%MZDmEY2Ndj-n3}4& z=!L9Eri0gLpcclq-Z(ZG*N5o9mjqaa27=P3HL_J1=o{K}v4pl~1X%#EE3~|beZIqz zhMM*oQVpeLzj%kvqmX3Dz|?{2*x;7ZdJHwD)$B}TmPme^2M25P%{frk}1)X1~&w6_`eFS5UHV4Oc>31xZT)hI>Hf=8NP8WOv1jBaGjkp zW>iR-piGe%Q8^0_<)ae)mmWd6J@eJ9kRb$Ooy<@xMP25P#@px*Ww|s$77AwnXv2i0 zr&GG3a_9rHcM1vxElM_yB6?3f2ZpLdefzET5>hQcOjM9{#ZFw#kx-2yG8L`OOd56I;90+$8E|vBkzgXhsJcG#sintLs_8 zgbsA&P?@r@20g=2(J;@3XyhE(W%%Hh*!9HgXMxrc4GgBbCUjKS#F{0t&Np7vwz4KmCEfOIh@^4OSqkZ5PQ$#C{pNX#JSlZH<+kW~N~ z?3oy4Q>iv%)UE={S*fbPNqUE+Kvd^hvV{UHAki6c-9NlID{81m8X=!Tl#v9he8oq} zAT%gY3Ws3$=%CCAr~X}gZE1-h(9rzN0SXhz5y*+NWZ(O188)o3qB4@HO(nN@Wer1? zd;BGgUMBy**i8~BiJ$dgebb>?2+qC`d-DWvNth<8iG24>f0GqqO*1b*N9@`nWM#BD zbdXSHMx|-fu!1I)rRy-x;Av*a5=5@%DlBlevvl;D7|?$TsvQ=^6P z2N6)7^_UsHXxMm@csjOiv?+xlMVj}Iucontg5Dw3I7(uv>FkZae0SDBW(CW611{dU zsS)~Hpp5?+Ti_$=Zg5*Et^l$X%dSH@=D^wbz)gsTayLp@&k}KZ0uM?wrrn{Zv!c;K zd77wD{LJ;J**?S*DR%=O_5pR{)>e#ZRwSSjO5@sL>sv}O4?YW35YJNB8?HcPE$9gLCDrWRgz=f^T& z%yRTKa)hVO6o?uuSCT1LEV}$HLo6DUA}aL3Fl0@^QQ34VI(mgusu2D$n$kPG#d}2_ z^Qku)jgT3)aXqq9>eIl_+9$GI&@Xt>m5r3b>{&okpaAm$Bn8+jIsn(W;wZsm4gOPq z@v6CY^aF}5+$6NS&#ic=VvKL8%qDWP{v1rfzL@b*^DHThrCGqVk;rGsB0`cGd5f?y zom~zTI&(HubF6_v08-8=1QBg1`!|Z}tcY6}Ri?l2&HI&|=gjQ52M4&}LoYhUnE>5i z`K`Qx3>JS2tP87P4zL_^G-&7}k+SNEl0XH3dS)6GB?B7Cqu3}VLoeblHw$&xk^m06~G_;%z^i zJJN76#CjOp7H`90K$4IUMA8u`y8!}Qn{EP~o3@1mum^dV1;==qghPt#*twCjiDn)e z!z%Qy{QK-jvBEx!IuPVQPPVebHlzum!gVS?4C#n&99!RztHylwdpRfBW2~h{q)YMy zAAk=!)TTFn2<5+K@Q`}1US~dTkusqTxMsklxcgY^A-P!@@LLtE8nB{|yjw9*e^4e; z^CVg`5u!7(|B-hBMhUl^P8)S0G=NElsiK*bwJxC~33Dlawv|cH8rY;27)77Ulh!i{ zkW?px_AGRSD*k`w-Um#M^RDx(DvH^T5KeccX=*1rd1_p(j2tKk*ZepxaExF zo89y0(Ls6!YC2XA5 z9Ui?>Kw?}S;fQQpn{bji-9$RYoKTXWfpsW<62gd@&}U*^sD?I+iIc8Xh8yh=>_(WM zdZHMDK4Yh_(1_D~(+!O77B)=jUezJbgqu@ba3^fASS6ArGJBf5JfNWAzF3S9g4$0W zEU%#oK@hj+r<(Ip0Vr+Uh`B7U6e2slHgP5xIugV2ftUa|G-IvtVqlN#f+&DU`9Je} zMdpm$A)g5WE0x6+NtM)PWSjHU*{wDlOn?I*xUO<7DV(tZ*DqD5P(kkDi*G6KCwQ(B z-l4!rXmSdOQNkW7js+L14m40F=c`w)`S3QBOq!k(BtP$L&P8N!7A$zD(D-KCC zT5jA#+dvAvD_|FS(Tk-ADAX@eql3n!l@YLThGmczB&(<)7#!qCWjdKig7nl2#hxCl zM=oN5pLUD7BC4as3P2U*QR;9M3^rx9U=MQ_kjUC21zLwen41X^l~`&eWdykoJNH_l zYMPXo*+SQ-i4(|qaJ!81$iWa1Ooz`0 z*{<&xS(3;JNm&^bu-X*Zm2!aNK?$Sz6NfM*hzM#unh*BEA^s*1Guo72$qPF`gg?>g z8-KY7?MyyS&9B8Js$!NHD9lSW3j^eYn#0Lf7lSnwGTj(>_$8E#mWxZ}K~#t3%oUHb z!@18ESCGcgQq0|3UFrj+7{LExFtoU|FyJYO#^1v;!=wCsw-i?Z#BxH}Rf{u(cx0BUd1bApj#&e_&P4 z!YxgX?qFt!Mr5ER<*kcDYboyq>0EEV_*9vF5EtOY*w}*)eW2mt^%6sNHRU3psmyXy zHf3Tlq(Vl4A(}a-NwJ)CjyrMpmUZ=x(w*w_*f5KAFVUVQdB4nG!3ME5Orn#0xrxS< zOhqY1%n3qTOw8f?h;xzv&U0tUNhm6+ z#sG;|n%cL7#HjQb5$GpGR7R7UX)PUy4V;9!Fw=!A8u8q7<8mef5vjZluqVSV6;drx z3cb=Vk`Zm?glrbiJ6aQl6bEQY2SG#0TX}$&$izhh-5aMz%BRo^q$z34JBa&4jRaca zp)90is@uY%slr^&$5aH-LWtGJgj7zYcm%6rBx?8vrbUF?C>65Z+yd{gO#}oF6eQ*V zvJfFB9K&+ATV$|cI7vn{5Z*vQz&Eripa5^Q0&&xdOvMMD6jwwe;;Q*2pwu!*thjHk zR=pO{f(Ym#Mo^NqCS(#t0v{=MalZyJxdzMc@bjJX1@({(He}k#RD1s91GqEcF2ym2 zFs3!2-N5NMh8#Jzx~Px@L1IFn8lN^ERE`d2=c+gS-9N}@BLJR7zGk@@Q%N2wnHV`7 zX>_+mMl#P1&7od*Rw3k=El@}D2LA{lxKd16B>7y;VYvDQJHLVxC5&t;zi+dBg&cyK zAT4l{!IE&`MtePqdJW29I7!i_IABvQ+)z@kvplWL6!Qof&0HV+L}?*$al(LF?0m1? zasyTpOLedm4hcU17KuZ^PH;#tHAW*xPPWnL$OJPbEn0{HhJi0WQF0C$kWp3=hi4%k zA`=zR1vhZtqJf+MdxhjUlZM22RAaCp=mgSvS_w6c=nNar8Swe01XUTTVoI_YXx5NtKa|u# zLj#D2CpGN$<7lbRW)~BP0wcT-L?v!A1lL8isGqb?MC9gM-(C(tn_BSXkSea88zKS_ z-&|Cz#ifK&Q7;L}N;y9kery^B0RBTUa@`RLX#`9~ zEd`9K0wMc-_Ff%|+$Y%AhUXK4FR!9`nNnDmKp1CJU~OdbyUR^$tX+rzkcDC?PPC{h zND#*+i-NO*tq%escEvCgVSyIby|{rqtSVMxb#aVajUPVsKnVrOpNv*tzEO4uNJoe{ zWb&-F^gutFLTZqV5%9&voB1J=G7=cc15}jp$ZJE^J?|^4ghYr{HZkW}qLDb}#zG8n zZZOJ;!yYlg$(5dnKcpMq>=a%cq|4K#p}RNSS%=R{C6V| z0Q&==9G`ny?NC6shEwuwuJ4= zLny9Dpd&}YSVrP3w2_?vu}LYw=-@sqqtW!qzyPwViiQD4*Cht`{7zv($Z=7txZRSk zPRJ@o;LC!b%S$aR9Q!G443#lH1srln7<^X-{(9j@&(R2^TB$Ln@t;3af`_U>FHD~T ze=G*bmlmJZT6qwTn*~=UEm3AP63$A9UlBm%6KZ9Z_qfrh`imbfGYpyFsFhHbUZs-= za{#dAO0tS1#dsFZ1R-|mIs*ty#=*eh>vY|POT-2c7mg7xesm;`fY)Mv;`szSEIG;% z2T1i~nJ|?yUgWN_uz)QO#qy>Iq*my2CZ8bimLVzEl74VNLB$WU1FsHB(I@0V0I+>XJ}Nrja&dd5 z)?mxbimPteZ+fH_5`@vLGWP;dmQk!L58;pg<2*!%=YMrn8bJtgF4_R=#gT&u$y=CF z3iP!jOe8F2U#%-*oS-72CLL1$sEAP>Qj6S_qd=tBul`7J#bhxMVJQhUax@07tb{^B z(W`pcMH5bz)4_Y@$qgW$bBq!?AWEy0CJkey-I9~oKBCeoMwuNuq}6B>BR6(qit5-a34TE1UK@>-TCE@d(0Ruw3WXGMraERc|;i&evBN+RX~svvRc>= zqj_oid@#2lnWGH*;K+mrA+5+jem!7{33arxvt zG-sPubcXxofhy~6zW66;E-#=)X8Vo5C6n*@&Ef(GIM`aoHO#)e$*T(Rb%~f8F~N9< zgNU60HXkdiL0G`Q!e!;Bfk+HCQevphM(oLAHHC7-POI`R2&K!Ez+cQsR7sG+nW=!R zQ$214*7;y4sdz({ zEaq~IilF$JvnC(JGWbh05@i#AzxZcm%NpfJtU<4bIIe^NSfLy_gg{~1(ph>1ZD+N4 zY{PZ%v$teS6`US}px8$?%fui6H~hK(HV1;TlQ0g1=I`JapR6wH|AR!=6_5lTia_<+_Gq{N-k zpG#?4EG5f;^Ttq)IfNe(<;^JMc7k^TL|6GCD>MAlzbqD2oI$@D@s7KC64ym{j_j+k zf4YT8L`0B4#xR*a2pPcfkuN9+C1qo>3U~ejdm{<=Un>Fxkl;y-R>P$V->BC?f*DGh zAxBEA=pLCxHG#k^fk33*`+XG*cwR0`r)t z2q86!R8E;MxFSEx>?T|+FBzMG3CYq>XaE<@P0(6J!J-QPr>v5Js!Re0V8$lV=;&@K;LzCcmxF2dYD{#L!Vp0wf)w z>hxjtM7Tx=0G~gGhfZip4z`-Dpbty>L?*I_ z(r2J6hAILwaq|2L+TdNb2t?9+sQC^6ECrQu6llwY&C#E(FqbdK6b%oSS|KGv?x%3p zi4oK0yo+=)8oI-Ea$lsfNnacRQNI`Tu;M1PE7xT;%!Jki)Jai7JdM($ks$dyzf=rh zJr!)JZjr$EP(l(@1eu^TUr&XECLk>J6TF|WhjuWqTn~{zELo0ArE$uyiJr1+I<4DZ z{6gXRv~3Q{;3iF~7~=+M2DgsHn{pFNH4}mvJqplhc+%|&hQU}vK}2X$35^9(w1Joi z`g5yAa|zx?JHbJpy*}s~2R-QzWY8h6N9MSqeZcvXE2|iEVW}m{Lj=atx)?;bHgR64 zWAHd_Jj%Y=aW%yde&=eqoo~-e8ZctJqiN$Hk zNr-^vkUh^emZ_K$;ko>Sgr; zss|jo87TnO(u!w^YDXlI@n(ACLCoqedPSukA+-p?U{9+D;)eC+4zmqMVN6e`vCDxR zftAckNoMBED|5M=jNPC(>4J{&;mq~Wy``fFLttE83j1xk6{e&_+$pe?)MDEq+#yJH z$f!V4;KL7$74m_*fJQlRx~BQ@Ack<3^ z5H>f6ErnPySOB3_xzrg1@(b`ABZdXf)qv-sf4dkFshmr@CJ)ZlT_PA9lMCtvIk0j; zcSRmcs~L|aY|4YA8$S!Nkc|nt$|{L{LeF~W#j*nf#H>&TxEEL16@V87`Ls*K7v{O` zD4#TO$)v56`mlfsP>TA>1C_|TmraIe4gZ_6gsqw#8!O2wE(Tc-WJ@p$kVXeG6H(-% zphv7SMNM>4(109rYFZ2^ifcxgZ$^jn#fM)#TAU}gMVl#ho$RmHJ-8tXgEfcF^R3Exwb)X6F@J0b4hjhADBH+j}6jU%uQ|sxQyVS%-Wl3 zqvt&nRT~Fc@9*qdBs0ck}L5M3jUOiC`f|hVUnF^@qx#R(gQO1x$ zW+d`~>e74w7KUx*VpuBf%(?8EOA}YbN>Idvit=Cl&LS*Pw_jjU9_r3200>cPY{AGP zsq_r3lJ?S})u}!@Jdz(xZCs|H7w5(TDH2Q4PJ!r4#}^Q44l;RF78D76gvTr#kTA#LV zZH-cV61yO2Ijah>OGMQ?$kVE;ff`0B)E!NZv>VYdnm8dboLBuzE(?;uzxNg>s=N!= z;;>D?PRElg8GslDpa8`NNytJ>aq@xYe2Ze432h2^l4dSw0-k)04wf>dDPhX# z{}dKiRLJ00M6?d4S_+)p0zcD4hL1zKvEGEv4IBdcIiV1&i`0uG=4-T?cp?y3$z%+} z%m22xMu0;W6cE%A+|j!=X*>el5i*+ef*5C!K!xj^fgCsM#K<&CSTaHL!egk6-8P+- zNX*XXi{)4g7IC?yoQH-?Q|8Ps2I>ryc{|CRMve@?#Yj|6(gTBJvc{B@n*%54XuRsB zw-@)5m=hDRM?fD{50#K7HkV*0h6UW%f20R%X@x%xtm8Q`MY)(LupFx%z=AT<@Q+)l zaNkzAZz@6xanMVkOE6-B)2zmBmJ$V$b)K?n@$4)n2XM!0A*y1a7K9>WUdl2^Gys~L zukP46UfAG}d>p=$br|}HRE6exf=QVFc-gybV|(A~%a@3ZCKsaVuUQbV; zMWTg_qdULE5Th7eCF@taOi0IQgMVyDfcE5KP+c?>X(7f$z>z+I z@f6%Q4hmaLe&V39J!VX*t&`|RX-}2K=y6-9b5c?&ZJsoLWtf1T7-5`HXW3tgsL~Z_ zI-jikX9fsph?eQ2GGOs+n<+M>LNpYc}SStKl*uxMh&+Noab0sTub9Jd`2)yO zPAmZhHynbwW{mXkPtFvVwF4~4WB^gD3J(Tob5%tnLIy18A@osh1!1|KXtEh{mhu9l z1?8`xB}?*!u>4i2*%&Sg&Te(8DcOWt=6XIZR6?=Z!cv4vWTjcfVe}dL8;Th4M^^xr z`Op2J>4cmDYr>@of=NBiIcA?wQ&2S? z#;}i1aecg43+GP~I7?MQpZb7y$&nU@$v7G|x5#p2U;4O30b3$~dUIof{GrKX2+$2A z2{Ov|$&kJL56hGzLIjl~4F-tL!ABs547il20(gMW+uSK?E zwR?`1pErcbXH#cZB}s28?kflx2~@~63H%8)IH^HjenVnkPAXbSkO;023uAi9ODZem zi7}Mt*WputRb0YfVJBKGHx988e1MZeC0wlz^$s8)$RkF)2_#cR9chF|&NA^Pk(C!t z`GFxr_TjOln$yGQzN5T^gftr`XjhT0im<4CK2Fs`r6UMqgMPeuDqYgw@-R}uDPvL5 zmoesIs0b_*V@lc9Ki(aULYs`;V)vP}0+VcvPys32B~%YqmkvSOsZc^NIWM4z1u~ox z#IbE*cCi+RtT;+|zxzw&iV)6Ne=f&;!7Hwqi@0rEpOlI|f_}4s9EnYn@rYIzS0&HV ziSpnkmNIS%8>kE4{iULXbeT^@bLhcW@-xTUAgSX01T*%Nh%j$tenxh z2_4A|3C2gFM6bz@mNg)mW5klvw0jff7~~4NP{8IP1gpamun9O)dH0&YRFSdF`d zo=7wX1s+R^T&{9S@-qDUWvz=Ejkt#eX~?-i2kDGCkcrNN)j6-g#xD z0(3xTVm$;4n+@FY$sexOe|oXX2Nh?L`?w|Ziw--CP1J)T*N zGc?U>Bu21{sS^ZTC_+>tVK@H1vR@9|97MzVsA(B*hml0)N)(mn{q1@yIGJg*sHi(Q2MzJ6Q%2rxP0dv(^zxF=fC_>A4?Mu0qtt zpa=!DOPEO=SZypWLJnsn9ptv>UK!<9+Is}J=2TcEx5g@sMk#{F+Tx5z^G_nQvLh49 zC&f!3CaXk@DwS5K1B1+y$zF|w-E&_Ne-V2TkwawQS6jVsD@X~EN#xXX3;Ku1dtBLG zk)}9Ibcs=6HTOC=@CuxQEC3|qI{Z&xEXSaD7!h{98(1omgWVhEI}bqTotcaD>v98=~$YSXGruQhfcnH`zTEg(LdxVru_sL01XtnYAtrL z6yXMO$j(kgPK^$2MHjWWDaf@M&&}6#dPc4_DLc&~kRgqa+AL%8N zsNwl#LR~7**q#-+hx$A~W6;W>;F`NA)2; zG-jfdZ|R`=Qskk41M!jBAI*wg$#F_FaEzSP%0zgI3Az31zb3mN@$93VSBS#LZDuFf2=jXWs8I880u_hjPBPojc8pdX7((RM` zNYWsE$@oC}5C<55Cay~60s~r3sWpr%oisWuMCQUxXoBDxe)h}7{Xz_PLsJTm^-{); zd)zwqVfZ~U5bHwEF7?eYRC&c1r(yzh&q%t_KZ)B|UPN8x44guetl_tgnnV;SfzKfn zED0!TKpO+LnUh6eqc+wkD=H|IWXRWzP?WqtU?5>tX4uSk1)cluRex2NmdM6n1^)i=_i?g( zCY#7tNVo{g=hC!!et6YY*+`l(mJHU02GUP>!!HwhVe~p1V4lXyC$z{D~mI3YW}R@2I8P0$i<;nf69DFYms1en~4Yog~dw#M!oP8jz;{G+>zA-GAV(ngX|K-nI1 zMZCgi1Fj*X9LXdy+$Q5LlU7ihQJ?_EqJs!a_+#E-sdJ|34l1N1l4075C;bjSS^Whj>nxSc?iMAsVGp?A#a+{savM z5R*@w1rP&;s*kEbrqq_ zj}SfaB<>26SW5twB8jUCo4C6^l}Zp69OHGQjtCj-!s1L=Z38r{Di!no=^`ovRUY06 zQAa?Ry~w>VU`Sb%Nf;*)3U&i(0bv61kpbYI5Iv0&S0o3(^v;is@>o^WTcqL4-$MCi z`bY94-s2T;*|Vn5LS25s!OE`4A(-;IiybHc5RVMYuvMby@LlB&2`qA=2C7UWLEq4O zw3L(+rPQu2{08n?xxiG6 zB-bRNQ)Acz~Zic>=cp6aKN3Bn=D{td$zib#5}mAjSl3>(%=UD&|V6&7~gtHSbdJVt7F* z!e^-1oPu9`Dh3}E01*+dSFz5tUw34JP3lTW6o z^ArOT2_eQ&lv4hFVy*H)-|$bB%1K?qmCM&jpHYViITZ-pE;%vGi@&>Ajz&sMhjv?H z^DQ($6*vU)RBEcQdesKGEX16orbGc2DfF5+&HVg{niRJ`SE3fl6#@uY2i1hvI~dji zhn^ZFA*T#Q_(z=XPKuqfV#Y+kJt>SV0sW+FR1kl$6nfRKjj2IZOe|KYO5~_8YQ_DC z@R?y{oGv0LS22-~2sXw8ODkBh6AD`R!2SaT#V`|ybf3qM@T{^~CHAUtDQu}Og;hQ< z0P{D=bKt?7Fx5y{&3qsx3!5Jw8Ep$dCm0WDi9aCbD3yi%>@`9Tr|mh=Uk0Q+n2ALs z)du47wCsrJr@tTSi~xEu0Gi70+SOI=mafc_^9f{Bp9(!6pVO%73reze$xLK&%o=LoUx ze%B8cL$EPepr{4C`Y4WWGdf@f2>Y@_*Q=Tx<(wFAj|Y|$vKY?0j%i_H%6z0A;KYe6zUDVdy7kf zggGQ$=HoHhhB6XwE=82v@ki9+X;DnV5Pu+pH9CZaaT(N2+yZ?r%Ep*Nh_OO0XI{N~ z6sIal<$S|c`2q_rDJo2x5j*p>U@mYPReek8P%)jTdq^CA;!xC*f)pYU>A3=kh2NTL z^Ak#p1gzD-pH0ixXmiWmIhA_rx?HeQ|56L6Kr zg5U7T3R|I&RAG!Q=S`6}7jKyK&0i^2GkehTAXFt)RSf}BU!$zT?65#RG>I@x#l2Ee z%nWj*h=eJkOvs*m9fwhcyUVqZD>7{wuzJ{H=@C&}q z=5OXRMxq$PK>2X)65GV~ckS>^hjMYFF_!iv$g|Z1ytgB*h z4WC?2>I_!KNSf9D)gKhA;Sv;w6R?J>^e3aqVnM-dP>)x13)GP1x(EmcSmU;t0iLdIzZkI>|d%wqcz)l@#2D)R1h}ae5b{Eak1Vwskcm< z5scJ9p&;8KyTs_2yXEl_VYBEq~9+BCcb+WZkm% z_Vio%Mr3nNK30XRw1iuC2=GEw%%A$k65fpMM~}P(OI*BoUFU^>4!vEvI0Uc`=DhyM ziudVGo{cJR)V>i>;+5BFIUv}MT6eV$EbLGBlHD}T^sg8r+rU54N(3j%GIMo2p9waS zgtI!v=c`ZFleqC@z5QT%X4h{V_3!^_=<)y3G5mXr`Ai1!e&as#-zzDps4fY4fU9@c}A{O^FzsS#hQp+ly^cWyVGk_M^!ad=8Vh z4Xd8}$KSvxZs5q+ea)DT85qwCokP9jHR|~M!VCy#nr!Eb0Fd6=t%2rckrEaQl>vYh z@nwnKm{%^Fv(_7buwS!rp^^klrFAIb@DA_{Q60F#E0a7iS*7avE#K4RIZ&LmGVb8T z#lWvsGXAB~vFLb3uXWB+bhcXYhCg`D$ZQAI;l4ar+p?K53+!Wdgy%(4Y|A?Dvlf4H z01Y=fBAR49YC%`z3EwGbqRt#|+^uZcyo)@Vvwh3+Q%@#m_!o~?Pjt*3Zq={5nWn*F z`&G2gS72zx+nj5dX=GvoW`j$Zjs&Xgh8Zs&PcC@eV_^tHotT>diZ7HV%RIft7w*1( zcGqNJ)lPDNK&$TVLIjAj0XPY_#Xi24zh?p)=#2qjEz8=0mXRAuY2q-2Nw<2|HumF+ z&nun~txf`0j|japHuT6guzQx5c>yGOs(ypu6g%J}x5BEb+c@xGx>XBp;R)lB&RczP zEz7FQooXe>f^;jWO&MPCE%C&oG&)jS-}MvkjBT9<-NYI=sh@4fS?Epv4iI1y9xBJl9hPkn#J24@aK8-9xad}I3JoDtW#nq&Em4)%1$9=NO{3e568 zWxeM$nzeQJ{r71HO){=PvW{@$Y4)lW-h2*X7U-v!cPjre^ZBwB|AcV=}(rG4EaVpt@ezjiy!I;eY?FGUzGqJueJ(oZWaX14nS_K%^KQ2k0;BA!0zT(*v(^(P0&%q*fYS@;!th^Rnpmdk-?Zl!G}ED4%P+ zwHCXYRBwsRE&CkJE^jxg7l638H?^b^XrMngF-PYx3dDc2?Z#~Z6S@j8C120N<^YfEAe-?=sAPXWNe_xv)yhvMU27DSsi?+EuZJMt<4 z@c5zS!Ig?vZOtNiJCPLkp|7A($es(k#eDNsM>HaLtrvT|@;Ya(l_Ky3It&vg32r?} z@`Yi9$dFiG$O$IqCG%^sKNn+94&R2lzW5Q0fDiy^fE|G=J~4;50f7O$JPZL-E8enq z#N?dDF+m5jM3uv`1DUE7=x9_KK2z5nC_dAblu!)B!9<=Q8XZ8OH6d!I)kky#h`5qs zEkoT=o!;E_#ny92Z;19a{R%>h52?9*2tKo?(FpA)B5MJ0=${4{0)`lo(_?BY?II+%9 z@I^HOOfVo~G@UrruS~sG>-ZlEYEA_6@Jg@0@3*V<<@JEr*a$5MVHg%J)X)2u{Nw3v z-8*i7j(-T;F&jzFP6rZ4V9gJNFa^-+ffJp!zu>kjSLcG@HsAAzPty3h^`nh|l?yN-1SsQDe_{%^d(~n_Kw`~8s z->Ae}x7D|Tpq4FmtPLro{3tXehA4Rk8v0nycz2K_%bhQ$UU%+19xqMtr8~F!k#}G@ z3pZ--O|wR8-%T+uZN9~iIxE|a)+65S{>Ou~wi5X8>Gj_@tf7&>aF~aF~deQP+)5!)) zvxj@zDK~6ejeBqA=SAmCu=va+KfSf~nG5^lyUvNSAxaaV9=>N|M;8uSV5pq zx|>SNHZdo=v31#Zfjf(rH?4QqV(WO#J(oUwz?=-z#m(?=y7+8}t$@ZCJ!jzW>plxP z2Y7G3mgm}Tx)TJ36$hTFh1<^@tI({N5a_hE5q;kEfT*VV~cAOi#5Q9F1Q1X1^>g>Sblo9p3KCFJKdwIxtYYC zH>h}C7<#at{{?890cD6yxmqi|?78XXlk-7$t4*Rg`x=DV=RH;%>|a|t8&nmI|=t%d~TA@S<=eQ zz1TN!Rc{9-rXg61TGLL*U8q0)G3wm65@hZB`ic_nJ+y}5U4JEA%qX6`oG#8$$eEwE zv+(V;%$nY=0Z`3(8S}F1fgrD}4yNt;@W{7P25ERO5^F@H;}R!85-ZxNomt$RA?EM_ zi(2N~)cXx3rl) zT@y7Rp_TiKV}kI$yf6YWRhwqjD6v_1!~&$r%%%)mx^B5R2LmyifqE91#aD4jBIM<7*wtEmBelV%fA=QPCdjl4e03 zW<{@k$N&DdM*Z#1eej#Uo@Ib4akD7t9PlfHq*LEdZdI+!)WTXn4XyaHgD1z0Qd;m7 z6_SpELdK=Ex}2p1{*=Hf34gUVZ}ZRC0Pj}6>p;4zJl6NCM~P^v`xm|z2}k)_u<mCz@Zfg9(_;;E|XR1=@# z1`%neGGoInzEb`KVaj-&`b(rMtfOPY-iRxN!M`3Wb4oV=yIT3EZL#zz;tepwEDYcB zq=A^U0s=2UAr|{}Xkf+X{o{d6QcLY)tw!6I8LShw zieh5?&9-pme#Q0X7k<}4l&GkU~n>w}Rh-(3F?J4A?xa zSgm~U@7)l0KMPYR-H>;%DFx>!3wded5zjw@i;uB$cLvs=-kFL8_+{26aYfcbw zxlh2tVE$Yn8VDgxgSJ<0h!I>UtRS8rd@1i*lL^nl>ZW~4v=)__(+N*)>o=>hNnowh zSAP*bcL(g!s%+0T1=&4=8}8{K%4};bjjz;AsRePp1h+8;EEOi?CejzwtJT45uf?!N z5)`J9S)94W)eL;nw1IF-TmZ`Y%-vrX!)q~>V~ka>(_E zsu~P3bVvh`N~^lyVrUYiXr8&he(l&9aLBg=Du^o zR{e(CHQq>fjt?_%RG&~i0WOMY(G&h!iiyg6f2+1>=L14WRL|ac?|vBTCd`Wzn1kP8 zb2R@%J&Y1(%?_9`@}bXGZ9P?;Q-)p(stG!`UztW2+G(t6aGU{q18_Ec?C)X%u{XKX zh*jb@iX0P+R^7PDhiM#-sg?!8fP=xNWeT=g5rsl@2uhL4!t$9QMXCdv+dPDrYJ_OU z^^CBA{uDzA*v`2mO|X(k9W@M8x9Xyu5+V$QsA+yjF(vie{O~=w1{pCGY{sCRi9MEJ z5zfxk{`jH&Fa#W2xF3TN42r98SxQ}P?elrpC!;^$!L7qKsr!r#J*-m%U5-jPEG9xR z7pMpe1l@e!#-8CWvKn$ALVmU<70**3Yno>+L z+z@Mkb`9*Phxvj~a+yM-914nuo!20A!gv}7%_^oX5NSqOb?uT4YP4)xaNOLMW0iMQD( z{ZJaf#@qei6d8|qlYH9Y;BjvaImG*WSkrCzkYNk&LX!T&v!7&RB-vA3EO@kaD32^y z5;*Kt@2GdPOO4Aby_hZYLjZGTakk<6%j*athM%Ch*?BNM>t$gU`r%nG{b+4^Grr;h zDm9eF^}#IggwgurUSl@BjcEQRyWuoeg0qrn}R0ul6ZNq~G)-vrFFDxk1PC9znUj>iZXc z=f#i4pUtKhpB?Pmh+EFN)Fu}?JFSX>{~fb$tDT)ogTt=`R8HQ$*nQ^d+C3j#{MaoS zY4T3+Sk22WDW#u{U)qeFgZ_ta{!(psj-BewdG03b-}nBl<;{hPshm_*1(|v6*IprK zq!z*supuC7GT7hU9Jpkvr0#Wh`jwcFWYwj+!lEz~q<~9KY*8F|);c)7V-4IJ2mo7zv4&GY$hj-G9^<2#xMa|Tc=a2y8I!+1+9vO=HwjpCu$uZpcD)V zsor2b0_;E4hxH)#R?>soo&yw!F4cLzh(dMXA`z-;V6bfPATsfT-q;^kQuWY$2^ zGw3+b*?U5<*z?|Pesnv629P$T1Vl{^1kyiNv)=W4FoixG1Bs|Zafl*E0{uGdHDLLl zrsM!!W|4=$^9T3N-UK-)6a_(b8ELKY&6}=ye@>MQ!Hzng^0*$}>P^SaO=1K*oSt3W zu94Ek4VttC&6@TH@9z_wke67^(hcArM2^kpFs6ysU@=F>;81Gwg?xgfHeQR z+oxgmVf%cm`)nGh5<3H!l+HTdZ*JOE{)ZGzy0^bQK+Bkt8K3uU6(b0Qd=$fa^;_64 z#WN+Q_+VLwq2(GO0Rm-J*GY#uccsWpMunu|@3TJf=uC|Y3BR%Nv=df4t;c60C)kKD zw5t9z)~HkQwif5)w8pbsxGy5U5V>X7Hv2wO+6P{+VyI@w4&UbUuEId=aDuyTH5?PoY{fJ;2E35EH~!S zx*esn`WrfCL4h?qiC+7K1(i$Q8ot9n9si?uQ|VB(7^(F-TdCX^75Dm zMxVa?wM!@x&^y)1gE%xyor7t6xs&DJGMpuh(~;^MyGj-z&zh>BaMd_ca|hv8 zpc~3V_Z3Iif9S2Fmdx^`tlEF>K(YRBj^Qoec0TK7c#{sPL6T&I?{Su;S$u1KCJo~H zll2+xHN-6X#njaI(ZRUDmE#x%LPMjRw0r!i8x8->wonrHMtS9DG%CX zQhXI5wC_bn>oauSdGs;4P1jnpqt5!{z}%=Pfnr+L5UNxJYQ)L{dXDO^Vx@{j0f!8E zhFsX7$*J^=of^Jc=RPoH?oPB}&pgQt1)Ug!5!z9m>WB`?2Uq|q8U&6T*j-|73J!rX zuj)P$-@J2~?S_umaX^jiea+4QlKpVD24nI?0P?I;C$s`bb$?8kM94@dP8Y}s_&4mU9=L}o8s)iRRgwcuNP>vJ{{o^pWy_$y{1 z*tSRUtkZGgwc3gVMOj76ZX|9$)2zhShyu|zAW{_DGnKIIrjwGmY$wf5CC2;(UJwW5 zQC1Uoj~9(9=j%#JD7V!Jm1nc)=mGc)&VfCA+Y{8Q9p$GksW@wDbC(}yYMuARTeXfu zP~B(C6`QtBXzz1pMj^7gH0LJ`eB@2`hMfjMs)UA6dv0U*z&52Ae=2$~IFml^%c8FB z`a4q8t(x~>%7#8O_*;Q}w;$crp^Rwx+tHK$@F#zZQWd+iC=RKnt1M7iSW2;=Rfk8= zSZ7Eakrb74Byd&V(ar_xL5Pl!R`+e$qzrIVoVny5vn>RUj3a)eJ}0jtmY%VnyYgn8 z7uAs%6q3%KO7iQ-frr6}sj`O5)gn!VZJ|di1bK9W!9cKK(^N!$dn!dw$sGt2SuR7u zav;r|sxx>qG{#u>+mK3W|#`(H1U=uH_{JIEFaT z-~@T08Unj-&Gsl*$Oedv$ixgHiv_Z=P7S*MkT-HCA`onRmjYe(t3S`&30x3upjbji-{MRWj3JrZ>c#$u_g#NZl441$%VOH*EH1}Z; z`OO^fucM9t715Li6%4TVT>Cqwu?f>dZI+$WN`_V0q9j>6VlxR9Rm{(Mv5iG2DdS`2 zY)OlVPN5s^$>^cl3?4r~v23Q7R%hd*2UL(wWVZwv#g-X+Ca^&-N#F4&ay4n2HW#o; zFcI4n(AD(9tqI?dIRmX|tvWfYAPkI6DVJtvViJs-Ljm;5y4BIx@W9jBN- zpFKkSL&sgfV`amOKSq9o_Ta)WRKT^(?|~vr8Bf(9x0qgkrA%pxJ$`_82S}nMXzkjp z2!Y-q!~8A8fl?yL%>Y-!V_Tp3sjutvX-Eeel;UXXprfP%t#_~y)!D^P)%y*v{U9Rl z-$Z6-*Op_{dRA;N({@psSk zf{(|}=NXa^$+zCy^Zn+9>0N5E>D_+gN}UYiNBuetBWLS->~LH;un`~i7l=90mXb_Y(p7Z0c{ZMXg80Hg}5$w&NK>i!P9Bi~s+Vtc$axq;w5QtzC= zBBfMZ{B$E$S1c`S#-82=w6vbx;%zKG)13o6|H!pY{Jvge`a%56#^T(^;|q;FsM{cg z@%*2U6`>sUkL^O~LEY~>Qh&rhku|6Y?QLAkZu1ESfW1M_U>4YW!|(mCRH#|*th%b{ zUtOvE_Lwskx^U(;DM*pWos1MJGn~%WlGcHp+Q#zw!sfLX7L(_F)n!N}lj<@J z7=z_Avvuk{6$(RSKGv;SMn6lM>9&l-+H2nK4X$|2PkGz556>-mN5j=$;@5fi?Tdq@ z4<+8|&A}7vi0t$t4--3|KQL3f;FH>YZ`h*s(wo1q$1njCGzPiuqU zCOf83KuzMXJ?K2TUF#-{h@Yn8rJXHq?!cF9hH}Gf^!kAVSi`3&)KK%H7bdYXdYzaC z>Q+2;@H}0E9=~#cE|jCQ_{A@)ev?$Gi7ZpE(l2E5Jm5#a0qr~9uP-J~*F5HWjb{q0 z%akCclCp=E^)wVzE-wO7F*MXuWo3HtE6ttaJfGd=?F^i0yQ&1)qaBBW0svqDU6qkQ z#MZXGpki0#;T3DWyJ-qIe0nLrQ2pX3H5aM|^iFuQ*Y;x9r=aIElW4_ESt>(8Ie_q% z*;MYJGYPR6-1UUl-CVOT9|%*R47X!{V{zS@j`z`z;b=e6f<{b$;9-@z@_Gc7H2Yv? zhKEn!JmNMFbhGP86@v>YfyTVAXzeu+2UTlo3hKZ5Ht(| z;Hj=J!g?xDS18^MU<^hMnC&p&1x$Irg}b)+f;O5&Qm9J_rsB~ng{}VLpS?LGcL@PV z3fbpdB~aDHo0_ieQ=yc82&?--!u|x5m;p0jQW7CPZVFHpp`a-J9>78SNc?n-l-^rn zhmKGIFY?DRB_NgBs63{N2__pHki5;*T3Ae~zFU9s*Vu4EMwZb6ZybhBNDq;6o zK43g@WE)87PnRr!V1f1(Y#48y1^%rL9ren~6JVi=I6yF$m-(>TUpW?`-sJjo+%3`kdPP=nN4U z3xevB_9uq_@R(^!hJ1BruYTBD-XSVJ>|(@%w4%-SESL$9Q(Si^b(EI2kWi{E(j2@z zS)Z5PF}D#rftlR9l&#sR)o^Es%Fa-y*{UV!O;AovDLCJ&RLL5P(#+)EUFq9i@W?a`C-NRvuA^yoAWxHIF|y3{KoY>Hk2fD zpjE^&VdKe$e)(DlAt5r3*&bg+5A%bVDrGO|UB57T?!3J6H~BdV_H;9)PY$#)dhOk3 zFHu=PYBU@kl9nyo;Jbd+r*#j6c!2v&U2 zTb_&d@hDmQcJ$e59IgAiNqc#2mr&-?G=Y7KAc}aNe7NSjGriPn6B1YMrbKf(Cd=@n zqjU+pvHT`t#;8-TfTfzwwdLm%`JMOM6;c?&ZPbrx*k!1YF+d_zjU0o$$!Dx>6IgN& zzG92+!;oUl9ym(U<+3AUe+~alE@uJ3Y$F%b>BTvapQ){6Ixl4uXR-LNUII$!yaVU7PytE7+__)*4m=zMPkL=W6qT)v zn%|oCKUABmJwoYfhXfBu?j*TK*iw7OK4Y)dmNSal7~WH9{KXni%y%+e*Zyv&FVe2n zZrJ6sR@TX}qj$iqh4|*h6_2e|Mp)L>ur_C(tsmxDmnRV(=yQI$-RiXbsav?tm@L^& z)2w-7Jtgq2>}=TSk=XtAv>LMS>(A|CrD?$4^E}X*u@8kbe-S)Jl+`=_9scku-%nkX zontaXqn~lr4ccl^O%cr`3&+s$EGFb*r&(jBjaFXn`T9cZa|K&n0K6z#(|icc2AG zQ(`rcOB)BS6>ke{&L^tV2wZt-mA%L@DM_dT$xq3iV4Sh%%w*QB{_xI^^SQC6ISRCS zwBJ$MO@?Rtmw4!ab^?-10HgLCHj=D%VAf`Coz?{^PV4rGx`uffoMO`;H7$kg)yuKX;#1;CpUi8RZUWD zPq%sjH?x{48$+r&yI1vF%X16lzYb4N5Uj<=>?UpWZnoD|RFGKlVBOA?iz8_mGRK+; z?ClUW4^IW6_6)R2Fi%`m49Yk5`LoCG`EEUR#_R60er)mRwI%M*XO0+Vu|vHwqvAxc z1Vw9}D{53*uI0TgZC0qEGcz@zkbW}yGAP&`2qlcnAQ^>GaW)e$g^WqUP`uHp;;kX@o;Ss7aeYR7318;w9$R!lg0IqNgmWj3< z7=yxL5@hkXYW&~u14M&VzCuCG@{tozJVO#Rix=DkLBJ~r(fI_CCOc@-RVU9mv)G|( z4+ktv477w85DU|3v`2WT`oT|*=Z}3|Vtxk~4)BM1PISdf6n7&gup)ZYt~z^XAlLrr zLOqKP*;rp5Ds5GgQz^G}=i=iwQVO|)2zBv!rq3+3fO%6jSMX~QzQ6X?-&dPVwc!T6 zt8;e92PH(>DOrNp&AU_)3y(_>K$w!59!9I4P*e;qHay%9XF~X~FGFJ?J18BdKLxR3 zfdp>~3MmavP&l<>LD6~rFMmiSLVQPP$PS0Oj29F-&3Y z_Chc9&({}jJCGeq?G5@!>Bh$*8lboAz3Bh==*I2-RuvbeLmy?ZBBskpkw-cF~p+&NpnGw{P~r{Va2vN+prt@Gek_<8RX z53F?#xN%Cqedf`|*q{uy5!WjTAD`k^YDw0{XH`CbpGrXw#=OUPVb$?cc6gz%S2-Ln z-yGAxLt9B>`5mgA^tA7*T9A_MlZS$geY|@+anM+Xc$9mZJGI7r?^t`Kw|M9hd%LT% z`19J&)hG$+awk5uO)Gt{I7h1lDI94mk30pYDntWDagVu?ZwqTZBn|+1U z%O|?TZZGv0=e@PX7SYCReU29{1n;LwqQ3mG-ZalcZBywX>;B5qH9s5r$XQByv)#`@{1*0L*%85$s=rV z{bPVWy&dqj-DoKZ2Ai>)b`!d&78jnb@i@zjeVKNV%RI5NX#u1G&vzgC_kX9q>XB&h z!H8I@D1kQC4&@a8EJX}2#(Xft9FNp&26$Q?q2U=UjK@W)gV?S+|FwKQXFDLELhIQ1IsQAka%Ce~^YLL`l`~C0X z#(~P}*spFsfHYP*xOd)XJ8br0f9W?=(ReT@skPic9N_d>jK{Z@Usz>1PoL?x&b9>= zAJMD5KnbWy|5LqA&xmF9yo27w>GfT2b)OXkxFdK2?gyYZeKoYin7WND_~Mmh_@`gO zMNuI!J~pIsQKJlaDh+AB!-zj!+o7aGwP>*1hqq0)L95*R{k!09%=0~%UhC@SVh3pb z$_#|`sZ8Ut9Qvp)B1?k<4j;k{_CnU%C60`zV~Sa9+wBLenZ>Pmxbh(gA{gb8Lfjka zMTY@zG2FVfx9=UJGhIW)SS z*=J!#x|W(pVcEQysdbk1xRXb#P?(Z*53X!cI)D{u!MomLXMAX!<0s*a4Jrv8J)4;g ze#Ay8ajeYxCEA}b!aTJl4e0y>7voMLsuCU8=kJB&w^LZCMx}lB6 z^WOZar0WVuzhxS1j{ag%K>CZgsM&l^QTq9g>mIZE@aS2s>k3Fzv*xaQSnH>YS^l#H zq_6$NmqBRm%lTtgJQtOhk6P~uUi=c#ejr;@9HcaP8_yBq5h63sZ>-z?+X8~Xn^OBo zkfOaae2d&QyXok)aot%mAUf2oi_DbiOj=a{91{UYXz1wpZd02b{rR`~McQYM;mHs3 z^B9}?h#4^@3!aJxPpU3rt))SYXOR5LG4fYr-X^}yE|~@ji|s8E1$sGtz~0N^Zimp1 zYI62|uR|oqE_qW)N~-)z(N(GkxifO`3w7)a_Yx%z@AwN=B)kzE#O7GZEWV(kkv32b zA=!K)UCh>qr;&9I1eZ?&P~n^|0Y4*aiCB}zirB)Yp3EJF{(Ptjbz)=F81@j^m<|vm zQDye%$+}dB;G%jv5xieH&h}|%i$E&^*+!?ck5WV|YfiZ}&V07NGm1+LU*|mLqPlL2 zK5Y7e8T)j^%10?UKr!2zW0~|Xc})u+v<$AmlMx|XF?o7Iaz=6*_OgyL2@uw#<{*N` zZPVc6=-D$&M`-&>);gES-nfI}g)Fod055`Vj$x`#=1i63aKx0gB`dlm)Y*LHkhN3G z!cLKxf0NT;s!cm`*=4_*vKc%w2@m@r+^&QC6Y>{xTEidu3W&6l${upc)jbel5y%+U z+?m>}TXkiVt!zeD*ZAhm)MtBH0PLW*pWNs8ZLMmy%Pt^!nQI7_h>yD6R)sItPQCto z>bLY!dDVTfs)jAMJ+1UDNduxs?3+nZf`lnaZ@2@>lfv;F-qUqzHGJ6k9D~#I)Bh)P z?;mEzb=G-S-ISG%R~v3$uA57buy0-0Ra&-;l_2sM9wx4;KKH8BY1>yl9nll=V0Clb zI9alBGTxbx$@BPD>$KG(@<h621PM!0f_t$yf_q^wvtUhVVa-FT;fXTnV8q3#dt)16W7i6xj(LekVj-u$ra*Ob`;061{26Q3?<%gGVDP} z1HVB3JQP@bKa1c%NOmh6#Z4k9v}gGQKys6r)A+>BrBD;0aU&(H894}D{s5zP%Cxj0VbHT( zO@Y%ka7K9qb~M#U{EQyjBPLnJn>5~C4bm)tMo1zkz&Hn@d?IfwJ!1+3V2Ef8&?ZzspHHw9w8?u55LqZQHc2D}d0xEYxBz~QD^XfIBC0rbGw{<>h|8H8 z$cojg3El$G#=}7%xPDWpQnKPBs^_zO8+IA4-y+_FnBjN-F0-HZTKWP<`DXP$hdPkt0I3T}5A>xK{<6B*FyTyeMkU;6t^Rt^(GNBD_+bP>_^K&e3j=|>Jnuza z@~aeWq-B(m@X05LrUWE9uAz73+HGDY^xl6O!V2lIZ5q z)0r2yg6k8qWAm}#QUvou2Bb|a@7SImCoH!AsSp{>ZPZ(;&Mn2$l`p2V*I9xBSbQ_t zy0y0Vj@2ZLcbLH}k}z!=m5(B~ZC3Z8CBhSH*@@FBi;q71*0CjgxD#y4a{Q{s$Xs5# zrSZA__2v4~=uM5!u?vKGPow_GI1uHvW62HKaUweL8&M7G`8v}vWGUs7Z)3ldndraiudpcW=0u&V8YSdYzpxopG}(9iQ8qa}QRV0qmzA4Z`)K z0Ven$xFJ2xhwNjae>7Q&{G6QzZh&Va|9om2wFAos@)L>OU!U&hz1**dhc_YfHXb6+77r_u@T(z2`Bb6-5%y=&#Izr1H;m2F|?`impgr~8l0%&ttY zrBkyjANo}5`TCiO<+;}N<}Rh@wN2&&ZTot zwH`^ozwx0jr_W!tK4Ckn=IUB^=bqV#<)30s|J=uT?d1GZ&##)}FVx36SIT4W5Q!PJ z{)Z+W9X&p|^Vwp}*0`TEN2VE$3GXEM^34~Hz2OL(?%*jeD~$o~7>7^`vXotp|szsQz9nMDCNys`IXSB@uNOVi#;t*g~V?@Mc6 zAdE4Im-=;MP@~z&2cC=WHblcHdL%qR{>6d$TZIe)FP>4V!@kCaKz}c-_#NxZeXilF z8}AmRw090qj5Q`RD;IvWi;Ia+u7cyn)VQv*Se%|Z6u^Z1tuQL#1BK0Cbw4NZ0 zv}CQp+N;+^XGh0AnFhuZymIed7pTfA)3L-Sb?IKbrrFxi(mSZ`!C#zq`wR zItP+>(LnJ_kK$kCKA&XGixul19lhzYO8$!w{65Pp>yNx*@%O_Ugtd zGqpOJcYb{)U?aT72h-;1sq0Ox_7!uz87If8HC2Bv2qaMiRmdKBBLvS%ofHQfFJ5(I zBGeOt8FPQhU=L}T*FL9|8b;(Xbl!zO0wLMcMx=eF#V}G)@a91>RX$p;T6T!o*;TCf{OX| z&>{Y0x@xND43s--rcC2`v-*~CU#0OTQp(yJS1D`sdv)~T?jz~!3M||qSi+7!?8%ga z81N(lY6~E2mfIfPVS$NNU5s7q2{U(RwQ`DXV`N-%mJ5()gXC-7RNQ`J-Bv7cun`Ne zL_u_8e`ox6Y37Zc1GiJ);;d=JFPdb+yEVPmC!;31F{0Q*t{4os>UdG}knsbdrV>dO z0uFYlVfhz8HjH=A{}xz0%?i0W7=C%B*N@q01`a;8f>}?QD%QVj!lSZ3_5>J8tYnc2 zCBp{;neN2-wJdy3{`d|{CPTPpG4WZP<$K4;6Eb|s9tauJN!DQ?8{}&?A(F~$Z8P_u z{cReTHG>t)@~Q^QuiTzA7r9%(DJ5DzNQl^vv~%1w>(qZpG>KNpjpsWRhJGhcQRhB^ zWxGsdhFFbO;In;zuS_DGVx{{uePADu>ckZ0JO)zDJNdV-x!P_n&eAqC+aoobYqMSw z*?4KT4{1ODl-+E$uZH^e**-7bhvu?~PqC!x+gI|B$UAz4t!$qBMMY|ykrA2FwR^0sebStt*@C_*$1Y5r{zGdlNN}Vz8ca`q8YdHJG=`WykTime4p8I7c2JKYs`2CvgnC!K5>CAitC)BPUMp!rmXn zMD#5ajmDc{7S852ui*}4Ba?YZVmadqYhi4ne{f|ZzwwyA6z@dT;*oU|*|iXtlo(ch zniP9Bqu~I*ILMQ{x&vR9h(?~%DYj7WXL*@d)NhPkiM=HiZJ;2`B&|$B6uc}=Py@8 z1d4-!&pMUKV9L*IHVE_|r&116?U?bB6o|R^6Tu1h$a#9Wo4~*E=U<8|Y6MgzMk9aTLwT`rBQ8*F5U|BXp4#q2 z6wD1QXieg*WnVvC&4AEr2HBD5t}I9g!5mo(`%ON$!Z!CS*q@qd*1@hA*TJb#x6W%| zMy5t5>QTUCf6z!x)8EK`5;hFiS&TuN!KD;~*V0uh$Fi|6TZTf>7`)H`Tx*Ypug^T2 z;bXVfp)|9`hNS;SGdOB?dRaa&7c-(HDS0B9s*)@NP4bRYxWjn^nX@bS1$H|6GF4RyR9Y$N~s1uMKC5am^mj zpELBk8Kh`|2}zrmHD=D%Euk0kO`@Rs;_LpLo5(!Os>CqFPru$pC%u6~&LJ>u*mc5G*3aD@ss zVFE@TOd6uez|o|W%`3=%$Pln*)Mo8f{?+%rW+}8WnZDwCI*X342eM-t$ZQ-8g2|xz zVNMR9H99pp%Hlq6ko!a&AZuYT~zgc`m0w!19)nk^<5f7Py}Kih2GKG(q%A=BDP+7 z#0)I^+iHpm2=q`g3g$jg|4jb8O(y6$oy)v~_5F3wPi1KmgDG#y_p+HrZR5g=O>W|b zGcpAzI59L1`Ju=SW0Adv`-+N`gfK{12C5pSOowwU@O&+MkmPKEx!KMPjS;IQvV z(uK@5B9nI3asw&~(E+d}-kWZsC#u?zOG*csP&9#ff(to`C7}+(6w09rp=%TX3poN7 zgMr`!_LLzeNe^@>s1r~04Si3i1Fvamgy#4Yzi{0*)OEmDMHD1_gP2h#p=UFKypm6V zF6RllfNZgVspuA}AA?iFjb0~dv5*o+om5eiS=hr1hqNV>NWkDMtTsfoNI{7jQ{RiheSl-=eO{3bV0(J{Em{gPf_Eqv7vm%VG3;>|}g*b|zapdL|=@=`+u*zkd3* zeE+Un>-QORc)f0F>DA@~$zeOXvh2^*(sU-BVG#TJyN{EdY?lK9JPPu-Ko6k|GC<%l zW!5N~n0SvRx0saMQ9obSbnQs|UN+0Hc|u#cAu6<&P*C8OZc&M%M8jY2&FXeBr%x12 zfjFD8VIHlsOLb%#A2w4wJ7cB@K=IqHk2oHYSw%7}+xoemqyFfdu2cN7d1!^Cfc!1* zj|^-REWghf_9A92*Xrm``6~@PrZu$ne3Fg_x6}<83&$tZymrpaEWh>fQ|a=TtqGQ< z?8*b9$LzI_H2m&FaN%R7##j;gANo|^JP%Ejc`Ln|LJRQn$uFw+ys`_0ay z&m}LIY0_%gMb@k)`F*?2UUe)#J^7{47aBJ$-(<4A^M>_a?eJ+6ed5f!vx~MdJ#Vt3 ziTRje;p~$?e5KYe;o>j9&3J1@3u-KWGeI?msKzbzgg8DQA4}Z&rSU_Lo2fdhhe#B9 zY~9NrHi0+AvY7kW5)kV%Sl&4meYS|?fsH1=gS>>GPu<~D#%lBwva z_0iy-Umuw!7leU;IDujXd4d)JiL8miyhqH(W=(S*PDLS&A0iI&fzh*2pOR-m`8neq ziPFLAO?onaE_s0P-H8Ln1N8eEG+@Y|XxJ%|Y;MiGlWR|rZX=o-mIrj;_gOQ3p|Px3 z&#@fM$@(Qlb{H58LnQ&R?22#vp^Md^)&Z?LH!b9WOwT)pxX+rwQx|i55(b`x@D+o| z1x%G&&A^{Rj51IeT!5<3v$qbgoz+C^%JK_f`GHYDCq*nv&vWuP+tIA}-g;;CExnbD zDa%fjvo5Qqm1PJe;X;EB-FWbELYP`IwcZI>q33m+%z78VENLx|dyPrX{mK0l)l6ax z$w;sY$vUKy6833KkiF7G#RGwm=XIjUXSLN%xJz5@oUqJiO|26kZU$>-jlDnu8>uyn zc#3*O!KD?<#Iq2%8FYe;M}C}$YOT^ii#wtb-DJ3cgyU(y>clASf}Tt5C3;VbMZ zFtQ54I<(XDiP9)kGk6MitDTonn6n0$rd4E?QVdaqQya%};fUxTM87RLWLWb^m1F~1 zp@lV$ywiXsU@~qh$7qCI%eyw{7#kg0H<$j`D^^3e29v?-%}%h-6~_e#b7x1V8>^)B z5qY_7jree5*8wDE8IDe#udnvKsnuEbN)Cu}+3-0D`vD-ZlLVvzdy4qq_8zkwJOM=?U8Jhaq`d2(JMEr^?Cq#lZYl?r|!!Wh* zK36Ou^)PS2a`_)`9p=zI_h=AM26GS_xww&e^>?M^*@Ldc)-RdX-}-u4ZV^nQ>&O2B z2UWH*?5R0YBvF%LX!rzQsgc~3Ef~aef1R+<+O15&CrzKSY?%9!a79|Ht^`L>RY{ty@5`F@OlEWZyey+r%`>xu$SO=ShtFJn;rie4jLpl=B~*+^ zk*9z;m$UzXS)WR}Sjjh>>@Vc>d8#BbipZI|xbvne;;t@LBa?YZxb}-+tU^mLmK3 zLqLZv<;b{@AUfc$P&Iec0SW<#5=#{+!`hI*F?D?4pB43%s2liJ2?7K#=mn!BH8Wnb z)J$HiQIHNNn&6BFM^Q~K=F^=R@HZ>gOU*#7ZG7&xit3BsaX=7FbLJog11oWnF??wD zVGo>}Y)HxpaOq|(4cI*QnsxTRqwEQqOX&-4n5wdlp&g!CmhlaeB1jfBL0>50RYDGn zgfa1^j)dHbTRFH3BiMe6U&^fF7#7|D&(rE1*UC1JNUB02Vo`f-7Db)sZn8GKDB!iTPWIRzZOQ zupFoB)Bv+Lac(`UH+4PPeU<)zF7=CgIwR|zDoGeOyhyK#++N1Gj|;}vCQQLnAcapT zi2KMN;IU8!i$IXnT0HQ@Hw5v%zQki!g{mno3K}Z%y>8%5=oVh$P7Bx*>IobqUyLw8 z&{DWX9JMc_ez7u_Yfx-QP~fZYXG+R_))RLTUoPNRNY-P4X4B7kpm!CNFxCB;E5}1u zR~)G7{HTCeAr;p3(3`Gk(j~Euyket7SS|yu@T`52oMB9aclkMDU6^igL7E z_6paK`cf*j4nua>1(3%_ojrk@uWDUGju`rNBw;d^X5m5tiDaG-AxEgG-Lr(S*=few zgj#_F-t{u!na?QC3 zQL*JK->?+W8AaXPR&-DoEsJ^$}(oD`spK}1xQFe zdYtR@ct#4zAKUu$u64%G90iD7kzHhZf^2tWu#wGKV+u@18Qc-?_xkE5Ij@iT*eDm$Nf8~^^h z2TY@)05AV96oHiTKUM(NEEcT`c;JOVKRl>iJ9AQR<}M~U{92KLt(@ad!|c5iNHeEA zA!gIuL=C(Ba`3b$!9|oK@J2t)mbMo5M}T{s18IGNy;Gw}q8&Id!O~zP>9B>9*@>G{ zyJV7}dV`i18Lh=pOl0Qxp%dO?E6W#g+34#Hpm$S2UhOOZe8~%jT|y3{^Z1~ z00e%63*~IF21RRfxW%H>?cd{RJT9EC;KV4$Q4y%Ytz4n7I^g98Oq|_q0^1DiSscJ1 zJ4?J*V}iVPJ`!H>NNxZ&Hd4v*TeFk|-`+~fV|tT&_x$$%;6R9Jl9oZD{&E?ofqK*I zHDHwOAgn1`v5XSY!ri1B*bDDRPA3AqSD;qI$E*7mo7pm zeE_{63MJK%TL@7+J{`m>aHsaK;gQ_-6~M?lCjyTc3h6EC8l>g}dJr%+eqLt=OBEFj zs++_@H2$!!NfZCwbgYllTtoVkguch1*5$^~5eN*iHRPXDd&F5t^@7r8MP``+pu2c9 z6>O3ilx;-6_I&6bnr8v2Y->QRDp^Z0P?5zWR;p6h*?UWo} zv&0^W5nRn&7_pp$FcKTvCPYe;h{_O#(khM+fC{uIg8?x#{S0O;VS5SL8nTgw)Js>*Z2B(b=PHfxq zcPp!;@WRt;%)9ry6NUa~h94a%^aXAG%l0o{DE;ta!{1l(=#%I`aX8USxBUI}V)K^G z(}~KRWL~m_N1G69^OiUN>@YHL(Cr+2?vaC+9olrAc9a32;*6tj6&ToB2sEta+aLY( z3O@Y}t4Evx1`N3kesmzCmzxZ~dKC(;*6EwTkfq>w=aAxu)Tn-ldo8~fIo@b;+q?b#;d$g(RakXQz!5!QGKaTWH_lF%$oMo-18vY{o7AX@Hl)HdoEe8? zBAsfzK&hK#)7P!*_BXytv!>*V%kI^c;8m!nGBni#?W?mgsyu3JeUO9gw^E1JScKUi zvSua7FlCux)0A)y;Cb0vffOf`-q{j)T0&Vsa~JL5c(cSMvGGKnuep6)arNVh7s>0h zo=5D^X(!KN9N4(0OEatBQXlD<;rEN<9~I0V-nA9!bu%Fp={Nl`0-B9=!X~3<*l9A% zL!V5$$XYMVj}V?<=&EKQqyRD)CtM%7|s-KZs(liIKO2K(Z3 zwK3$PB?bPqg@G>ryOyWT+5}q>r5W$17_Kyu3vtjN zN5lD6%+0&%De>@wc=lj5MK(zUqswybJtD6INbW3nNQh46U+B=#d9O`^ZxE3O-(Eiu4h>R5M6{#^+R`V+`o)C&%^p z)auYOz>TDOtI&YFEtQe|0p*KJK!K5<qUm}MNw0Aog`2B-|7~=Afs3)wu0)7Y_QQZ-A z9qPg|sM8LRyKA7pM?vGVa{amVf(tIi6_Jq(=&KbFsJcrqKvqqwr{qwIDVw7!^A==q z0FpugO(58;7rE0{QNReajsNK}J{H&Js3U-;@v3zjjFjAtgf#uU8AXxxE$wUfSa6Pj z0QY5=ao>LXUk+~;SP-k1*FaMY1v(u$u^m$ya?}&Jpd@qB>BU0 zOjzB`Q4qYvvjvm~B>q^myOSrHF&Y&B8fm+xjeT zS|D--)wYX2fjTf#zyC{DIB-I4#`PVzw)Nna+H{z|zMk|O#Fnatm9EgAJR35Xj?%U} zP&v;zTmrtg`SCL>mV2bJKRX_2QEK{uqmBABM_apcwoW|vZq~7|5i6efdCPtubYXcU<@lh+*+c9-yC5HY zdBVQsoPD_VYmFCBpO3AitVKCza_MSzP$9+bLwDl*v%g0R-=E%3vRH+1BzyM4l=uI2 zX=HTR@WS-jnj-NQ>uj|;%53Xw7p8L?g$g@fQxK9+-wfGAgBdN=)kS`;1^%K8ntVPWwwYuB4c!kjUon$ z90-P@-BO%KH05nc&TwZi$rRjdw!ZPZ-!0H+5w67jO*%nD<|Lccc2OGxd|%QwJvB+a z{O_%B$_#CLRW=S)761|t8cHBsRgT?pv;~(_&#J@oZu?t@1Q09A_E?w$W!c=tW6M~A zD9+JVz(Ev-5Ap$vT&Sdm^QpF3nIaV9PdDGP!kyB1q)bW9j>0ughl@mv5%1h7aOhLC z$W|MRW2i%Rvd}&p9_I{eQs12yRGb>5fQDM*momJE{R4xR>2W|fYv`BsvM?Y<<3~(H zMhRi8&G?Yw(%#7%cUr0-K;y+f-QoZs)^xC-y>e-R<%Tc_4g1Le_VDWCuVQ3kHd~%4 z`IJayo|1KI;hDUWD-(rRX&ZOf5+0ebLC(S1U?N^FR@Izw=N_N8E=sjdJwN^#DnU(0 zUTr9~Z9lxuHisT&FQp9Om=N zo3biK@QT2^WaY`XnI2zx&MB0_zK}?O(SxCHS^sjT&ctqjxyOHm4dO~Kf#RG|3M%44 z=P-e+4_!GU>h^!dUH3bF?#-0{?{sba@Sy>!mO) z)5~~eS`p4^gsgo9cqcW-Svn9jgCjQU1}E@LnF%Mb2_u!J9=3&QMcGCb*Fd%Y!e4yW zi(FepADT)?1yOJ-nZeQmID}2*^T2yTPj#g>!Z<%2q(`kBGfJmvyizs-e-eYFK^YRU zEn4w5{)$D`u9=8FVW>93YU^|@+~bD{Kh+AAs6+h8waW>hFhUmlz4D@S*QFlZa%KLO z7s1csQykp?oSO~Bl}TbXYP~47A#3TA3h?u0-BbFDhkvO=7Fd8nLfgQH>?i}W5V+i6 zK?sy-pfkin=}E$1N5J5GJ*KT|-rc2g_Hu(jB)~e|>P`B>5ie7N(Z+e@6))uSrFnMB zEuF@wQYpuaq{`?$tzbzCYgG4HQ~inGizpJdE35@JHWHL*gC)IMtA*+cdJFu4Dg2Sz zQ6CfEiy!6t7_k8zF3D~woJwHBP>pGqTWV&Whe5zH4M(m4Q!KLZ$BeLde`h2T8rVi6 ztAw435$Ss=qi>$?4VbGlUNg#rBS7Vbpc*MjqbuyH2>>mN4b982Mw1BQAO{qDn|($z zJYbi!Y&eOavCtY@pEa6$57HF)q)nX8LLPOe>5D@La?>3Vj{D7o{r+vVm8|2N53#-3e5#4!#It zF0H6JxuCUV#2`>WX&Qt^(&N=k)8Fei+8TSy7n>meP6h*sQ&qlL z^rw%aAdPF+U_`NK2#Od&{2%{aZ%LrD5hNf8{zgdVO9lQW{ekriRw5{Oh*-B}Q(_f4 zRk!$ez{f@ocF3z`ql%=7r<$W8xB!oX&ghHpXX_RrfIG}b2s&LxdxAz$JQE?CkFqOv zg%y_lD2nI>$Jnh}GU8dA-t>)K_mZa1D+6B}4HQ=b8rjo>Te=d;{rwYE$LEmcS3Bag zLGxTv3fi;LB-qcH98vv51f zG}2Ms!nmvttUFf~ZvKG=tuAS5X;Hk|JbS)OhCK zHx-2(7Si8F#JgBf5ZZ$XY}2dFV%Wr4GZ5UfOdYw_Q8cbjP_m4 z=2{(2d|`P^gLMiQ@mW~$hC!=w$mxCX8`oL(WBSRYPXN1Ss%Pr7Mg{=rHVtEv?|J8d z!yWOe_|KeoFPj(E$SNMpCkZ*o9jxbe%bz~9yHR7iF@DBb8^tX7FXN%Ry+W^JU}|4! z^JenQ3L9ck3De}Dp@DOTxi9a{hZ-`!tVuM_j-qPR_yH~Y%>U7QzV}s;4f8w#2VvOj z{CL{VEA4vv26HN{;tKy%@~Az+fW_K-&dyc}e%~G9GP-+VbbM0V3@$UbeSLD@ID0dW zf8ys3ox8z4`@o@hgzPslTK^hniV*a_Kmzcw{P*4;^*QesFQyiyYy`;e3}?>UaW=>x z%e-gh6)TH*c~0~730BW6*4d_A)8$e7 zFga%J%BB7xT4KQ0_b+*sA?nmuU))JNj99p^XTF&7}DjU1TzBvAoQ8Jw=`}t9M zR}IqGFYK~-V1NkrXbA=z9}V!w8QhqgcP9&TgfN~eGnVosaYo3M9{%z-e&NR$UFIg> zv#2`v6Oos++2z&5GYfzhhJ!<00A`24y`!vk4?_W{9~{fZ7k4U*uu;GIi=6dBr3=+B zCrQw|$SFN!R}*=lIYJ{$5tB8KV}}KRF9>br4&vmSv!etVJi<79@*b`ap&Iu$etOAU z(pC~4E-8*adZ!}Q0`~5z*A?mD%u&2#b;rSk_p4nU#t)st{XX;sk&;77k;`Sa`y@l7 z5fPKoJ{od@+5Tdd7I_Lo;VW`Oek$2goct;zQmsSPxNkOoVKQdhRU3i6h@eAS2M{i8 z_L^|6P{5JE`05cPjVm#Dknc-_WX!K{?ocv*rDsB>Aaddhtc;-F=sCBL0C1SfKFee| zDjCmy1-%V$Jk&h4N2Yow;1}P$hpy4_zB$U5O&yZTfOoeU@{Je9pE(pGVpRBYp$(;j}>D>2a!oUO&pRqS-qh zZalX}6JunCT;1qQD=P%oT1DA}l%`!Szj#)G5oAnYJ&xoPDcIzYH;)Q6-lw1V4hz4s z$Y4naSbOcCZZWf5eY#u9)D8D~Iy8JWZ2B-SV%I+X2KwfjpOXYl)!bo=-yTJPAl6+t zXGw!ip!5Z|FvqDQw~{kM!hAlboc;}bN#*8snE|$O)w}c{(y!96)5ll7n5_CX*Y%H{ zTGCvr?Xls4I81La+6lq zhZ}2+HJBzqw9hk>Gw z%ueIASzOEsAPEIyj$%bN6gs9E&yzpPO?}+F68GtQj#Vo*$7N|V+ki{8T1Q(BLccLB zKgVnOp~r%}Bx-p3ILWX+;x$Jr{O4W!8J0D3{-JGjFk4VasvmK5oss@@W3B!GynCqr z?7x;*(PNCOE_@^?@Z&0DOUb=H7&UQ49i%^w5!`$Vm|-5I(W#uTGta};3;-d5-g@Eq}k+ zLWAli<#LQ`erx0{V^48KYB^MJgmcxE(R=~tonuI^N&2b4&6>6f9u&A1_Q{%2$(Dbb;0$hB4KFG;+7#mhj^)Xc_qsHb+uh>_& z;?IrW`efDAg2;G%kPuqfSlEDrW$vWNOSpFp^M;E^*3zNYawQ}{5ITNGIB3-!y5t;B z^+58czk;}4cPXE__U|>uvNSszeed*Zkw_XbF^5%EuMAbzBi2}p27bf`tOb5?57ar6 zD;%q1dNO0Bk#gKyJ1e z+Y{yl<=}UjZ;?;8-kwtd+0Gn;mxE|WP)Alrd&P`EY^JkhkK`S8105uWUcUIJ*U`bM z5r}S{xg@(oBll|6E7>D8EC{6Ef*~JhwqCUQR@dMY-}!39uR^2L>`O9k-(h@Qoh@ek0%AK!o?Ea8*;**d``N{*1OT#u= zCIVp&=>!WxDuSiOUnRgbU@WkEbq*rT0QD^;@&CuP4!3Lo)+E12x$rzn)-_f-yD$Kl zp1pnIiuv~8C<#~1;@s|jABkZt7@exlwDu+o;i($dW^`iogS9Ab`C)qr>0y?Dqnl=0 z2mJ#%69m^jHE{?;w4Q4DW60O*!bXkMyISLX{irrJfXGNV&?xYw*5PsDg>ii@V>6HS zGk#cXvmXVw;!m5~W=`K@UP1aT?=9?-MJ9gTj3azcIN_?c|5 zxs$OKKO5Fov-nyfnLaA=fhU?L$tg|RTYNuU<_kMFe)RiL8g`yk0rp*GpG));cn}AL z?5mHw)HJ5xhgN!j$#FSkSSPfg=tw=p(v@ab7{vOWfE0bAB6JlW8_N|Q76S11oX^e1 zEf}+e%{sxe`3o#)_fP)Pt2_AiQD_q!@i`qNo71-XOPB-alT(Y~kgJRFOVjGn9$!fW z7ue$Ri`asM0QiAs3Jr|F(if&lQNfg924<*qKwrWqBkL0>+b+#!Ep8nTg`Wk=7v-GPlL<3_Cez7wO=vmnFg^GA;ptq>Q=8 zle-#o7mFMKdJZ=LfN-F+2V+>L08-!s7S9;Yg}pFqHu{gzmF2nhkUR%>0xyUV5fq;x zW8vA56qqOq6%_P{o#p=GFOD`k^*7dZBF~|T4zfydxKZeE`5L`-s1o{k_=>nFn#7UP zF7O~;Am|`o=&fk)a8*^P?5(mIP?S$U*Km=h+Mcqm?1Y9IGUWw?;;S zF^U(A9ge*9920^rUiLOgy(i?{Rr(E`UNT84qpt`h=t@vIYfzftPjd( zTLVAxdbJ5lhj|-iO2nn;e51!hZV;8-eE9Ku2S5X6v~4*pn@)Z$+Y7M7-`@-~Fue#j zI)JRw9hQUGZ4pr4d1Ork`wO36c!lJK%g*Om-aMb zV!UpQ^lY9On@cY6X%5Hz^@yjnfa_D7G{>eA)x#|j(4-;ttUb>Ox;SIuMDfc7xaFh=x$FG4TFwA4?<2zQc zJ-zwf5?ag~%XB8EAvDQ?s61Upf?iJSZJ#6CAfa)KKH%gAx`8E#?QE+%_!!nqj>t0U zN_O2yBD-G>Ar+lcax1aCq^Z{2#oai_1-)wFLO1bkWA_iM&f=E4%Qrg5C6g#&Dw6H= z1skrAdvoB_ymLMr$a0Z}mr@m)zW%dG+Ae@E+ba66#xJ{U@y$>kc+025o0`(ytb0I> zC|B>sSv0;0%UYZl&p=bS*YpR2IPoHWL)Czn*D1(os>#s=^y5(_YGvIuMKAT2A7Vi@ z0-qFa-19>?dALP$6Zow-=s}4+eTMvdWc;Z>Ejp;vj_<6}&LK&SaYuD%Ua>#L?hxK9|y28p$ zaX8udKYqvYGo@64_)#An_c7_Zb(uZ$;qV&*mE+^NsMqkG{^Ez1*U39r;}72xB`+#2 zYUE2qGYS27D1cgy|G5uqZ^f$gz3h&I2RGDx{pMF#9|LnV2zeH(U*FR??i z+3IRhT-1CSE&udycqm{`w7#ZDm+iSNJQzTU3RYTf{W>{$BQ@-Fe zq5QJqjst6-{&%kiqd|@QOdenLK#OL~M}Tf}deFY2-@J{|hHwX`+2LWCC^4)|XAG4E{ZiC6!g5EO8Ho#=Mn-llwR;c%cT zzvaW+_u{8UKhh!>x%F$Q4SjFgVSZTe*3(BsmTeDjpMMRtzr5p4cwUB3g&Bnhn4K}8 zl#PN%US5`JPyTbj|5n#a`Hym&N^SU#U>ja`xD_t=C?t2W|jt2);?Bsh-T(pxT$MexoH8{=uxzVNfj6QH}qxSmi(;v9IeBn#x z;=SFkty^|8zsqJf*~eC`d6|-)ev2 z&gi!3Xa3vQK6BAlpSd_<3Bhq1z;}m7N9Sud zwVw)qY-}Rxo?b9Fq?13F?z1lw31mdqVtL>$1>hpl3(b7J-# zq3JC|os`;z1mGWDbTrTp%@Q==_wa#>l{#?nH9&^z>&O43e5?sTx>M(<>UL#OzW|V! zNAY@lrqxbC@l2Yu>xb_!ox}b42%HvXd{G6Rl|BKFfg9|~iq%#k>znpOkcU24PCF=I z#}Cw+=`W7eYlmAHqaBu$6-a7VT#JyCz#W-MGbyn!b!^xldEVT>Jq9}rTO}?)(BF`2Mi1Mw3q9fw1mU)|iI+#^ zRj~|D__)<9EJRNo($&#F`{!jxi9vFjATglc9gBw}5VyUbM9Vlfr{(oK=J4+J%s=RS*nBer0|0|^N;oEZHkuEm=3t$zK02W+LWrB4Q{zr{ z=p$?+0&o20pOxK1BB2$zi6Bk-XI>ToSS{X;;AJwo7Uuh5yNgI70pMthRV4uek18SW zHeoIF9D)<*J{SiFCvV1obr(%U5ifS5_;4gK2W^fUq}q9g{v-FWbGRFWASmWiGm2N; ze3bNn_)#rxb+c$l(C~@(C_+zv=*NeR!my|S6HA#xEiFGVW14NcZ3XfZYa((R>8xECx8Ldvd*0b`XnBkeLa#X6{%_ z$Ec7h%6HKMqULO?Gh;Z~dq=2;jyjv&K@wmO2~GKA8#ikZ5k{q1oaQ}wbBWq2VkdD3 z<61h~?{vH9IItw{RBypN<6B%a^|8ZH+H}&xpbLrLR=HG-1W?E<{_0J42?K!18!{Z8 z{CMec>kLMO1!#77?YhpT+9W0T1t7HROgBlwMUK;UoJF68buv^^t>j8@Z0o+$3}^#2 zM;Bn(m48>heApx` zBAlY@h1u=R#*k3Dz2G6C_{KMGnFh>JtKu%yLc7nlRC<%^QBfY6mJw`rA?%=tTG(A` zSGANEf&!%CBdAiUFFit9R5*a^gk!LCb9*~IBL;BB;jp)R9!8Kpbrou`VIfFM!x82R zHLIiB+M^qke+f064$vqf=pB_$-cBe}7t@7^JJt4Di&O+Z(w=ZzHi)KWat!q|R%iG^ z#WPxNZ%X^GO%nMoKlTkV%tgx@n%yVGO>w?EPsqA+!J%vJm+rpw`Q<_!+vvn7&&^uSIoSJ+1OC@$>6F|(=M1WN@7|N*500134 z5?QH!V3>`P$gwm%+(d#3VXQ$;x(!biICQT%BQKDyg%sjAz}dL&FN$X#s70}X&iO?Q zozATC_NBWvIf4*>TLlnYn(anWpC%mU${N(LQ}Rxsi?*_}h8O%OA*GPm;KpAm%}azc zg0v}uWa>=92b3uZ2I|9Vt;V?0=>k{V?4ZI;a8xg{$bTUmTyASiLdt(|R#1QAM|YQC z$aKUmC&9j+nwj0WCSnB2>e3*N7J_Tj`L>#jB8?tHcvOV;fu29Ae|XV4y@Pr5OMU)R zx6qHrSU-#vsWD@-@Q4{ZyZ}}Tfzr$PD=i$fDg!E7uir6J3P7{1FZdI}4B`SUx1EP<;!^)3RC22$XvqIk@2dIAB( zN-`iX^ARXX_r%8P>c$ryEMG#QU^`;SO6|%rD$4Oxb_z-wGstjFjayI z*aiZ<=D$2kf%VWer7?*O4t;tHDDiHzIAfxyt?8Q*F>zXH*RXp6C`Wb+V>U<?L?if@wDsHM=ss)LlI2aN$fKvr%(i3>NMkl-I1bi;4S8eXG z16!7nvnr@S)ub32Drm5B_O84`VMC-sRt#_U|u96 zm`@hFxF?}#LKnAVR60`@lsdoFruv1xb7qH_;t$?hf)gca5QFvubDHQKUczpy;a1vhJ3{%QO4S-%?|I*Rq!dNQ17?-tnwjZi zOUx{Y4s@feGGsXMIy-s`@Vt0Y>@;kPCM5G96zmOe!uEgwyzs4S=*dr(4aEopV|j{c z&q&Ux&nTWQrQATH*JV#K8uojAu(E*r7>Rs3eFf@Kt^ix^Kop_0(>TSPX;*|}5VxK2`CLWph5sQ_7bCIS z2Ll0|<9%b(s)!UK5|$$Z3ksz=lhP4Z%v*`T(X3oaGapG*q^LHpLOL9thWFHf<6kvJ zw|;Wi5_-B?(MUqi=G)SML#)Fb7)&XKsS@hu+hYN0Q(9tpi7!Ckwmaxc?m!~_=;1~< zJuHo{8MfKfaItpS%*Pe=x@<}QV6O%Cl8*fG`M!+TEsCfGutse|X(_67@`v3ba&hOL zAAC*Ol(?EMrRZT4Gj;L4dnCoocYLHETEv1-Zv8e%62NE?`bbC1x@0s_gT_|m0s#?C zPyTEJe&ZcZf_3Sr?;FA#jt9&Gy4iohTGcyjicj6TZ60+_t+=5CRTI zr;R`SnIRnP6j6a5nvTIJ67ox8X$7bl1BNe7%X+zHx``*%ujBE;v;6tM=+?rslEfk3(ckwobRV&KE5vI7w9Y`q-0%$f6xBI>gib4uRL@}i2 zef3SlXraP|ByAEDKn(sI_hQqvQHUzvxWaxL6a7r1o8s zEZXAw-!7lYC-B-`LJar^J78-%g(+V=C2|&5xP_}nkb=%b1K5N5i%a<8t27KZhi~yr z!xyyxgQAw+pd3dqkx_J{q4wuP1M`coN^-$8UNvQ?x??_UGm57>WD+@zT{fm!LV9%B zJp{l>fMZ$lwdei((XxCI_G2u;I>65l`bZW~me6DFNE<`u9W1rO#{}A;=j7l7~rM55QCLqSG4?jH$!LV3B!|g2lGUtdmwD zPZm@Oyp#!=OxS^vQY@bLD??LGx{!cwU_5(`%vhs#dUzHC^NM9f+RCTc@DSU@-_E~mq# zia>YCOnLwtt0gH7H)`E}pqwRh8!^cloQXnW{JSHnD%qN@GIpl4K&P0SBtDfMHb{)q z6J>i&F*saN2)-HKrWNUUI8uOc`=LjMEi(3NjA|w5hb~sV*sEj?j78}#(Q`)|>m0SL zYqM6***6LL(1k0?#^^J03L4Z;_vfoO3{6ypMiiT^by2cWv`J`eEl1xrnZ!UzRRmv~fOSa1fzLqp!Ys0F>YJuOfv zZZCC=d&`AT5n%K&0BwBjnqg%w3_|1%yT!1%1Nb$dmjxtkS^{tNnFT<;+{mB}SRX}L5~Fxc zqAbKvjTm|3SH7(|hY~!V z=zZxfjD3|n`9q}-4aY%tez5i;EH&yDl8cr!=JSNEq=tjYx=1G288#$k#HDd*^CCDP zn-i^A8fXuFb2wUI+lm(q77{3D$PbVZSDB<2Ig_mwpcO&5^Rt@b5c>a7Ht z)8x*SEjedLj>K$)G}9z7Z^Dgnh~B88pKxq@-9@d0fiH(+rm7fn!=^@YjeyVu;Q3Kw zW?Q!)2G%kpuh1pX>%hR&B;Y{RZ6@n*h3HSPX#}_uC~^%F$kaA&RF_}}Nv$h={|}e^ zAg#vS28dyF)nqP@H#^0QHdbL36%jE^QB>x`7NTHgQ3R4W;EUEZ>^n={DQU>KF?W6W z#6_La2RJ*5*+#fS&bKWv5Bs6X!^lMa{(L)_@2eY^2lj*ln%b_Y+_W{|Gv2AZW20~0 zT@H#0;qzN(V}I9ClCQOHrAE{dnFNbz|~vc$%O(y&gz zufXZc z6Jt(rZ;UOJU5)@<5h5u-({}?jMT>`wzSxPRAG8lcFviOwi~(B8%dw#m_rp8Go6=ce zTS#yu@jicR`AD`It<})Cy#*A$3bNC8_3WFB}jhM!V(@{}$vjkq_N=S&tkSfQK=8+4vI@v9I zfnEY>w9iXhoC$K&oU`T~>#mb@zN+_5nSI)A4WgG&AF2|!9>YW06Hr`bn9>Lu%`!oQmprq(52VQ2R!d@V zkxzfN-FHc2C{6GPW$4rDo6C2Y+7X}QnFcsrHJC`_oi5tqQkomv0)h32S3ybf(3ODg zMWe)l@9rRF2!bf!f(YEZ=SThW2{CQ)Hv4W7WvbEV%~6Rb?Mj~*g9ghW>8lgY7%kuA zkFszA=}{hS-bD#xb_fU=yXcS4o*q79go#)m&M1-w9WbV@yJre@R24NrTd6%tFaR;8 zT_#^NLW{b!)tVRru|}v1U>?3|Xy8bL5L`&bVhLswdaZm`k+Nqofdu&r3X>#sQ9@XD%!M@EtQ>Qmv%C9FkcF4w ztJKDOLOWF6yo@qlQH@Ycyu_2+-o+|1T}su#U+C0!RPjy4Q)Oj{c$@~Hw^IX$_G~>mriJa0U_!HBE)sylCN&>4*6~ z$}=s7!lKt|kMe-+tXJ^5tug5kRi~ze@eh2y1TW+-3RbQuT&S_E=ocL70t03dEBlUK z7yCO$B!dn< z?e%-R7iUC!hyqw!m8(&)ssL5DwlDxqX$HNC+=1$itKK$j6(NXG#+@Jpe0J-T_>}KK zJ%)w$81oKcm@p>rE0Cyf*6U==RZAzG0xhdWupA_S0-Wmq#y7^wXM|?b3eFM}j~#-s zgjaYztdk)Rx$Nx@7ja)etc0D>aa$j0MruJ!DoGnQC}pD&y|6s_{QJXztTW%jY7ipm z^s$22mRz8WL4YBFgJ$O88f=tW3ir98zpR;-=z+$9V6)$19V};c4Gsk$p4`5-j6x`; z=v)nK*O@!ov?Va%YFA+h8IcA9_bhZOqy*8V{2!S{)78VAW<_WQJT^BFs8zGQt-R1i1en}yL zZ+gdn(e{Zu%7?NaHT_0phshgyO4^$AmE(hwFnCrt#Uy+&E~JZ!0D)E4hpk?z1<+l* zD9k&RH-w!hErEH@YZ05rVE3 zh?L6|5}-QVXAqrjC4HCxRBrW7u%nB(1KA`zTlhp{sJ}3@GskcIld^vr3S)vAgdj+! zRGw}~AFzc=)X0F8{f%`)S_B@w+Rz|4?4l}0D*wOs-Um*Ov%K@HZpyQbBAo7~nUn{u z)iqRWN1VYn;gdMoU0l_w9=DYNx8^2da2#8s%s2*2Y%c#GyPvpAsJy)1#S@dZacHK_yLh zb=6zX`}}{O=Xu|%f*csLtVMFM^hi6Y7I++fU$3;M+A*sRXZCvTygR4yG>w6PDMMx0 zQXjSQ?s_fETSog=5D8C|c>%ZI;n5QvL7`B;eJXW!X0;C?A-4#SDKw~D8iRt0ggF!{ zuu^IslT3?-MUqaqr-&lk%&-far8r#FPdS5%QBz_|U9k0sdQ4T7!*G?U&^f=Zz)<#- zUd%AbFjLG^hrwk{5)@#A8ltj3IiN!tDba2i)H@@Rg^6+P$xv!pANg>4A#~#0wQ2Pk1%BoS>M8OY#F^$Cq z5H*3t9%JHek7ZSLOu^(|x||gf^8Vn4_r;7~S*D9V!4e09)|g==>z82@&!GG& zl>4Q!{-u-|RAHdERc~$6v^FC##b6sKsTW~+4IWs7j!MPjWTbO$YWID_N`gw%;1tmN zPB4Z6P6lcYAO4F}%a0o}*8q!+2m$+|%9SP5F&1QYqvWs0qaD#ZpwlB2up0g=IU zD4KdbBA-MVWDXgkoJAqgAa-E44W->*`8Vk`9w%86KTRq>=_-UzotV5W7RnfHhK%j)B;o(vTC+F*Vw(6 zDP^cK0_j&i6hrbs3Hyi@0REe-n6nU-6+t!PDR$hen{X?e-2rl|8 z<``sjlbMOb{gB#hZ8Se;1{?_|MHbctvaV!?q2B>0y95y1I zJ&z-nC83}xOyVo7Gh_y2rar%rCq9vCXV+Q^a`_24{lkP;q0OL*-Sjvk567H9=n=V9Y?Wu>6J7KO#J*+Lc*qrWOC+KY`J#dF^Phb- zy+lzb9OZs)LR{{BtX1mVqlP-CF!4NCB|eoq_vkNRWd-OicZdrS%Mc@I^s5ryOwk<7 zHWXrq(;rLw#0KRgF*9;P4K=VW@lR@iLr`^tC8f$38RY9|mLm6MGQo!jugo#JkB=7rWgSd6+*D{>fg`SvQX`l3!;k4dxmfa=_QIY z7-1l(wRe6#@PMq?CNhe zd9ZJRCowLt_L!SX`z#OrNL0@-uFv414>93t6N|d%xlCG6BG$Qk-H8T} z7GjD1NEqT+v}zttCjH1RL|{OoIW+Z=rEuQ32|NvhmlW}iU&u&fw6pvXpX8ouB;_`m z@@*iRISqJUp9>d4Ju<|YQ+kpXpk_p-3|JYyiL6sxP$0z@G9tAhiFj|CAekZ71JrzD zw?`yeV~ADcl~RFTx;5?`V@y;)mzQIb#`S14{UB-}%f@>fY&TXRL5b7dTmCFPM|BAg zMJFm6QU)eBVE_G`V7ycW{^yeDWY78U1N=A3eOlS3pXA% zFy%BA+t(S*VQ7VsVh*(M4k?+&krQR`K#Ohjb6Oq;I=zTTpy^!np-@Iw0h2=37swI+ zBPYJBM}IW)VNx8H#}#*T0z16?7y@`mv+ zK4STF$qhI^nV!KzQ#_$g6QYg;QhUJ>He`r0STRJ}^E{n{@qS*Y_68~-01pyPc?#N> zwH4#h=#2K5QSI=@va%4AX}O_hjT?D%)Ns~DJB$ucLr^-!q@L~urnWb;4Rw_{F4KW= ztEeWX^c@uhNt-*NesNB5qgef$Qhl;SM#EsW@fXxEGMLGm#y-C#2 z1xz%(Pmj`62tO)iwQl-Ch6%kf#PV!|njI_<#>l^CVTxi6-C?AX7vcUk-}sH?zK{$g z;gl30(p?V;8<#Gja!4e1KmDHc6#A}IOtRA;L?sw}(sK-U@~znXZm%{%ED6tOm;p^h zhcJ;vpYNfCRFiMmMgk4;KwjMx=73GEVF2o3n+LC_F+EsD;td5skJmB9%OXW5g$pLE)7?B_nD| zB7+X?Osz@Q+wax{1A}LfN(S`q;=Ue76(%sfJ$*Ab-ORBtA8(t9f_R0xnie9?Q+FRl zFA{&*<0%-3f%<2Lz&^dz0AfN!$QHcr&vdfOaFxEIdka-sf155J)L4NGHCf7#09@&S27u&R zQbr{m%qjBdoasqi9*!0!WakB6N@=*lck0B`ZXq0eH1^8Qx*z!7?6?3Duduji_cop^ zFc069bEbS#*-$94EO>kl=hmQXY$y}3bi;`m5B_4v)%ga>%`6k_-CpUJK<#V*1a z2tnx(9$b=AnDg>93fDr?;{{sc-|&M_+f!+pVO2?o+OhkbD%~n*Nf;p$cz%1f;uQ8u zq;*i5;htV>WoEC2HQ*)$%d@JWBM&dinejs->AIiINK`aojj&1KRZ5g_qHpv=p}bhw z{iS9`Fw!H!ks96X2Hb2cCzW=paGXFG{|m!dQj?*rWI__ zuczLhT|rN}!36^6!+D=%4O2|PncHMZP4)bx+6XrzHpn<+x+xF?mIEob8LK zb(QR~*D2^5PsU6YBz7lnO3z>~3{+?dBcRQC3 z482cRNhGP2f{^U=joyiiAp({nGO^(bFMD{_H>7p(n0rKv77r(eyItd$>$rGkH z5Dj$bO-fQmBZH2-gu&y*J2Iz^x-wD_T{fT)jfJOlpSc-T1En^2sL9$45d+zQ>0ZEgg!4Zu8poBGM^Oj73rT^G9vDy;SEY z`nxO?+smyoQdTM&jM1i=-_uE{40xFJfT(BhxZx;9Eb~XiqW=H7GcVsCKt-~ z!iWh9Q_VBW($Lo3Btk`eu{x4#BZRB*8yEDl=gmI1JmT7>&MW!taF~}eNa*CjQ zCq9g*WxR%eLyTZ=5K{vRtpr-gQBx<|8l$Y^H5RhWJHr}XPH*yqSjjRvIt1Ft(u^=$ zk7qVQazV8brf#dTI%Cey%X_3iQ7p`Yu4hOe!`+kE<+u!Cg?-2xHEdz4^5{K&V;Tl| z)z8GR=lkYtH5S7X?sINXZ6|z$6{$p2jpD52M+O$mFCfZEMA;7-^x&$x6|q=L%0U?q z`U+q4rK9&em#r$mL~3~?KS@%DDj-ZgGkGy!GKMJKR6lL_ee!ug}zSd=(BIg25C>XXEKQisd$1pu|y(EIwcR|JdwJzc|_9=(;6+!V3dFc zJ+%f|FhO>*`)q?ZV8KT+l>G5urzeba=Mh}2Mq_~DeoP!DEfYT?Iu(&9xFl6)l0b1* zztyWJcnaClVWhXh0|7;5#Bd=xuX{sgol+CUUbg3fKe432*kAWg`kZiLrwuBSHg6JCMF=pC*Yv$VFX`YTN_FRKV8S^Yl<_S#F7HpI5 z^pqgl=yqcSmZ1bqnhX><=#NUoJt~bu5(lJNw#e-6_`~chKFH+~qEsZQki1vnL0^46 z`hm&0$r1V?BMh^v6t7E__>(~T4kzy1md_(>bre z6?+&bqUUZfOk+}Eh*;W3h_sL{;UBobz}^Ngksmm5&U+zu1@t~^Se)?~-bw;>-u zn#<&0;V1nwWK9yd`lce%Z;av=+9KuGj*^dbqjQZTxLLk6a6S8(TzX1tvNR&{7$ePP zQmVocAi-X*jL#lL#l2d1$#fE7UotGD*JCKCkqIFrk8G380z+pd2?`RsGoOPW!+*ji zmNa4jl5j?(ma398AY8IM(goFFO|>Qg3t}Qmof&tNb(Z7;@Do)L3U~Zy#!`@1a7wf@ zS)XQ-Aup@Q_@cTGEOm>_a7um)tcaH$EK>oez#S7utjkC7@8YZ+G^;89ZC2Ky+CYS8 z8yTS1!ZEX46(Q&=#I+GY&nuRLXKK@fYDQb^A<_7L4K-(wwr$Eb-50->l8t?#h3E*B zaYLs|huQitU-LD@oqL&~V?Mwbd!POZF|krwi3{%^F4JTPQ%@{?TUHYwh$A@UBK-0K zE5xt}Gg>DEU(*JVVMU<$jv5~DT1Xt94V#_GRz8^0a#kG%uU#ZAjQsPI7p!KDRq?JA$CVuB)~sU zS87m$uvi`iE8!$#t=u*cQvyjkG!se9pQ-W?i;yw(psH(t(Ivd?=cgGkMY9nsunzw~ zKD`QdDwY79x*K|O5E@F%N!8F~>_LMui(>CKbHBZ+RLOZYf(mnqKKj)~c+eqVh@e~h zM%tT^-#m+G$WX_*HPVdoDZ^YUWzaSP&GjNB9l0LGXuZxv69fF_5$$A~WI(JxmM(8JRa}@G>|FLM|s6c>0(M=Y)cx9WuKI z|30P2hzi?u@n_}GEW4ngIjK{ub-^>vFX#p})p63R;2isM7O1}D)H_Z`CeYPE#sD6c znk|qp#cjp%p({tgh1uY(hfe6`#bQ2?k|JnyJA(*oq~=B&I049Xlf|MRV8J&eee{dz z3Hd6d5xSb=Wd{-Uxzu8QJ_u?yHvmpDp|%2dsTCB;>1UnD^O}f(u0^u-?0>x|J%=vT zkvBf-W)~AyfW~;5B8W>-U~gmMps{GAIE z*(KsLdJeB}L`HW~hUm@!Yo1%XY$igfX&I6At}=c}CWswsFzcf%@!+rm!fyUVdWG1e zKmdQk>kGnin3r8K%do_tAT-P$hO|L zT%;orXNboi;2Y{vYY@_g-)Gh(Pq-hk>Pn?to}6S>Ov6yhF(N!@#FwEQ_Pn@Z%xW1b5|pJgeu2ocG~uOk zTsddMt*sMjMTJ$-Xac>tbjRvN&rF=93^gGmZgWnHrKt(jG4@30DQ{4CnKq%%pKQ{J(qM5m+E1f4a_CQpanUygRv)m2z6-z{@KFB!@p{I?z;Y(~E%z z+ocdl5b9R?V;Kt?lL!C{fBc`OmuZA_!*HHIus8XI9HpU<(t}8(_)tShcr!T0tZ-(z zM}i~S7w!uK>+>^+RKtTv1=91MTn-s=^GIfQo!Wt(rYL4+QHyd9RE8mxcx&3j6PXA; z?Jdz%DNElaItMy16UwA@&pw{5r{HD?Ww(seD0_JlQvvamm5NMA&jJrKnyckOQVuxX zBpoCy#Wcfzc3f!E13Z-9+VYFpacWRhVR*>~u|EC;EfPA~sLE3;3ibF)a^JerpgyIO zypo7p<8yL_KBZywU`p|}b^Ci##1NF_f&%lTdkLtN3}wC;3qwQ41qQOVp%z%svNX5| z?tp&cQBvV19VR3tvkxyG&cvjg0hL!2I}*rlRRhS}s&2!`^N1QeC+a~e5C71DKCm(^ zV_u@L--(EOibxH;-Fg=7P(k86y_OEAi!f1%+1%WH~nP{q@aD%V}$n!$|NlFBGMXv1Y2fi6}%q6-& z8`L3Fc8vXYfA>x1sD7hnb(_<;dV(jEAY%diB3@L*702a|PKt5n>f}(>c55Hcy3(W-t_d0&yXRRMN3&%&sv)PCCob7N&SJ1eUaaG6cCBF&a?&?n z%iT!>)lB&%U)>-4+4K^vh{xR%!RsXeCb~ytnKRciA>46I@q!o}NV9vL;iWllR83M@ z-i(Ssn_?1t#!qIq|1hhHP|zasaerii1tmReMIA9Np77%O6>fR1!xx2>8BCDIs~R7X zjzT&kzJL!rHteO6`_Fr2Il=Qnzmj*gkPXhKUD1i6s=#fq91vG!Lsg$#e6W)<;{)JX z_plGyi`Zm{-}=8V&&^??EIFX{0#CTDQ$)wNi zq73|(&o^*>K^rA4wNgCFj2bR(@mO~bWi9fZqYI zKivF@5v}0=Pk`rj4#c z*fRODAQ_7v8wX!y_olMu?O(V zc+qBP0~d0SWeST%I-r9LP*#b)`^Eo|VnoL(sSwt<#gT=4V(3}FEPNE_!?^{O#`9<_ zDrw9hy_y38Y13~%`8XP3BeqKTu=VPQ_YuZc44R;7_DRan@$wcY?>7a&ygt;jF3ah? zl>TUi*LU(BZJU=zMtb#nvW0*!8}HlZt&-(xPQPMaM)~BW1zzi0Ea*kt9Eq592R=&1 zSA;9jE8_K@SkJ0Px#9@D$Hh&&=W6hV%&Tq(~GQnA}P2QUf!ro9B5@-PLE7%v@m|Kvj{-?KA{Kl=~CBy9<} zY7Q2e-%?T-wA_7il+Vk5wh$bPp(IKXCix{^$P?;;-Aps)WvB?;Yz*%Vkkan3a$m(6 zosXOY!9?knsO`ErCl#%RC>qRgq0?;ky)hK;q%^Ek;b3&r!35DB9_O&ree14sxcZb! z^%i*XDGHD1J=!P`oGWf}L-9FfAdgtA)N94=FogF$s*bpLb7z4! ze6t<%Lu{jcWd&Gq&g%Zrzv30q0QM7=rH@9wwa=3zbseA?J@T!lc1#EZNPi+%&0SFm zv6Vpbje(%XYQcsVCRVWYu35IHKCvmVB2Gs!adU+B`8Io;>DLz7R;!D%vkTbW!BzeJ2k~FzfkZou+s;`GlHyMqgYTSv47@ zwy7v6)C#TATIsB~_5{B7TTv2)$UKl+ZkuGLzP#7SIx1EDpnN{;th+ zA7KCttRso~hO~=Pv4?8S7IOf%R6dZyRf@yn2Iht5EXE~t!bG`^rp;)xSq zos&De{jJ{(eISPMRhqEQn&V%hW??`xbZ{qU!`TU+Nw)%raR0pedove#P!3$q_4_qpQ(1oFZnra*&Z#hvL6T(aMN2I~*H1i%`anW9)13HN#TBUlJ@=BZn z1&CXcd$&IMa~JPvMsVJroEo(o&Dna#mVIf4uxFO)jBd;qmKi`dj1(p2gZ8PvP>a|K zqvHKrq5&&BMW8k@31zj=l;j8(nv^M{rOZq1 zC1D1hXRgN#TXj<-E1E~4g)k;WS5RPoC%DRC(W4O4^)>8<9KqTXz}909{Diy7##w)c zRK~Fn>624%Q?OXA_OM<27^6-st1Yu*Vd;RxH#nhlS~_V$_|2@R*hEkqw6*~DK)4X5e6r_wC=v(31%7)8NEz>Bco z^&5Mdb4&5Di1V}ijy>23n_+Wj$Zfewwq-9K%R1!BLzgZimw(VwY?hnlSue)of;|W< zek$G-gG0kv%ylaFJB|A*M;*D7rB)2v8Sn|AaN8ofV|#c zH77a9#0&&uO1dg~pfu_f#^xe+#)877&i-8YVTU|sbKD5MU5measb~H0Pi>owroYk{ z@vaGZf%trQ`@x-`iJHH*b9%)?c zPtUg&f2afj*Ou(Noey2*Z8_;&)tC*POUw0uDV{419*tX1kb5vf&NeZvz>Z4el?gJP z)+5)%0pPaSzjMjac&s!NKkAe!_SnfSj`fkh((DI$N%Jiu*1|~Z>kX1PoB0{Lvy<7P zyk7pHC-AcjmYmgXExK|Yt$mjF@TS&RJd4MBbY9rvfL9QVxw{UA<+xMva{iIhSgv8i zOslgQzvpj84DfN$>dZ3y9Cz%v;ng*+t$( z!H}q@S1}uSvx-9gh(BtJRgZXRj>WUTt&WqAY1q0MeKWYUOEaPK{*vX4?Ft+A*sdqg zx7HH@{=#Tv)F3Eo*q!DqNS)xX8FIYvY_RKu6^7Pmn7jP3i-LyTx~zs8FOrOgn!0vz zf;^k8#Q~fMf?@$NuFb<`wHD#a^&!qLAAt?0L#xxYBV0-Z$&M8~P=fs`Qelh7G+e?3 zG#Z2=VlU1%3r?9h^rYi7?AxZ~AV>3^+5aUJ@jm@fmWR?!beAZJ3pylYE{mKOp)RzJ zJX~mfh4(iQCs-2m?3A>FQ7;_JiS0%?=$L5fM4(?dM;lQHktOg8gRbK&SaFf_?s;B(V16|Z?^U`DsM-X>xJ!h@hx`r1gAZ#;cUhU90<19*35+O*#7;K#3R;}Vr~Aze4=K*lV1w0 z;O&gWaqbC_=G+$hP{q3LGle?~xc7FB@T3vpU=P(%G_JO-*t4uQUbHg7k?l6#_jPw# zv1`So?9#^0Ol2ZQBf_`amUT4d2wNM_*%dgS^4&2ivqyf{Kl$%|ZBOux9k2FY@7xu< zi|=jkalY_xxjqC9*ckBPQiG=iEq2=r3Z4;!B0;J6@43Aw#E;YFO8qS>alCTyzeA9eD<+x z_wEx?KlI@@e%~|A7w+8o;mY?x$z6M)N^t{{C@HW>^m7Rof$?l#nb#>y~%aqloaa`85a&=``LeUg)X8^`kw*YA&@yl{Oufa zh-9ldtMlBFDUJ7HxYeDkJc2%~zjd2m@ve0$A+biInJ1!bZeg^*su?juoD4a>0yR%5 znQzCexF9GYwm4J{NamH(nZ8prtfNiHpbnB_mUA>tvZO-H-!WtwVj2f zFq)6&kx&>$#j*&AquM62w7j@MQm#?2IGM+xs8j*uvNB3~b;wI|F?5!RAPG*|r70(* z20(&ScB0@=#Rxu-(|$+eosamIcnysV_^q*c7HV#Q?7dxGc+=#Ro^e=aWX51Mv6 z7h1njk{B2qx4|+L98KUCAuvnI_@>Vgl8r3mR5A23QxdLi2O^q8nT=X8N2J=+S48IrQA*4tD(Y|8> zr7;2wwQ;tZLw7iO^_MSNpdM=un-9~12CiwS6G4(B>NlN9_j?-<*OEXwIf zx*e)ekhaQr5!AB0^|6bIKxdnvMgm5($<=UxzM#p&;b0jShf@lTKD%xTDpDRyhY|th zD!B>(FuqARxSkj%OFC8h>yK=qVBiKzfTp!zc_`3>?AA8{#Kqur)WAi*mB58)6^=z> zlCcz>`yFUuLLiYhOp8Ygv7@eV3FSs1h~h6jvx!{EbPpbuD~@@nQqp0;OXVO>gd~dC zI;{eAU^dFo?OZ#T{NUOH+6~I>QqwzD5h>;Ft#5{8y7UZ@v2t1!Y$FN_uZn6d(Z<_Ymmgt{0X>Y0Gj*yaNJ3Z2`IBu%axkRO zG1Bn!lsq`W*))JrN2aYjjDC>)tL{~ZJGT0dnd;b2IaQ6iw>-}JzY4WZnjiw88D7vK zgWM56VU(&U&vbmgkOn0`lM|(ap& zHqRC9h1q@d1DT9_rhYYg!XcYJc%?(7rR?ChvFvg@l{*kzwIzpgUJ0z@hudB?77yq;tl)YgqV);i{S^{IfyBv>);a|a;hb!A&QRU+!7Tlw?xsK zo&EQ2iQ@hDI>LwJR7&o5e(U6i|Fb`H#1s=8)CpZA-yltjiR%g0m5R0=;*;!^95c^A zmi}4s!+C%9wIsRY%qDD#g$#IbrGep$&MvC@u-Pfcc$C)S-H!6SBuv{AQIMcA;ix*{ z=KRlIl6&RJ<6k5-Qw~_}oG822tNz8dS~PuP&h7l*l!^qS_KxNW=Gl%HA{M~q=jY0Y zDhv6ROJ(BjiQ|{%J3rT)y06~3{%bY+^N+Ywg?X|r9vrY35@}hj15_L!?2-DRx?dQ3 z_b<&ZPE9;mI==b9gC%S1>BU?*irP;vmfX*k?!M}H;i*U79opM}$|2?L{*u$7+Y_D5 z`-8C1d8A}LzIBr_AX0evdyiQ5fSNjg(x zZNE(d?YZPS+?2G}g(C=1`6e9F4!G=sZ%V|+a@Ji8fU}F$D-r5lQHQkf-A|B3yarR))dSqeD?p#m4>NQl;a54I1!;oTO0y^(6h3v^cMNw5ac$6?s2oqA#Bc=Vj z;^3*ppg=B4HjUxsy8qK(w!$3+DrHbVF=urqM`9ilW)Rw9<2OQ9OwN<*+5RZ&y`@{0 ziZ7k9OF?Fz70jt(nPDOWCnKir5S8o)O89!l63ST4-Oh0mg2v`O(J=|b`p>1!&b2wT zwbK3DpC##s$|i!btm79KXTJvLecSWxBc%S3HE;Qo%qxxJR(LO!ss{Nvd`xj9eI!^? z2Ea!F?txNSog2yI@Hn8$=uG9L1J|RLsiZRI;7QS7IB?ft%SE;~cy6Zv1D+_>9oxmA ztiUZ6$oVOJ;975>TtNPff>61jKtXCst;C;HFo35cmqsV}9~s3E{bQyMWCS6-C^<6} zE-cdW2TE}Wx61O^l#=Xj^9w9C%gf-VsXVWb1f{`5Qe8@D`cXP$xyYwsi$ z^(-u?N!i{4)gBgn70K=!;b@&+Oax`rB2$U6z(ynlQ|;UXB?tAm+X+zxC+6e8t~g|% zY=ukhU13=KY-LyY=&$6D%uzP89iQ^l_mTWlDWkWy+q^D=T-&uMoHeGvY3`}TUGpBk zBFeWWeMiNFw}jT~VyiJ_iXALQ0cxX{cryl!9b=#gn72SQjy2|%!UwOsD{9P!6#l|@ zg=4|&RKtF%$slpufS~wk-}YA*Q%&eJoyxvl6IgMh{-JR$p}g04rfx^ig~b!GwG>)Q zosoD6YN(b?R3?aQqkxLVbD?!BMTbg$=@_LU>7xnN)}hRWp>~YY&!Y$Nj<^Cm6<)vc$); zvV;kzd|eZ5$D*901avAsC=?PpF=l^%9pwQU;Hg&?3*A3{+qZL7A}J^Qfhi|Y21#oY zK~hh+>erK+#4jW@iEsWw{ne^TeDfDgP2xj0Z8tTE-#k-I;*PsE5kfGSOWWg!VJ$MB z{8DK_#RcUmd~k&CWRtHndt9J{h+w%)LA`>1Z8yp#JGsY~a{JN?m%q$VzWj5*Jv`Rq zf46zDIA%v45p?9WCKSrIE{h`9trg-UatKkNFv?nD?wVwh9dHatL9HUC3qzs;e!}@k zNJBZ}O^gRZwP~bU#g5#5mzk9Lz;UiUR-w`#m9BnT`3#{409?9;@SQ|#A@g&@?UgZG z;Wg@4RNaE0wW&q8N;^WsDe;%%ir(ndWTXT{#LsbQA~(hKms5OW#W_?tR0)cOtN)%d zZ=^UB-j}5EVce+`6O#V5>Pd2N%-tbOH(zi4kg$NQ$-=?yJn- zjvQ;8p1BD0NRRV1d(NGUi8lk&L~No*B|ddKbVEg`x=EfyGic#&MPs@-RmNBw=__qJ zz~Ycn`hCII(A)VtIGBgW36?C z11AzWd6kTXhnyK58SuaAN4eY_bfz4*Vkd$o6IS6HdD0JWZ9LSlT zL(?i2l61YaQr57g zg;Kjvq7`ZAu&X3Jg#;Lum++&fS1bpTvRTE&5-BnZP!5z{c;h>Zo>+jklxO#0<8^rv zz#&v38nXVti-e|UsxQ@D`OrD|7{Bl)z9$@sa$55594 z3vK|Pz`0ci-dq^S09mtumew$BY=Y%1)Hp-~WG-(R-;*Qy1)5Qj=)OwdRUAwAcQ3W_G~V}q^RdOgV-1v3VBNT8HhK3cXy=NgyN4$jDRU0CM2 zb5T2omJ4QYQ_+I1+Y!u+a#4KvfBkMCYO;rbF;q{?SJaV8#5|~YhKs>g5H@@S34c82 zXOcHS0hZM;_zgWrWrPQE5p7Y6#~;U6c~IkZ$jI|VsSZ zw5W~Q0Fpqi0#Yi*uw}?l(Gn6){_U^Q33Bvhzu1H+K63&_xm@fPH+d0Ddg!?w?8`YG z)z!cWE&jJ<%jN@&k#SpMFnt~AWUm*bHdAVueq|kCg`JScClqgJ zMgi5LXrY;Z&WVYb=Y>wTql=ff4}EtQ=+cb1*&C*VM%p5MM}n>CvMv3twqr?v&t zUON{+yJ&2?xrp#3iu7mLU~IbVz~^{$(ar5Y=0q{xu53{diLEEU_n%BTcB@Ibpfj_L z+QI?}-U)t@WX-+Pk|sB7^BtmG{^+Zgcgo9u)sn5=g+hraRujKW>X;)! zjO=5M#J%s2?2z?yR1?1cPOV?Kwf2T`=b5kXn)GLXcbsy<*U5YznVbo?htuzC*w;)v z{7k*jm^sKCcZKQLZLi6_xkAo1>;ALx+S7~EN4QaaymDXNTPT0DwBv2#uZzpqxx2Qx z2cGtJ9dY3Saw=;rgXLW2+S@O(u83L2Kvr}>KBAg)NSakrm|$vfY`?wz*Bx@D&mW+k zKvo?+>f}hKI)$eenA}yOHNANJ#%*qNoGj=TQcUH4Pgt$@S;wdBs6p*vw#h7QLs_j? z%g6JiuB^`nw-L``?Zh^B>{FG}2n?{Q;uzXugf}M5;lDY;Y^|1qSoCj=kqUKmRPlbhK%;zp(;=b{@ zxzJ@@K;0EgEy*+;Se6hXDa(2l148E5j+)&#lhK{fQqS*N$Tcv|iVp`$W4WLTGunt3ThviLhD2c4o2 zfr13&fL6@li~wS*4Krv^>3)xA!Sj%eecmNucC}CeR;d5ZCgs!k5E?8kjI>TPR9Dc# zhH{>uwN7MH9)GY@8*wfRM&t|)wQWo{Ck`l0P7c9{Dq29vM_GNW()JxJpn3E!1&OxKbUhNoID;}LMemB`LUeq?8r&_Ir&C9qIcsg_`D~Q_{T&y z{j_t{T`b>VkFtW3aNg=RW<=He!f2j6LDV9BR|0_SOGms8D-|fuG;XZ31cJbg^NdTB zZM3*yzTq7!dv1AjH~bG5?4uQE$4Zk;MB_U3neZLGkm@l83k!-WQqk^Le?x&ZRlR*d zh?8h^sM=8$y>C*>5}rCyXq})eGV6i!QO9f8aqA6A#9JyJOa=~12U_8r)!4!j1Y6Bv zkD9}`G*3_W$0TgY|G|66% zN|qkf?W1?Pi2VqqGcOQtD-+a>ir~huK1G!{bjwT7oSb5~xxbE|Dwn4UIKn-VSl<>4 zDpx^uyxo(3+<)vKp{?@ugZDbt-~Wp}CsfpTxPi*5?dMgH7L>&gk7x-(%QI^tyrVix z%&@=iG*t;`jkn#W_sSpcA&`)IsgDUc%aroWQ)a!JGsFWYlu2kd&_6l((`Q)?IL*R< zAYB;n>SSR+l7ydjVZiE4{;?Fuj&CuLHI^vc^rtV|XLLDEG@9T+ODs{~-hu4I>AtZ+ zHj49B<@x{DEJj$_+Fkimzt%Xkx>5JvKGSBoHY*HR;zGbwX;SC~wa^4u47WD7#69T7 z+>@-(4FF{VHxsgt+GQUbNy$hG9!azbIQ2vhIFTbJ)&g@;7_q;lMi zR}PzX!g44G6w#3zI3ykFSq-&`0NjoNh@k~Z(~$C8WXO0cS#2UN3(qB z5>o<8nMJmRoHQ5e0G7iiqlG55sN>|2BS{OZmzgtTA`|{t?b4=qegh;_2caW)p^eU4 zpHo1a`~U}XGf9ChK`hxn^%Fwq3b^<1!jTw0M}Zf`mV3+%lcqHQzaAI{mO)$jiiyG% z+@_lug?)ufAV{cEbxA2=O^-%STn14J3#EyZpP!&+?AtLJ3M(sZ9yr8u*y$MG7kg9= zY!(ty{6H9Wgh2{uBY-$ZM!~TZA0WYdIwGO2Mhrfr^jA1|rvv0Eq%9HmY89Ik>fU+w zN^vI=mVgI9WYFa|``rCu2+=t>lz}%b_%K|_e$b;XCBcSM-TPiJ91Xx71WB%#XbpfO z5Jq#9IfR_Ek*F?NDFNxKWQ&xY@*d!-JOEtsrwMbj);+)e3Z#xQGIfyHNv3UrWwunb zuu?zaPJ*!6F%6_j%)9EG86v3){Ni!d#EMh-*tJ4#B2@Y=bOV2^;CeLW7#M3aKegkh z2N2*D{4;@QGUP^y&4FL6k_y{zzS6qW4ui%f))y~P8Wa8S0i}oej4nY)Cqbe;;yio$ zZ{)7)>8&8;;lK1;6T8rJActUy_H*=uVNmMZG8cVpw|pbZ9F8SdnXB~?=p)2nl_^O* z+0miogmzSgGh7GhYU!59FmAu<=ZDBh4Q*RL2tR8DDp|!FcDjs;s(OTi7LxvkAw+P8 zsoi4gxMI7Kxj5JRtxiudI*80U(Ax?&ib0FAIX&>^oTZ&+~yoyEe*$ zERouL(3yEC^q9%w(Gc6X$+lAFi^qP?LorXj5i)gNbTZECQ}|%vT@Zu`wJ6v@S9v`D zltwb1IPKsnXFmrI&PC4X#4(2@1_xZX)MRB*m3Z7e=Ikkb^2cAsa;?p^`i*hxNM~ke z@bDzaxfB`n#HNn@;DbEP6fbg&`zv_hZcwX_@gNTmD@T`tdG0ubIbh=jJe?5U*@4k9 zqul!$C#u0jFcGcZ-Eq!$pkB(*yEs8=ZpvgYpI=?q524uf`>L*9p`;YdeYXw$)n}S2} zQ-A(4k`H%B zt=cv9$^_4gsqYOBk?L1Qb`)M0lTgxZ<_Jp0I)l(MS-wARZ?6=pS00R}CRj6oYl@k5 zu9lc+D2-oQ8haUe-QM`o@=rUOGQRFWK%yVf3}IKFJ~7f@(7xH~+(068{01fZyOnPe zd-&5N`8WJ2^R#<4eNQC9Ya-1r+zu~kv|JVoDA`_M?li$mL04N#q#nj}n!1 z3b#8N@2ey|<$Fl*tC}&^1in=s%N4(d#{YdsY31=I>2qU>B=*RHGH&KpL#y>jXgy4} zrOc8A>pVGGPb^ssJS&)YH8j|sOW}|7n5-0yOU#(GjDE|PDw!s^t45@^6hlcF(djXM zuymn-#jzTTtY2Ah*Ksa&te-e+UDNbuLn`Wcqp=Z6L}cDz@d4TQA`IYp+*V_Rl90*4 zdCt1ru+mZx^x;H9INGVwfCdpD>t(*jk1HfGC5ybKJ1%+9ZLnyi~k{r&@Y23u#k&=3CuxtZ7vcAcwSrAY*$-Sx@@P*vF z#1UfuMe=TIzo|J~K_RXC+aG8x9cRWSbfdUN_tJ$1#RVQN^J{aoZardgrvyt`@}5Vj zWgMBzD_BMo7({q`Z(rXQ%TJ8DQFMSnR!KawnB!Pd?BKI$78U{Z0H?*6t&hAcKE|rm z(a&+`gYAbA!Lff|9UNPWx3XA=@rpPuZ0BG%C-H37p*o{789(&K^Du##Z8P;wN{kZj ziMZ*2ssg6))FP!*3`9wPUJiu0aA;?Bbkv^1-&@@;Pqt!M!`)kPt1`hJ>AtN7EVLRc z6gSgtUa(E4fr<$XlQAP@8)2pwSUPMr4*JdLmB@a(my0;e>Wo79V6K|8KKc2PeaB1{ z)ame2;*ca>B~jnhH$;q_;}W5U>JP+b3;XlbGgRFe4^#sP8+m_=?tao)Gvf~zh*K#s z5VMx0X=(bOxXJtL#IH_#cdVi*dHz+7fAZ3I_NV$EUU56ZBWvD{aMM9E-Tv3dC*H5+ z`=`m$(|Z73id6rRPv4?jBQ}0R!T`vuk?sG>=c@=XLZtfB7NMv~I-LAo^_eUR(87RZ zaX=Jj|5i5jpS~-5iga=!TzP)oU((D|Hq`XzKiV!>OUi&q9~fV-CXOzLs9xVCiJMLj z&=#7|N;Y=1F>VlZaj5w859q1$I&8wdSZ7VNXLkBO!u}sbm9WhO)Zih2AOjQw_3@t} z3|zuEC{mb<@NI$FNj_YKiR*4Ag|)_$^U4wo)b1~T7K96n6V_`BRb5`qSMzHyss~o_ zKS=^!qxWx5Xw|KH(9~yGt=RRTYM1KmN-4|*d%~^n;L!^u_xJYM;U!mk-sFk<{A1(w zZd{s(-R7Omd&l4Ys+s12rhR$o3(cK{Xw-SG&gk|(zGg2?WB=G2>gDU4hzjETVrAm( zJW=Do+nVLeOG`&!b?No-_ONh?J3aAi`11R9mJ8Qi^_=&)rq{e?v9kSxb*FRRVpOgj zKk`6upjLYBbI$>6xZ8ac_NU6Oq`n^%u%b=QBU8 z4nF#YefFb~`?-C~XdmSEt{u&LC$?X7G%mhS4yJZ8YXl~*Yg(7M^}X@b%PW_S+t)eA zCampmj4KB|IBiWig=LJ_ZC7XEQPfA;=^MWCQ{|1T-1_KD20BB$}QzU;Dd_mYR)h!+aa~ zx;5a%f1QzBEF1-32yDh~S+5M|G@D@J=(85>T$LZn9NM|=|MsTD08<#gZJ?T_akA?K z*@b=Iz#uMx;IbLgss=dyumi%~$3M9esla0W+n zFia1wXt5F$*a^2}smjmy9t@@nS9m!cP}|j;RtQ!#D)Zm`(F8xGt$W|EO1g&5LByO~ z#Rv?XGU+505&;E0$-QlM+b1hy{)CaOYVPSJXZlJJQZut_93O=cQ`4#3etlL!RvZJu zhID|RNr$p-1ykW*RpmMzbh^`D*LOs5F!kk2`fU`S&&cer{%D)RVscz{Ka`OlfYdSq z6!Sgb?2R5mG^0QJUJWoil1g33Nk;|K9QuqwQ!D$U1Sgp|bPM|Wo1rnGG;M@@lI_{i z&FlzPA5z(FydGG{6se-pP|JR@si*GozuU9OHx~m)AToGKn{__h(3!z8W=%Wsm#v!H za`NP@<~oh_W;2AdXV|cw;IZtg>*lKHrnv}-OO@!x^i<8gb$1nbQ4CmaLoh*4)`6j& zgGqO%d;-IbfGj17u%e0y!?mX=DYuM zi>W}A{?%WB60@cxm9dHdor0Z|N`9U4 zsk9Oxq`+p{SMEsG&LM56>{zb5oyh}jNkRydGRPdzX1X(bD?buY#vKVx+7(Hb1`#R@ z&z987P3|VC6}(AqYv{u~g%3q*Z3vYfjDjZM&Frzc^+3O2W;@6||2GO!DR_!C{hT-h z?w|(%d^Fe^hm!ad><(6G>mK_N^9`R9E|6cEEd`wXSoLYVKEM++fmO`_nxQWnBaIi^(&JCXD;=l zGA;TJ8wKd)kkwWnL)fOaQ zpqCv<4lI9WAdHQs_$7)6j-^ljb8e>;v?zmsktR6HuZZlmkdsQv22rvUzJUxxow@uQ z7p3qt9g`T5+7G&=AkCK;+1>kpS=Qp9SFee1-^EWpM@j>^8{HC->MGHwO+K^xM@KAc zpZGM;<||b`_J$^;#CqsGEs}}DHdiN@Ndkmqa1GFWrrSM#o`^I1y`k?U znq9u6`}XXOM3~8dL{~v6MF$iOt{|9hcm1_?PD`j76boWb|JDPco!*b@-YNENY?CoC z0?NH7TW`nezBpk)=!Q1HMad|OIB>j4Alrl4z4Wyk0!L%0GX|Sv6ssUUds|PZ282vZ zox-dppbe5Hyi6cGdTo|o4G58DNyg_I$pSVVpp)w#f7M1&O#1~*tD3-E#^msyDPh_0 zCRphv{L-!aSoQ+X?8uqFd%`@m>Fv*DPnkaT%zD2KQVBf8IL6+V!T-s-*Sl`Lqe_iq9UwpLx_dxq8VkRqDc|rGSy;R^VkdvQX z=^6OlJ+L+l)b>o7f@#zL(fykj`hO<-%OQPs&WA?>Y=_^o{y5MFba~)79n9_rcbx9@ z#?GCkvaQ)k-?Y@4=Qnild`4`e!|(cpe}C`IJnOd^^vwCpu|a7#W4mGN*hWL+^%4Bi zr*zN%a5ktMo{n|@>BokHm7t(xj3-0d{=YFf|8o!Y2g(g@yJzE>?s{|%TMLIL?C%tZ zat3vTXUNcS~o~frQ$8levxvo;~d zaJJGn-ghBHH(Afn^sv(X@^1}CID&FMyYve&`s%rZ%JT>EqhEN_V?4+4-R2z`d-s`F zW_%kyK;kqv$qfD|i#6^`x$coy3~T)6saXHzo#$d~*}_w$ifq68v%__*=YrabYlq_o zLIbn<^mQAaWm|zv|BwFAVzBad|JA4LcYp08ryMzlpTl8Ufh|R_#3bHkQKTj%Adz8c>rv-MJlb7H4QVQTS9iQpcDI?4IMdh$U?(gK1+1Wag?#|Dy)}46up@EKc z58pFTyFnWHCx7AILD~)0<`n%O?4osARc>2rS?d|S<2ul~Z+vJ~Vt0CHwhka2E}s11 z7uGA9bqX6=!8*{y_D!W#AwG9Xovr#D9$Pg?tapFhX?T#H>OS_KRm*D68k(QGB%6uq z^?cUAETMMFcKSQtPHDXI=XLL26%2CkYtH%zG414%qvy-zqcmc7Ea_zk4*s#L7@8pX5MinA!Kjf5h zcn*8mOFhqD%-TaqP>U?QDxQ4u+wn#*AJnbeE*b8?b-}4*CO*(N1B8zro^#E7&0=}? zRlG3g+ZFgZ7Sdnsz4p1_g%9u`hvb237oO;F8hvCmI=$U`t1n)E`ti2EyLcGo4|!G| zZ1%i)RPpNmlOt;&wsuqF?5t-eR!v2&-TaiJX`-<5=uO|hY9?}JgTa0!n0@jOhje$g zz+L?ZLjkq|GnL&>vqDB^jlj-8^p{?Jb`n?%?8@kR?RgAyT|&rOAo`BI<$nDT5q(d* z=sUlm-Fx0N++lS?ou8(0<*Cu3D6Q#YCI3&;>ma9w91#!F*Hs_ec?txA0|SPi`A%-OG9UK!;-P(cMEyeZ+S^_pW;f=KmQR zo{y$xkOnb@0Bc6sZAOgMPifdd)0c8dii+tkDdrdM6&ro#2Om4m)0+=IzxKUiXVm&Z z8=RLuTF94fd(}%7)D6m;b=v&{JCyYU$=lz%;Rt>G;QPrJ)_;22I*eKO@Oi6b=QU!d z&z{$1_No&XO6jXua>fJyz&5@SWX5YF9)UL2_1K#hh>4@fnx))sjtxmj`cBPpj|k|a^Hd9J~+@C78W{LwNIu8i zA#v>Vh@E*o`WjShU9{IYdUl7tC0Uzzu>LBdbrA1<&+uj&hWg}%@0?c)tRtC?AO4nT z*+$Vi-)HWIvv|TRKY#M4hBphVr-EIG(9QD=E-aYakj>!*E`;c7ysYH9*S+FG0sUK6 zKwtZrwi{C9zQ*6F&s*$c!Fs#vE%mrSQ%5&DG)eNf$7ZinH1`$p({w9t41 zcdQQH)Ia&l6BnxJXR4xCnSL40HtffDwTFh8ZtWS`HY}fiz8A8F#xTVKXH_v@6NBz= zeRIv@XLWE`vQ+2t!e>)4UmNkCePr$9XLEFjRDS0?bKz_lz2-INWmqjtRZ>|K<)`%)|1(O4Pp?XI)4LPytV z)2&~4ch?$hInAM--#AU1flu{ks%MtvnS^=Aub)A82F5FKkH(=Ks>?rky41`~SZ1sM zS>qKll!^r!mt)JS?#o$LJ?p5+68Uzau7mrkF>q+#t$&@4v|7`0)TTB)(a>3))) +user_io( + .clk_sys (clk_mist ), + .conf_str (CONF_STR ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable (scandoublerD ), + .ypbpr (ypbpr ), + .key_strobe (key_strobe ), + .key_pressed (key_pressed ), + .key_code (key_code ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) + ); + +dac dac ( + .clk_i(clk_mist), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +wire m_up = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3]; +wire m_down = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2]; +wire m_left = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1]; +wire m_right = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0]; +wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; + + +reg btn_one_player = 0; +reg btn_two_players = 0; +reg btn_left = 0; +reg btn_right = 0; +reg btn_down = 0; +reg btn_up = 0; +reg btn_fire1 = 0; +reg btn_coin = 0; + +always @(posedge clk_mist) begin + if(key_strobe) begin + case(key_code) + 'h75: btn_up <= key_pressed; // up + 'h72: btn_down <= key_pressed; // down + 'h6B: btn_left <= key_pressed; // left + 'h74: btn_right <= key_pressed; // right + 'h76: btn_coin <= key_pressed; // ESC + 'h05: btn_one_player <= key_pressed; // F1 + 'h06: btn_two_players <= key_pressed; // F2 + 'h29: btn_fire1 <= key_pressed; // Space + endcase + end +end + +endmodule diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/OzmaWars_overlay.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/OzmaWars_overlay.vhd new file mode 100644 index 00000000..601c1d9b --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/OzmaWars_overlay.vhd @@ -0,0 +1,126 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity OzmaWars_overlay is + port( + Video : in std_logic; + Overlay : in std_logic; + CLK : in std_logic; + Rst_n_s : in std_logic; + HSync : in std_logic; + VSync : in std_logic; + O_VIDEO_R : out std_logic; + O_VIDEO_G : out std_logic; + O_VIDEO_B : out std_logic; + O_HSYNC : out std_logic; + O_VSYNC : out std_logic + ); +end OzmaWars_overlay; + +architecture rtl of OzmaWars_overlay is + + signal HCnt : std_logic_vector(11 downto 0); + signal VCnt : std_logic_vector(11 downto 0); + signal HSync_t1 : std_logic; + signal Overlay_G1 : boolean; + signal Overlay_G2 : boolean; + signal Overlay_R1 : boolean; + signal Overlay_G1_VCnt : boolean; + signal VideoRGB : std_logic_vector(2 downto 0); +begin + process (Rst_n_s, Clk) + variable cnt : unsigned(3 downto 0); + begin + if Rst_n_s = '0' then + cnt := "0000"; + elsif Clk'event and Clk = '1' then + if cnt = 9 then + cnt := "0000"; + else + cnt := cnt + 1; + end if; + end if; + end process; + + p_overlay : process(Rst_n_s, Clk) + variable HStart : boolean; + begin + if Rst_n_s = '0' then + HCnt <= (others => '0'); + VCnt <= (others => '0'); + HSync_t1 <= '0'; + Overlay_G1_VCnt <= false; + Overlay_G1 <= false; + Overlay_G2 <= false; + Overlay_R1 <= false; + elsif Clk'event and Clk = '1' then + HSync_t1 <= HSync; + HStart := (HSync_t1 = '0') and (HSync = '1'); + + if HStart then + HCnt <= (others => '0'); + else + HCnt <= HCnt + "1"; + end if; + + if (VSync = '0') then + VCnt <= (others => '0'); + elsif HStart then + VCnt <= VCnt + "1"; + end if; + + if HStart then + if (Vcnt = x"1F") then + Overlay_G1_VCnt <= true; + elsif (Vcnt = x"95") then + Overlay_G1_VCnt <= false; + end if; + end if; + + if (HCnt = x"027") and Overlay_G1_VCnt then + Overlay_G1 <= true; + elsif (HCnt = x"046") then + Overlay_G1 <= false; + end if; + + if (HCnt = x"046") then + Overlay_G2 <= true; + elsif (HCnt = x"0B6") then + Overlay_G2 <= false; + end if; + + if (HCnt = x"1A6") then + Overlay_R1 <= true; + elsif (HCnt = x"1E6") then + Overlay_R1 <= false; + end if; + + end if; + end process; + + p_video_out_comb : process(Video, Overlay_G1, Overlay_G2, Overlay_R1) + begin + if (Video = '0') then + VideoRGB <= "000"; + else + if Overlay_G1 or Overlay_G2 then + VideoRGB <= "010"; + elsif Overlay_R1 then + VideoRGB <= "100"; + else + VideoRGB <= "111"; + end if; + end if; + end process; + + + O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); + O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); + O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); + O_HSYNC <= not HSync; + O_VSYNC <= not VSync; + + +end; \ No newline at end of file diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/T80/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/T80/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/T80/T8080se.vhd new file mode 100644 index 00000000..65b92d54 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/T80/T8080se.vhd @@ -0,0 +1,194 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 8080 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original 8080 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0242 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- STACK status output not supported +-- +-- File history : +-- +-- 0237 : First version +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T8080se is + generic( + Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + ); + port( + RESET_n : in std_logic; + CLK : in std_logic; + CLKEN : in std_logic; + READY : in std_logic; + HOLD : in std_logic; + INT : in std_logic; + INTE : out std_logic; + DBIN : out std_logic; + SYNC : out std_logic; + VAIT : out std_logic; + HLDA : out std_logic; + WR_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T8080se; + +architecture rtl of T8080se is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal INT_n : std_logic; + signal HALT_n : std_logic; + signal BUSRQ_n : std_logic; + signal BUSAK_n : std_logic; + signal DO_i : std_logic_vector(7 downto 0); + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + signal One : std_logic; + +begin + + INT_n <= not INT; + BUSRQ_n <= HOLD; + HLDA <= not BUSAK_n; + SYNC <= '1' when TState = "001" else '0'; + VAIT <= '1' when TState = "010" else '0'; + One <= '1'; + + DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA + DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n + DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!! + DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA + DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT + DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1 + DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP + DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR + + u0 : T80 + generic map( + Mode => Mode, + IOWait => 0) + port map( + CEN => CLKEN, + M1_n => open, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => open, + HALT_n => HALT_n, + WAIT_n => READY, + INT_n => INT_n, + NMI_n => One, + RESET_n => RESET_n, + BUSRQ_n => One, + BUSAK_n => BUSAK_n, + CLK_n => CLK, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO_i, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n, + IntE => INTE); + + process (RESET_n, CLK) + begin + if RESET_n = '0' then + DBIN <= '0'; + WR_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK'event and CLK = '1' then + if CLKEN = '1' then + DBIN <= '0'; + WR_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and READY = '0') then + DBIN <= IntCycle_n; + end if; + else + if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then + DBIN <= '1'; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then + WR_n <= '0'; + end if; + end if; + end if; + if TState = "010" and READY = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/T80/T80_ALU.vhd new file mode 100644 index 00000000..e09def1e --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/T80/T80_ALU.vhd @@ -0,0 +1,361 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + OverFlow_v <= Carry_v xor Carry7_v; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/T80/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/T80/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/T80/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/T80/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/T80/T80_Reg.vhd new file mode 100644 index 00000000..1c0f2638 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/T80/T80_Reg.vhd @@ -0,0 +1,114 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/dac.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/dac.vhd new file mode 100644 index 00000000..db58d70b --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 8 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/invaders.vhd new file mode 100644 index 00000000..7bff683d --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/invaders.vhd @@ -0,0 +1,273 @@ +-- Space Invaders core logic +-- 9.984MHz clock +-- +-- Version : 0242 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.fpgaarcade.com +-- +-- Limitations : +-- +-- File history : +-- +-- 0241 : First release +-- +-- 0242 : Cleaned up reset logic +-- +-- 0300 : MikeJ tidyup for audio release + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity invaderst is + port( + Rst_n : in std_logic; + Clk : in std_logic; + ENA : out std_logic; + Coin : in std_logic; + Sel1Player : in std_logic; + Sel2Player : in std_logic; + Fire : in std_logic; + MoveLeft : in std_logic; + MoveRight : in std_logic; + MoveUp : in std_logic; + MoveDown : in std_logic; + DIP : in std_logic_vector(8 downto 1); + RDB : in std_logic_vector(7 downto 0); + IB : in std_logic_vector(7 downto 0); + RWD : out std_logic_vector(7 downto 0); + RAB : out std_logic_vector(12 downto 0); + AD : out std_logic_vector(15 downto 0); + SoundCtrl3 : out std_logic_vector(5 downto 0); + SoundCtrl5 : out std_logic_vector(5 downto 0); + Rst_n_s : out std_logic; + RWE_n : out std_logic; + Video : out std_logic; + HSync : out std_logic; + VSync : out std_logic + ); +end invaderst; + +architecture rtl of invaderst is + + component mw8080 + port( + Rst_n : in std_logic; + Clk : in std_logic; + ENA : out std_logic; + RWE_n : out std_logic; + RDB : in std_logic_vector(7 downto 0); + RAB : out std_logic_vector(12 downto 0); + Sounds : out std_logic_vector(7 downto 0); + Ready : out std_logic; + GDB : in std_logic_vector(7 downto 0); + IB : in std_logic_vector(7 downto 0); + DB : out std_logic_vector(7 downto 0); + AD : out std_logic_vector(15 downto 0); + Status : out std_logic_vector(7 downto 0); + Systb : out std_logic; + Int : out std_logic; + Hold_n : in std_logic; + IntE : out std_logic; + DBin_n : out std_logic; + Vait : out std_logic; + HldA : out std_logic; + Sample : out std_logic; + Wr : out std_logic; + Video : out std_logic; + HSync : out std_logic; + VSync : out std_logic); + end component; + + signal GDB0 : std_logic_vector(7 downto 0); + signal GDB1 : std_logic_vector(7 downto 0); + signal GDB2 : std_logic_vector(7 downto 0); + signal S : std_logic_vector(7 downto 0); + signal GDB : std_logic_vector(7 downto 0); + signal DB : std_logic_vector(7 downto 0); + signal Sounds : std_logic_vector(7 downto 0); + signal AD_i : std_logic_vector(15 downto 0); + signal PortWr : std_logic_vector(6 downto 2); + signal EA : std_logic_vector(2 downto 0); + signal D5 : std_logic_vector(15 downto 0); + signal WD_Cnt : unsigned(7 downto 0); + signal Sample : std_logic; + signal Rst_n_s_i : std_logic; +begin + + Rst_n_s <= Rst_n_s_i; + RWD <= DB; + AD <= AD_i; + + process (Rst_n, Clk) + variable Rst_n_r : std_logic; + begin + if Rst_n = '0' then + Rst_n_r := '0'; + Rst_n_s_i <= '0'; + elsif Clk'event and Clk = '1' then + Rst_n_s_i <= Rst_n_r; + if WD_Cnt = 255 then + Rst_n_s_i <= '0'; + end if; + Rst_n_r := '1'; + end if; + end process; + + process (Rst_n_s_i, Clk) + variable Old_S0 : std_logic; + begin + if Rst_n_s_i = '0' then + WD_Cnt <= (others => '0'); + Old_S0 := '1'; + elsif Clk'event and Clk = '1' then + if Sounds(0) = '1' and Old_S0 = '0' then + WD_Cnt <= WD_Cnt + 1; + end if; + if PortWr(6) = '1' then + WD_Cnt <= (others => '0'); + end if; + Old_S0 := Sounds(0); + end if; + end process; + + u_mw8080: mw8080 + port map( + Rst_n => Rst_n_s_i, + Clk => Clk, + ENA => ENA, + RWE_n => RWE_n, + RDB => RDB, + IB => IB, + RAB => RAB, + Sounds => Sounds, + Ready => open, + GDB => GDB, + DB => DB, + AD => AD_i, + Status => open, + Systb => open, + Int => open, + Hold_n => '1', + IntE => open, + DBin_n => open, + Vait => open, + HldA => open, + Sample => Sample, + Wr => open, + Video => Video, + HSync => HSync, + VSync => VSync); + + with AD_i(9 downto 8) select + GDB <= GDB0 when "00", + GDB1 when "01", + GDB2 when "10", + S when others; + + GDB0(0) <= '1';-- + GDB0(1) <= '1';-- + GDB0(2) <= '1';-- + GDB0(3) <= '1';-- + GDB0(4) <= '1';-- + GDB0(5) <= '1';-- + GDB0(6) <= '1';-- + GDB0(7) <= '1';-- + + GDB1(0) <= not Coin; + GDB1(1) <= not Sel2Player; + GDB1(2) <= not Sel1Player; + GDB1(3) <= '1'; + GDB1(4) <= not Fire;--controller + GDB1(5) <= not MoveLeft;--controller + GDB1(6) <= not MoveRight;--controller + GDB1(7) <= '1'; + + GDB2(0) <= '0';--active high + GDB2(1) <= '0';--active high + GDB2(2) <= '0';--active high + GDB2(3) <= '0';--active high + GDB2(4) <= '0';--DIPLOCK --active high + GDB2(5) <= not Sel1Player;--active low + GDB2(6) <= not Coin;--active low + GDB2(7) <= not Sel2Player;--active low + + PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0'; + PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0'; + PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0'; + PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0'; + PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0'; + + process (Rst_n_s_i, Clk) + variable OldSample : std_logic; + begin + if Rst_n_s_i = '0' then + D5 <= (others => '0'); + EA <= (others => '0'); + SoundCtrl3 <= (others => '0'); + SoundCtrl5 <= (others => '0'); + OldSample := '0'; + elsif Clk'event and Clk = '1' then + if PortWr(2) = '1' then + EA <= DB(2 downto 0); + end if; + if PortWr(3) = '1' then + SoundCtrl3 <= DB(5 downto 0); + end if; + if PortWr(4) = '1' and OldSample = '0' then + D5(15 downto 8) <= DB; + D5(7 downto 0) <= D5(15 downto 8); + end if; + if PortWr(5) = '1' then + SoundCtrl5 <= DB(5 downto 0); + end if; + OldSample := Sample; + end if; + end process; + + with EA select + S <= D5(15 downto 8) when "000", + D5(14 downto 7) when "001", + D5(13 downto 6) when "010", + D5(12 downto 5) when "011", + D5(11 downto 4) when "100", + D5(10 downto 3) when "101", + D5( 9 downto 2) when "110", + D5( 8 downto 1) when others; + +end; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/invaders_audio.vhd new file mode 100644 index 00000000..f16cf379 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/invaders_audio.vhd @@ -0,0 +1,496 @@ + +-- Version : 0300 +-- The latest version of this file can be found at: +-- http://www.fpgaarcade.com +-- minor tidy up by MikeJ +------------------------------------------------------------------------------- +-- Company: +-- Engineer: PaulWalsh +-- +-- Create Date: 08:45:29 11/04/05 +-- Design Name: +-- Module Name: Invaders Audio +-- Project Name: Space Invaders +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + +entity invaders_audio is + Port ( + Clk : in std_logic; + S1 : in std_logic_vector(5 downto 0); + S2 : in std_logic_vector(5 downto 0); + Aud : out std_logic_vector(7 downto 0) + ); +end; + --* Port 3: (S1) + --* bit 0=UFO (repeats) + --* bit 1=Shot + --* bit 2=Base hit + --* bit 3=Invader hit + --* bit 4=Bonus base + --* + --* Port 5: (S2) + --* bit 0=Fleet movement 1 + --* bit 1=Fleet movement 2 + --* bit 2=Fleet movement 3 + --* bit 3=Fleet movement 4 + --* bit 4=UFO 2 + +architecture Behavioral of invaders_audio is + + signal ClkDiv : unsigned(10 downto 0) := (others => '0'); + signal ClkDiv2 : std_logic_vector(7 downto 0) := (others => '0'); + signal Clk7680_ena : std_logic; + signal Clk480_ena : std_logic; + signal Clk240_ena : std_logic; + signal Clk60_ena : std_logic; + + signal s1_t1 : std_logic_vector(5 downto 0); + signal s2_t1 : std_logic_vector(5 downto 0); + signal tempsum : std_logic_vector(7 downto 0); + + signal vco_cnt : std_logic_vector(3 downto 0); + + signal TriDir1 : std_logic; + signal Fnum : std_logic_vector(3 downto 0); + signal comp : std_logic; + + signal SS : std_logic; + + signal TrigSH : std_logic; + signal SHCnt : std_logic_vector(8 downto 0); + signal SH : std_logic_vector(7 downto 0); + signal SauHit : std_logic_vector(8 downto 0); + signal SHitTri : std_logic_vector(5 downto 0); + + signal TrigIH : std_logic; + signal IHDir : std_logic; + signal IHDir1 : std_logic; + signal IHCnt : std_logic_vector(8 downto 0); + signal IH : std_logic_vector(7 downto 0); + signal InHit : std_logic_vector(8 downto 0); + signal IHitTri : std_logic_vector(5 downto 0); + + signal TrigEx : std_logic; + signal Excnt : std_logic_vector(9 downto 0); + signal ExShift : std_logic_vector(15 downto 0); + signal Ex : std_logic_vector(2 downto 0); + signal Explo : std_logic; + + signal TrigMis : std_logic; + signal MisShift : std_logic_vector(15 downto 0); + signal MisCnt : std_logic_vector(8 downto 0); + signal miscnt1 : unsigned(7 downto 0); + signal Mis : std_logic_vector(2 downto 0); + signal Missile : std_logic; + + signal EnBG : std_logic; + signal BGFnum : std_logic_vector(7 downto 0); + signal BGCnum : std_logic_vector(7 downto 0); + signal bg_cnt : unsigned(7 downto 0); + signal BG : std_logic; + +begin + + -- do a crude addition of all sound samples + p_audio_mix : process + variable IHVol : std_logic_vector(6 downto 0); + variable SHVol : std_logic_vector(6 downto 0); + begin + wait until rising_edge(Clk); + + IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0); + SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0); + + tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol); + + Aud(7) <= tempsum (7); + Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor (Ex(2) and Explo) xor BG; + Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor (Ex(1) and Explo) xor SS; + Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor (Ex(0) and Explo); + Aud(3 downto 0) <= tempsum (3 downto 0); + + end process; + + p_clkdiv : process + begin + wait until rising_edge(Clk); + Clk7680_ena <= '0'; + if ClkDiv = 1277 then + Clk7680_ena <= '1'; + ClkDiv <= (others => '0'); + else + ClkDiv <= ClkDiv + 1; + end if; + end process; + + p_clkdiv2 : process + begin + wait until rising_edge(Clk); + Clk480_ena <= '0'; + Clk240_ena <= '0'; + Clk60_ena <= '0'; + + if (Clk7680_ena = '1') then + ClkDiv2 <= ClkDiv2 + 1; + + if (ClkDiv2(3 downto 0) = "0000") then + Clk480_ena <= '1'; + end if; + + if (ClkDiv2(4 downto 0) = "00000") then + Clk240_ena <= '1'; + end if; + + if (ClkDiv2(7 downto 0) = "00000000") then + Clk60_ena <= '1'; + end if; + + end if; + end process; + + p_delay : process + begin + wait until rising_edge(Clk); + s1_t1 <= S1; + s2_t1 <= S2; + end process; +--*************************Saucer Sound*************************************** + +-- Implement a VCOscilator: frequency is set using counter end point(Fnum) + p_saucer_vco : process + variable term : std_logic_vector(3 downto 0); + begin + wait until rising_edge(Clk); + term := 8 + Fnum; + if (S1(0) = '1') and (Clk7680_ena = '1') then + if vco_cnt = term then + + vco_cnt <= (others => '0'); + SS <= not SS; + else + vco_cnt <= vco_cnt + 1; + end if; + end if; + end process; + +-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator + -- this is 6Hz ?? 0123454321 + p_saucer_lfo : process + begin + wait until rising_edge(Clk); + if (Clk60_ena = '1') then + if Fnum = 4 then -- 5 -1 + Comp <= '1'; + elsif Fnum = 1 then -- 0 +1 + Comp <= '0'; + end if; + + if comp = '1' then + Fnum <= Fnum - 1 ; + else + Fnum <= Fnum + 1 ; + end if; + end if; + end process; + +--**********************SAUCER HIT Sound************************** + +-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO + p_saucer_hit_vco : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if SHitTri = 48 then + SHitTri <= "000000"; + else + SHitTri <= SHitTri+1; + end if; + end if; + end process; + +-- Implement a trianglular wave VCO for Saucer Hit 200Hz to 1kHz approx + p_saucer_hit_lfo : process + begin + wait until rising_edge(Clk); + if (Clk7680_ena = '1') then + if TriDir1 = '1' then + if (SauHit +58 - SHitTri) < 190 + 256 then + SauHit <= SauHit +58 - SHitTri; + else + SauHit <= "110111110"; + TriDir1 <= '0'; + end if; + else + if (SauHit -58 + SHitTri) > 256 then + SauHit <= SauHit -58 + SHitTri; + else + SauHit <= "100000000"; + TriDir1 <= '1'; + end if; + end if; + end if; + end process; + +-- Implement the ADSR for Saucer Hit Sound + p_saucer_adsr : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if (TrigSH = '1') then + SHCnt <= "100000000"; + SH <= "11111111"; + elsif (SHCnt(8) = '1') then + SHCnt <= SHCnt + "1"; + if SHCnt(7 downto 0) = x"60" then -- 96 + SH <= "01111111"; + elsif SHCnt(7 downto 0) = x"90" then -- 144 + SH <= "00111111"; + elsif SHCnt(7 downto 0) = x"C0" then -- 192 + SH <= "00000000"; + end if; + end if; + end if; + end process; + + -- Implement the trigger for The Saucer Hit Sound + p_saucer_hit : process + begin + wait until rising_edge(Clk); + if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge + TrigSH <= '1'; + elsif (Clk480_ena = '1') then + TrigSH <= '0'; + end if; + end process; + +--***********************Invader Hit Sound***************************** +-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO + p_invader_hit_lfo : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if IHitTri = 48-2 then + IHDir <= '0'; + elsif IHitTri =0+2 then + IHDir <= '1'; + end if; + + if IHDir ='1' then + IHitTri <= IHitTri + 2; + else + IHitTri <= IHitTri - 2; + end if; + end if; + end process; + +-- Implement a trianglular wave VCO for Invader Hit 700Hz to 3kHz approx + p_invader_hit_vco : process + begin + wait until rising_edge(Clk); + if (Clk7680_ena = '1') then + if IHDir1 = '1' then + if (InHit +10 + IHitTri) < 110 + 256 then + InHit <= InHit +10 + IHitTri; + else + InHit <= "101101110"; + IHDir1 <= '0'; + end if; + else + if (InHit -10 - IHitTri) > 256 then + InHit <= InHit -10 - IHitTri; + else + InHit <= "100000000"; + IHDir1 <= '1'; + end if; + end if; + end if; + end process; + +-- Implement the ADSR for Invader Hit Sound + p_invader_adsr : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if (TrigIH = '1') then + IHCnt <= "100000000"; + IH <= "11111111"; + elsif (IHCnt(8) = '1') then + IHCnt <= IHCnt + "1"; + if IHCnt(7 downto 0) = x"14" then -- 20 + IH <= "01111111"; + elsif IHCnt(7 downto 0) = x"1C" then -- 28 + IH <= "11111111"; + elsif IHCnt(7 downto 0) = x"30" then -- 48 + IH <= "00000000"; + end if; + end if; + end if; + end process; + + -- Implement the trigger for The Invader Hit Sound + p_invader_hit : process + begin + wait until rising_edge(Clk); + if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge + TrigIH <= '1'; + elsif (Clk480_ena = '1') then + TrigIH <= '0'; + end if; + end process; + +--***********************Explosion***************************** +-- Implement a Pseudo Random Noise Generator + p_explosion_pseudo : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if (ExShift = x"0000") then + ExShift <= "0000000010101001"; + else + ExShift(0) <= Exshift(14) xor ExShift(15); + ExShift(15 downto 1) <= ExShift (14 downto 0); + end if; + end if; + end process; + Explo <= ExShift(0); + + p_explosion_adsr : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if (TrigEx = '1') then + ExCnt <= "1000000000"; + Ex <= "100"; + elsif (ExCnt(9) = '1') then + ExCnt <= ExCnt + "1"; + if ExCnt(8 downto 0) = '0' & x"64" then -- 100 + Ex <= "010"; + elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200 + Ex <= "001"; + elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300 + Ex <= "000"; + end if; + end if; + end if; + end process; + +-- Implement the trigger for The Explosion Sound + p_explosion_trig : process + begin + wait until rising_edge(Clk); + if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge + TrigEx <= '1'; + elsif (Clk480_ena = '1') then + TrigEx <= '0'; + end if; + end process; + +--***********************Missile***************************** +-- Implement a Pseudo Random Noise Generator + p_missile_pseudo : process + begin + wait until rising_edge(Clk); + if (Clk7680_ena = '1') then + if (MisShift = x"0000") then + MisShift <= "0000000010101001"; + else + MisShift(0) <= MisShift(14) xor MisShift(15); + MisShift(15 downto 1) <= MisShift (14 downto 0); + end if; + + miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0)); + if miscnt1 > 60 then + miscnt1 <= "00000000"; + Missile <= not Missile; + end if; + + end if; + end process; + +-- Implement the ADSR for The Missile Sound + p_missile_adsr : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if (TrigMis = '1') then + MisCnt <= "100000000"; + Mis <= "100"; + elsif (MisCnt(8) = '1') then + MisCnt <= MisCnt + "1"; + if MisCnt(7 downto 0) = x"4b" then -- 75 + Mis <= "010"; + elsif MisCnt(7 downto 0) = x"70" then -- 112 + Mis <= "001"; + elsif MisCnt(7 downto 0) = x"96" then -- 150 + Mis <= "000"; + end if; + end if; + end if; + end process; + +-- Implement the trigger for The Missile Sound + p_missile_trig : process + begin + wait until rising_edge(Clk); + if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge + TrigMis <= '1'; + elsif (Clk480_ena = '1') then + TrigMis <= '0'; + end if; + end process; + +-- ******************************** Background invader moving tones ************************** + EnBG <= S2(0) or S2(1) or S2(2) or S2(3); + + with S2(3 downto 0) select + BGFnum <= x"66" when "0001", + x"74" when "0010", + x"7C" when "0100", + x"87" when "1000", + x"87" when others; + + with S2(3 downto 0) select + BGCnum <= x"33" when "0001", + x"3A" when "0010", + x"3E" when "0100", + x"43" when "1000", + x"43" when others; + +-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum) + + p_background : process + begin + wait until rising_edge(Clk); + if (Clk7680_ena = '1') then + if EnBG = '0' then + bg_cnt <= x"00"; + BG <= '0'; + else + bg_cnt <= bg_cnt + 1; + + if bg_cnt = unsigned(BGfnum) then + bg_cnt <= x"00"; + BG <= '0'; + elsif bg_cnt=unsigned(BGCnum) then + BG <='1'; + end if; + end if; + end if; + end process; + +end Behavioral; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/mw8080.vhd new file mode 100644 index 00000000..b9a88f96 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/mw8080.vhd @@ -0,0 +1,336 @@ +-- Midway 8080 main board +-- 9.984MHz Clock +-- +-- Version : 0242 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.fpgaarcade.com +-- +-- Limitations : +-- +-- File history : +-- +-- 0241 : First release +-- +-- 0242 : Removed the ROM +-- +-- 0300 : MikeJ tidyup for audio release +-- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity mw8080 is + port( + Rst_n : in std_logic; + Clk : in std_logic; + ENA : out std_logic; + RWE_n : out std_logic; + RDB : in std_logic_vector(7 downto 0); + RAB : out std_logic_vector(12 downto 0); + Sounds : out std_logic_vector(7 downto 0); + Ready : out std_logic; + GDB : in std_logic_vector(7 downto 0); + IB : in std_logic_vector(7 downto 0); + DB : out std_logic_vector(7 downto 0); + AD : out std_logic_vector(15 downto 0); + Status : out std_logic_vector(7 downto 0); + Systb : out std_logic; + Int : out std_logic; + Hold_n : in std_logic; + IntE : out std_logic; + DBin_n : out std_logic; + Vait : out std_logic; + HldA : out std_logic; + Sample : out std_logic; + Wr : out std_logic; + Video : out std_logic; + HSync : out std_logic; + VSync : out std_logic); +end mw8080; + +architecture struct of mw8080 is + + component T8080se + generic( + Mode : integer := 2; + T2Write : integer := 0); + port( + RESET_n : in std_logic; + CLK : in std_logic; + CLKEN : in std_logic; + READY : in std_logic; + HOLD : in std_logic; + INT : in std_logic; + INTE : out std_logic; + DBIN : out std_logic; + SYNC : out std_logic; + VAIT : out std_logic; + HLDA : out std_logic; + WR_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0)); + end component; + + signal Ready_i : std_logic; + signal Hold : std_logic; + signal IntTrig : std_logic; + signal IntTrigOld : std_logic; + signal Int_i : std_logic; + signal IntE_i : std_logic; + signal DBin : std_logic; + signal Sync : std_logic; + signal Wr_n, Rd_n : std_logic; + signal ClkEnCnt : unsigned(2 downto 0); + signal Status_i : std_logic_vector(7 downto 0); + signal A : std_logic_vector(15 downto 0); + signal ISel : std_logic_vector(1 downto 0); + signal DI : std_logic_vector(7 downto 0); + signal DO : std_logic_vector(7 downto 0); + signal RR : std_logic_vector(9 downto 0); + + signal VidEn : std_logic; + signal CntD5 : unsigned(3 downto 0); -- Horizontal counter / 320 + signal CntE5 : unsigned(4 downto 0); -- Horizontal counter 2 + signal CntE6 : unsigned(3 downto 0); -- Vertical counter / 262 + signal CntE7 : unsigned(4 downto 0); -- Vertical counter 2 + signal Shift : std_logic_vector(7 downto 0); + +begin + ENA <= ClkEnCnt(2); + Status <= Status_i; + Ready <= Ready_i; + DB <= DO; + Systb <= Sync; + Int <= Int_i; + Hold <= not Hold_n; + IntE <= IntE_i; + DBin_n <= not DBin; + Sample <= not Wr_n and Status_i(4); + Wr <= not Wr_n; + AD <= A; + Sounds(0) <= CntE7(3); + Sounds(1) <= CntE7(2); + Sounds(2) <= CntE7(1); + Sounds(3) <= CntE7(0); + Sounds(4) <= CntE6(3); + Sounds(5) <= CntE6(2); + Sounds(6) <= CntE6(1); + Sounds(7) <= CntE6(0); + + IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4); + + ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13)); + ISel(1) <= Status_i(0) nor Status_i(6); + + with ISel select + DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00", + GDB when "01", + IB when "10", + RR(7 downto 0) when others; + + RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2); + RAB <= A(12 downto 0) when CntD5(2) = '1' else + std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3)); + + u_8080: T8080se + generic map ( + Mode => 2, + T2Write => 1) + port map ( + RESET_n => Rst_n, + CLK => Clk, + CLKEN => ClkEnCnt(2), + READY => Ready_i, + HOLD => Hold, + INT => Int_i, + INTE => IntE_i, + DBIN => DBin, + SYNC => Sync, + VAIT => Vait, + HLDA => HLDA, + WR_n => Wr_n, + A => A, + DI => DI, + DO => DO); + + -- Clock enables + process (Rst_n, Clk) + begin + if Rst_n = '0' then + ClkEnCnt <= "000"; + VidEn <= '0'; + elsif Clk'event and Clk = '1' then + VidEn <= not VidEn; + if ClkEnCnt = 4 then + ClkEnCnt <= "000"; + else + ClkEnCnt <= ClkEnCnt + 1; + end if; + end if; + end process; + + -- Glue + process (Rst_n, Clk) + variable OldASEL : std_logic; + begin + if Rst_n = '0' then + Status_i <= (others => '0'); + IntTrigOld <= '0'; + Int_i <= '0'; + OldASEL := '0'; + Ready_i <= '0'; + RR <= (others => '0'); + elsif Clk'event and Clk = '1' then + -- E3 + -- Interrupt + IntTrigOld <= IntTrig; + if Status_i(0) = '1' then + Int_i <= '0'; + elsif IntTrigOld = '0' and IntTrig = '1' then + Int_i <= IntE_i; + end if; + + -- D7 + -- Status register + if Sync = '1' then + Status_i <= DO; + end if; + + -- A3, C3, E3 + -- RAM register/ready logic + if Sync = '1' and A(13) = '1' then + Ready_i <= '0'; + elsif Ready_i = '1' then + Ready_i <= '1'; + else + Ready_i <= RR(9); + end if; + if Sync = '1' and A(13) = '1' then + RR <= (others => '0'); + elsif (CntD5(2) = '1' and OldASEL = '0') or -- ASEL pos edge + (CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge + RR(7 downto 0) <= RDB; + RR(8) <= '1'; + RR(9) <= RR(8); + end if; + OldASEL := CntD5(2); + end if; + end process; + + -- Video counters + process (Rst_n, Clk) + begin + if Rst_n = '0' then + CntD5 <= (others => '0'); + CntE5 <= (others => '0'); + CntE6 <= (others => '0'); + CntE7 <= (others => '0'); + elsif Clk'event and Clk = '1' then + if VidEn = '1' then + CntD5 <= CntD5 + 1; + if CntD5 = 15 then + + CntE5 <= CntE5 + 1; + if CntE5(3 downto 0) = 15 then + if CntE5(4) = '0' then + CntE5 <= "11100"; + + CntE6 <= CntE6 + 1; + if CntE6 = 15 then + + CntE7 <= CntE7 + 1; + if CntE7(3 downto 0) = 15 then + if CntE7(4) = '0' then + CntE6 <= "1010"; + CntE7 <= "11101"; + else + CntE7 <= "00010"; + end if; + end if; + end if; + end if; + else + end if; + end if; + end if; + end if; + end process; + + -- Video shift register + process (Rst_n, Clk) + begin + if Rst_n = '0' then + Shift <= (others => '0'); + Video <= '0'; + elsif Clk'event and Clk = '1' then + if VidEn = '1' then + if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then + Shift(7 downto 0) <= RDB(7 downto 0); + else + Shift(6 downto 0) <= Shift(7 downto 1); + Shift(7) <= '0'; + end if; + Video <= Shift(0); + end if; + end if; + end process; + + -- Sync + process (Rst_n, Clk) + begin + if Rst_n = '0' then + HSync <= '1'; + VSync <= '1'; + elsif Clk'event and Clk = '1' then + if VidEn = '1' then + if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then + HSync <= '0'; + else + HSync <= '1'; + end if; + if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then + VSync <= '0'; + else + VSync <= '1'; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/pll.qip b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/pll.qip new file mode 100644 index 00000000..48665362 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/pll.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/pll.vhd new file mode 100644 index 00000000..feed4923 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/pll.vhd @@ -0,0 +1,382 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.4 Build 182 03/12/2014 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire5_bv(0 DOWNTO 0) <= "0"; + sub_wire5 <= To_stdlogicvector(sub_wire5_bv); + sub_wire2 <= sub_wire0(1); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + c1 <= sub_wire2; + sub_wire3 <= inclk0; + sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 27, + clk0_duty_cycle => 50, + clk0_multiply_by => 10, + clk0_phase_shift => "0", + clk1_divide_by => 9, + clk1_duty_cycle => 50, + clk1_multiply_by => 8, + clk1_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire4, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "24.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "40" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "24.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/roms/mw01.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/roms/mw01.vhd new file mode 100644 index 00000000..1e6a8db4 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/roms/mw01.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity mw01 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of mw01 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"F3",X"31",X"7C",X"02",X"C3",X"36",X"02",X"C7",X"F5",X"AF",X"32",X"05",X"20",X"C3",X"49",X"00", + X"F5",X"3E",X"80",X"C3",X"0A",X"00",X"C7",X"C7",X"F3",X"E5",X"D5",X"C5",X"F5",X"C3",X"2B",X"01", + X"F3",X"CD",X"0F",X"02",X"47",X"C3",X"D4",X"01",X"F3",X"CD",X"0F",X"02",X"47",X"C3",X"F3",X"01", + X"F3",X"CD",X"0F",X"02",X"2F",X"C3",X"FB",X"01",X"F3",X"CD",X"0F",X"02",X"79",X"C3",X"04",X"02", + X"AF",X"77",X"23",X"05",X"C2",X"41",X"00",X"C9",X"C7",X"AF",X"32",X"0B",X"20",X"22",X"26",X"20", + X"21",X"00",X"00",X"39",X"22",X"28",X"20",X"F1",X"2A",X"26",X"20",X"E5",X"2A",X"0C",X"20",X"F9", + X"2A",X"28",X"20",X"E5",X"D5",X"C5",X"F5",X"3A",X"06",X"20",X"F5",X"21",X"00",X"00",X"39",X"22", + X"0C",X"20",X"EB",X"2A",X"9E",X"02",X"EB",X"7A",X"2F",X"57",X"7B",X"2F",X"5F",X"19",X"D2",X"BA", + X"00",X"3A",X"0B",X"20",X"A7",X"C2",X"7B",X"01",X"CD",X"B6",X"02",X"21",X"07",X"20",X"7E",X"23", + X"A6",X"CA",X"05",X"01",X"47",X"23",X"4E",X"21",X"1E",X"20",X"16",X"80",X"7A",X"A0",X"CA",X"AC", + X"00",X"35",X"C2",X"AC",X"00",X"A1",X"C2",X"BA",X"00",X"7A",X"B1",X"4F",X"23",X"7A",X"2F",X"A0", + X"47",X"CA",X"BE",X"00",X"7A",X"1F",X"57",X"C3",X"9D",X"00",X"2A",X"A2",X"02",X"E9",X"21",X"09", + X"20",X"71",X"7E",X"2F",X"2B",X"A6",X"77",X"2A",X"0C",X"20",X"F9",X"0E",X"80",X"3A",X"09",X"20", + X"47",X"3A",X"0A",X"20",X"2F",X"A0",X"5F",X"3A",X"07",X"20",X"A3",X"CA",X"05",X"01",X"11",X"0E", + X"20",X"78",X"A1",X"C2",X"EE",X"00",X"79",X"1F",X"4F",X"13",X"13",X"C3",X"E1",X"00",X"2F",X"A0", + X"32",X"09",X"20",X"79",X"32",X"06",X"20",X"1A",X"6F",X"13",X"1A",X"67",X"F9",X"F1",X"C1",X"D1", + X"E1",X"D3",X"06",X"FB",X"C9",X"F3",X"2A",X"0C",X"20",X"F9",X"01",X"0A",X"00",X"09",X"22",X"0C", + X"20",X"F1",X"A7",X"CA",X"1E",X"01",X"47",X"3A",X"07",X"20",X"A0",X"CA",X"05",X"01",X"32",X"06", + X"20",X"F1",X"C1",X"D1",X"E1",X"F9",X"E1",X"D3",X"06",X"FB",X"C9",X"21",X"06",X"20",X"7E",X"47", + X"23",X"A6",X"CA",X"05",X"01",X"23",X"B6",X"77",X"21",X"1E",X"20",X"11",X"0E",X"20",X"78",X"17", + X"DA",X"49",X"01",X"23",X"13",X"13",X"C3",X"3F",X"01",X"44",X"4D",X"21",X"00",X"00",X"39",X"7D", + X"12",X"13",X"7C",X"12",X"11",X"08",X"00",X"19",X"F9",X"E3",X"7E",X"23",X"E3",X"02",X"C3",X"C7", + X"00",X"F3",X"A7",X"CA",X"70",X"01",X"C5",X"47",X"3A",X"07",X"20",X"A0",X"CA",X"72",X"01",X"C1", + X"FB",X"C9",X"78",X"C1",X"F5",X"32",X"0B",X"20",X"C3",X"4D",X"00",X"47",X"21",X"06",X"20",X"77", + X"23",X"B6",X"77",X"31",X"7C",X"02",X"78",X"33",X"33",X"33",X"33",X"17",X"D2",X"87",X"01",X"D1", + X"E1",X"F9",X"EB",X"FB",X"E9",X"F3",X"F5",X"A7",X"C4",X"9E",X"01",X"F1",X"FB",X"C9",X"C5",X"E5", + X"2F",X"47",X"0E",X"03",X"21",X"07",X"20",X"7E",X"A0",X"77",X"23",X"0D",X"C2",X"A7",X"01",X"36", + X"00",X"21",X"2A",X"20",X"78",X"2F",X"23",X"17",X"D2",X"B6",X"01",X"36",X"00",X"E1",X"C1",X"C9", + X"F3",X"3A",X"06",X"20",X"CD",X"9E",X"01",X"C3",X"C7",X"00",X"F1",X"C1",X"D1",X"E1",X"3A",X"00", + X"20",X"FB",X"A7",X"C9",X"CD",X"27",X"02",X"70",X"3E",X"D3",X"32",X"01",X"20",X"EB",X"3E",X"C9", + X"32",X"03",X"20",X"21",X"CC",X"4F",X"CD",X"2A",X"02",X"32",X"02",X"20",X"1A",X"CD",X"01",X"20", + X"C3",X"CA",X"01",X"CD",X"27",X"02",X"B0",X"77",X"C3",X"D8",X"01",X"47",X"CD",X"27",X"02",X"A0", + X"77",X"C3",X"D8",X"01",X"2F",X"4F",X"CD",X"27",X"02",X"B0",X"A1",X"77",X"C3",X"D8",X"01",X"32", + X"00",X"20",X"E3",X"33",X"33",X"EB",X"E3",X"7E",X"23",X"E3",X"3B",X"3B",X"E5",X"C5",X"32",X"04", + X"20",X"3A",X"00",X"20",X"F5",X"D5",X"C9",X"21",X"2A",X"20",X"3A",X"04",X"20",X"85",X"6F",X"7C", + X"CE",X"00",X"67",X"7E",X"A7",X"C9",X"D1",X"E1",X"F9",X"EB",X"CD",X"3E",X"02",X"E9",X"F3",X"F5", + X"C5",X"E5",X"AF",X"06",X"2D",X"21",X"06",X"20",X"CD",X"41",X"00",X"21",X"00",X"24",X"22",X"0C", + X"20",X"E1",X"C1",X"F1",X"D3",X"06",X"FB",X"C9",X"F3",X"F5",X"C5",X"E5",X"21",X"00",X"00",X"06", + X"00",X"7E",X"80",X"47",X"23",X"7C",X"FE",X"20",X"C2",X"61",X"02",X"78",X"C6",X"1B",X"C2",X"78", + X"02",X"E1",X"C1",X"F1",X"D3",X"06",X"FB",X"C9",X"2A",X"A0",X"02",X"E9",X"EE",X"02",X"8D",X"21", + X"8E",X"07",X"AD",X"21",X"A3",X"0A",X"C3",X"21",X"30",X"0D",X"DF",X"21",X"B1",X"11",X"F7",X"21", + X"5B",X"13",X"0D",X"22",X"C3",X"13",X"23",X"22",X"A4",X"02",X"24",X"22",X"A7",X"02",X"25",X"22", + X"AE",X"02",X"B2",X"02",X"C3",X"AA",X"02",X"C3",X"AA",X"02",X"F3",X"C3",X"AA",X"02",X"F3",X"C3", + X"AE",X"02",X"F3",X"C3",X"B2",X"02",X"2A",X"59",X"20",X"2B",X"22",X"59",X"20",X"DB",X"01",X"0F", + X"DA",X"C8",X"02",X"AF",X"32",X"47",X"20",X"C9",X"3A",X"46",X"20",X"FE",X"09",X"D0",X"3A",X"47", + X"20",X"A7",X"C0",X"3E",X"01",X"32",X"47",X"20",X"DB",X"02",X"07",X"3A",X"46",X"20",X"D2",X"E3", + X"02",X"C6",X"01",X"C6",X"01",X"27",X"E6",X"0F",X"32",X"46",X"20",X"D3",X"06",X"C9",X"CD",X"A4", + X"04",X"CD",X"16",X"07",X"21",X"26",X"22",X"11",X"B6",X"23",X"CD",X"24",X"07",X"21",X"39",X"20", + X"11",X"6E",X"21",X"CD",X"24",X"07",X"CD",X"16",X"07",X"3E",X"01",X"32",X"58",X"20",X"CD",X"A4", + X"04",X"CD",X"6F",X"03",X"3E",X"04",X"CD",X"61",X"01",X"CD",X"0A",X"06",X"3A",X"46",X"20",X"A7", + X"C2",X"78",X"03",X"3A",X"58",X"20",X"0F",X"DA",X"1C",X"03",X"CD",X"6F",X"03",X"CD",X"EC",X"06", + X"CD",X"0A",X"06",X"3E",X"01",X"32",X"30",X"20",X"3A",X"30",X"20",X"A7",X"C2",X"38",X"03",X"3E", + X"20",X"CD",X"61",X"01",X"3A",X"46",X"20",X"A7",X"C2",X"78",X"03",X"CD",X"0A",X"06",X"3A",X"2E", + X"20",X"A7",X"CA",X"5F",X"03",X"3E",X"80",X"CD",X"95",X"01",X"3E",X"80",X"CD",X"61",X"01",X"3A", + X"58",X"20",X"0F",X"D2",X"44",X"03",X"CD",X"3E",X"02",X"CD",X"16",X"07",X"C3",X"11",X"03",X"CD", + X"B2",X"05",X"CD",X"1E",X"05",X"C3",X"DC",X"05",X"CD",X"3E",X"02",X"CD",X"16",X"07",X"AF",X"32", + X"58",X"20",X"32",X"48",X"20",X"CD",X"A4",X"04",X"3E",X"04",X"CD",X"61",X"01",X"CD",X"DC",X"05", + X"CD",X"0A",X"06",X"DB",X"01",X"E6",X"06",X"CA",X"90",X"03",X"EE",X"04",X"CA",X"AE",X"04",X"EE", + X"06",X"C2",X"90",X"03",X"3A",X"46",X"20",X"3D",X"CA",X"90",X"03",X"3D",X"32",X"46",X"20",X"3E", + X"81",X"32",X"48",X"20",X"CD",X"A4",X"05",X"CD",X"1E",X"05",X"AF",X"32",X"40",X"20",X"CD",X"75", + X"07",X"CD",X"EC",X"06",X"3E",X"20",X"CD",X"61",X"01",X"3E",X"08",X"32",X"40",X"20",X"CD",X"0A", + X"06",X"3A",X"2E",X"20",X"A7",X"CA",X"E9",X"03",X"3E",X"80",X"CD",X"95",X"01",X"3E",X"80",X"CD", + X"61",X"01",X"3A",X"2E",X"20",X"A7",X"C2",X"E2",X"03",X"3A",X"2A",X"20",X"0F",X"D2",X"CE",X"03", + X"0F",X"DA",X"48",X"04",X"CD",X"EE",X"1F",X"CD",X"3E",X"02",X"3A",X"48",X"20",X"3C",X"E6",X"81", + X"32",X"48",X"20",X"3A",X"57",X"20",X"A7",X"3E",X"01",X"32",X"57",X"20",X"CA",X"B7",X"03",X"CD", + X"1E",X"05",X"3A",X"3C",X"20",X"A7",X"FA",X"F7",X"03",X"3A",X"29",X"22",X"47",X"3A",X"31",X"22", + X"B0",X"F4",X"75",X"07",X"3E",X"08",X"CD",X"61",X"01",X"CD",X"DC",X"05",X"3E",X"40",X"CD",X"61", + X"01",X"3E",X"01",X"32",X"2D",X"20",X"3E",X"20",X"CD",X"61",X"01",X"3E",X"80",X"CD",X"61",X"01", + X"3E",X"10",X"CD",X"61",X"01",X"C3",X"CE",X"03",X"3A",X"2A",X"20",X"A7",X"F5",X"CD",X"3E",X"02", + X"AF",X"E7",X"09",X"E7",X"0A",X"E7",X"0B",X"3E",X"1F",X"F7",X"0C",X"CD",X"4A",X"07",X"CD",X"0A", + X"06",X"F1",X"F2",X"6B",X"04",X"21",X"DA",X"4F",X"CD",X"F4",X"14",X"21",X"E2",X"1C",X"3A",X"48", + X"20",X"0F",X"DA",X"78",X"04",X"21",X"F9",X"1C",X"CD",X"F4",X"14",X"CD",X"01",X"07",X"3A",X"48", + X"20",X"A7",X"F2",X"93",X"04",X"3A",X"29",X"22",X"A7",X"F2",X"FA",X"03",X"3A",X"31",X"22",X"A7", + X"F2",X"FA",X"03",X"AF",X"32",X"48",X"20",X"CD",X"F6",X"04",X"3A",X"46",X"20",X"A7",X"CA",X"06", + X"03",X"C3",X"78",X"03",X"AF",X"E7",X"09",X"E7",X"0A",X"E7",X"0B",X"E7",X"0C",X"C9",X"3E",X"01", + X"32",X"48",X"20",X"21",X"46",X"20",X"35",X"CD",X"A4",X"05",X"CD",X"1E",X"05",X"AF",X"32",X"40", + X"20",X"CD",X"75",X"07",X"CD",X"EC",X"06",X"3E",X"20",X"CD",X"61",X"01",X"3E",X"08",X"32",X"40", + X"20",X"CD",X"0A",X"06",X"3A",X"2E",X"20",X"A7",X"CA",X"EC",X"04",X"3E",X"80",X"CD",X"95",X"01", + X"3E",X"80",X"CD",X"61",X"01",X"3A",X"2E",X"20",X"A7",X"C2",X"E5",X"04",X"3A",X"2A",X"20",X"0F", + X"D2",X"D1",X"04",X"C3",X"48",X"04",X"2A",X"26",X"22",X"EB",X"2A",X"2E",X"22",X"7C",X"BA",X"DA", + X"0B",X"05",X"C2",X"0A",X"05",X"7D",X"BB",X"DA",X"0B",X"05",X"EB",X"2A",X"43",X"20",X"7A",X"BC", + X"D8",X"C2",X"17",X"05",X"7B",X"BD",X"D8",X"EB",X"22",X"43",X"20",X"C3",X"0A",X"06",X"3A",X"48", + X"20",X"0F",X"21",X"39",X"20",X"11",X"26",X"22",X"06",X"08",X"DA",X"30",X"05",X"11",X"2E",X"22", + X"CD",X"34",X"16",X"21",X"68",X"20",X"11",X"36",X"22",X"06",X"D8",X"3A",X"48",X"20",X"0F",X"DA", + X"45",X"05",X"11",X"F6",X"22",X"CD",X"34",X"16",X"CD",X"16",X"07",X"3A",X"48",X"20",X"A7",X"C8", + X"3E",X"20",X"E7",X"0A",X"3A",X"48",X"20",X"0F",X"3E",X"20",X"D2",X"5E",X"05",X"AF",X"E7",X"0C", + X"06",X"10",X"CD",X"D3",X"07",X"7E",X"FE",X"38",X"C2",X"70",X"05",X"3E",X"01",X"EF",X"0A",X"C9", + X"7E",X"FE",X"33",X"C2",X"7B",X"05",X"3E",X"01",X"C3",X"DA",X"07",X"7E",X"FE",X"70",X"C2",X"86", + X"05",X"3E",X"10",X"EF",X"0C",X"C9",X"7E",X"FE",X"50",X"C2",X"95",X"05",X"3E",X"01",X"EF",X"0A", + X"3E",X"1F",X"C3",X"DA",X"07",X"7E",X"FE",X"3F",X"CA",X"90",X"05",X"23",X"23",X"23",X"23",X"05", + X"C2",X"65",X"05",X"C9",X"3E",X"04",X"CD",X"95",X"01",X"21",X"26",X"22",X"11",X"B6",X"23",X"CD", + X"24",X"07",X"DB",X"02",X"E6",X"03",X"87",X"21",X"D4",X"05",X"CD",X"2D",X"02",X"5F",X"23",X"56", + X"EB",X"22",X"28",X"22",X"22",X"30",X"22",X"3E",X"01",X"32",X"2D",X"22",X"32",X"35",X"22",X"AF", + X"32",X"57",X"20",X"C9",X"DC",X"05",X"D0",X"07",X"C4",X"09",X"AC",X"0D",X"21",X"34",X"1D",X"CD", + X"F4",X"14",X"21",X"5D",X"1D",X"CD",X"F4",X"14",X"21",X"68",X"1D",X"CD",X"F4",X"14",X"2A",X"43", + X"20",X"11",X"1D",X"30",X"CD",X"BE",X"06",X"2A",X"26",X"22",X"11",X"1D",X"27",X"CD",X"BE",X"06", + X"2A",X"2E",X"22",X"11",X"1D",X"39",X"CD",X"BE",X"06",X"C9",X"3A",X"46",X"20",X"21",X"01",X"3D", + X"CD",X"D9",X"06",X"CD",X"7B",X"06",X"60",X"69",X"11",X"01",X"2C",X"CD",X"BE",X"06",X"3A",X"59", + X"20",X"A7",X"CA",X"70",X"06",X"F3",X"2A",X"41",X"20",X"7C",X"B5",X"CA",X"59",X"06",X"EB",X"21", + X"00",X"00",X"22",X"41",X"20",X"2A",X"39",X"20",X"FB",X"7D",X"83",X"27",X"6F",X"7C",X"8A",X"27", + X"67",X"22",X"39",X"20",X"7B",X"21",X"1C",X"33",X"CD",X"D0",X"06",X"CD",X"C9",X"06",X"3E",X"40", + X"32",X"59",X"20",X"21",X"53",X"1D",X"CD",X"F4",X"14",X"FB",X"3A",X"48",X"20",X"A7",X"C8",X"2A", + X"39",X"20",X"0F",X"11",X"1D",X"27",X"DA",X"6C",X"06",X"11",X"1D",X"39",X"CD",X"BE",X"06",X"C9", + X"2A",X"53",X"1D",X"06",X"48",X"CD",X"E1",X"06",X"C3",X"59",X"06",X"2A",X"3B",X"20",X"11",X"A2", + X"06",X"01",X"00",X"00",X"7C",X"A7",X"F8",X"29",X"29",X"29",X"DA",X"95",X"06",X"7C",X"B5",X"C8", + X"13",X"13",X"C3",X"89",X"06",X"1A",X"81",X"27",X"4F",X"13",X"1A",X"88",X"27",X"47",X"13",X"C3", + X"89",X"06",X"92",X"81",X"96",X"40",X"48",X"20",X"24",X"10",X"12",X"05",X"56",X"02",X"28",X"01", + X"64",X"00",X"32",X"00",X"16",X"00",X"08",X"00",X"04",X"00",X"02",X"00",X"01",X"00",X"EB",X"D5", + X"7A",X"CD",X"D0",X"06",X"D1",X"7B",X"CD",X"D0",X"06",X"06",X"00",X"0E",X"08",X"C3",X"3D",X"16", + X"F5",X"0F",X"0F",X"0F",X"0F",X"CD",X"D9",X"06",X"F1",X"E6",X"0F",X"47",X"0E",X"08",X"C3",X"3D", + X"16",X"AF",X"11",X"20",X"00",X"77",X"19",X"05",X"C2",X"E5",X"06",X"C9",X"3E",X"80",X"CD",X"61", + X"01",X"3E",X"40",X"CD",X"61",X"01",X"3E",X"10",X"CD",X"61",X"01",X"3E",X"08",X"CD",X"61",X"01", + X"C9",X"21",X"F4",X"01",X"22",X"59",X"20",X"CD",X"DF",X"07",X"A7",X"F2",X"07",X"07",X"CD",X"E7", + X"07",X"06",X"68",X"C3",X"E1",X"06",X"21",X"00",X"24",X"06",X"00",X"70",X"23",X"7C",X"FE",X"40", + X"DA",X"19",X"07",X"C9",X"06",X"00",X"70",X"23",X"7C",X"BA",X"C2",X"26",X"07",X"7D",X"BB",X"C2", + X"26",X"07",X"C9",X"21",X"62",X"09",X"06",X"1A",X"36",X"00",X"23",X"05",X"C2",X"38",X"07",X"01", + X"06",X"00",X"09",X"7C",X"FE",X"40",X"DA",X"36",X"07",X"C9",X"3A",X"48",X"20",X"0F",X"11",X"39", + X"20",X"21",X"26",X"22",X"06",X"08",X"DA",X"5C",X"07",X"21",X"2E",X"22",X"CD",X"34",X"16",X"21", + X"36",X"22",X"11",X"68",X"20",X"06",X"C0",X"3A",X"48",X"20",X"0F",X"DA",X"71",X"07",X"21",X"F6", + X"22",X"CD",X"34",X"16",X"C9",X"CD",X"DC",X"05",X"CD",X"0A",X"06",X"3A",X"48",X"20",X"0F",X"21", + X"10",X"1D",X"DA",X"88",X"07",X"21",X"22",X"1D",X"CD",X"F4",X"14",X"C3",X"01",X"07",X"3A",X"2E", + X"20",X"E6",X"01",X"C2",X"89",X"09",X"21",X"18",X"8A",X"22",X"49",X"20",X"AF",X"32",X"4F",X"20", + X"21",X"8F",X"1B",X"22",X"4D",X"20",X"21",X"02",X"0F",X"22",X"4B",X"20",X"CD",X"1C",X"0A",X"DF", + X"01",X"2A",X"49",X"20",X"7C",X"C6",X"F8",X"67",X"3A",X"05",X"20",X"AC",X"47",X"3A",X"48",X"20", + X"FE",X"80",X"78",X"07",X"CA",X"CD",X"07",X"D2",X"AF",X"07",X"C3",X"D0",X"07",X"DA",X"AF",X"07", + X"C3",X"EF",X"07",X"CD",X"4F",X"0D",X"21",X"E8",X"20",X"C9",X"E7",X"0B",X"F7",X"0A",X"C9",X"3E", + X"00",X"D3",X"03",X"3A",X"5A",X"20",X"C9",X"3E",X"20",X"EF",X"0A",X"2A",X"10",X"1D",X"C9",X"21", + X"3D",X"20",X"34",X"CD",X"50",X"0A",X"3A",X"3C",X"20",X"A7",X"FA",X"84",X"09",X"3A",X"51",X"20"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/roms/mw02.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/roms/mw02.vhd new file mode 100644 index 00000000..ef4b42fa --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/roms/mw02.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity mw02 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of mw02 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"3D",X"32",X"51",X"20",X"F2",X"18",X"08",X"E6",X"0F",X"32",X"51",X"20",X"F3",X"2A",X"3B",X"20", + X"2B",X"22",X"3B",X"20",X"FB",X"C3",X"18",X"08",X"CD",X"79",X"0A",X"E6",X"F0",X"CA",X"4E",X"08", + X"21",X"51",X"20",X"35",X"EE",X"10",X"CA",X"2E",X"08",X"EE",X"30",X"CA",X"3E",X"08",X"2A",X"49", + X"20",X"7C",X"FE",X"28",X"DA",X"4E",X"08",X"25",X"22",X"49",X"20",X"C3",X"4E",X"08",X"2A",X"49", + X"20",X"7C",X"FE",X"E0",X"D2",X"4E",X"08",X"24",X"22",X"49",X"20",X"C3",X"4E",X"08",X"AF",X"32", + X"4F",X"20",X"CD",X"1C",X"0A",X"DF",X"01",X"3A",X"52",X"20",X"A7",X"CA",X"AF",X"07",X"01",X"00", + X"10",X"21",X"E8",X"20",X"7E",X"A7",X"CA",X"6C",X"08",X"F2",X"78",X"08",X"23",X"23",X"23",X"23", + X"0C",X"05",X"C2",X"64",X"08",X"C3",X"AF",X"07",X"E5",X"C5",X"57",X"79",X"21",X"68",X"20",X"87", + X"87",X"87",X"CD",X"2D",X"02",X"7E",X"FE",X"28",X"D2",X"A1",X"08",X"23",X"5E",X"3A",X"4A",X"20", + X"C6",X"02",X"47",X"C6",X"0A",X"BB",X"DA",X"A1",X"08",X"23",X"23",X"7B",X"86",X"B8",X"D2",X"A6", + X"08",X"C1",X"E1",X"C3",X"6C",X"08",X"7A",X"FE",X"40",X"CA",X"98",X"09",X"E6",X"F0",X"87",X"B1", + X"3C",X"32",X"2C",X"20",X"3E",X"3F",X"32",X"0A",X"20",X"7A",X"FE",X"40",X"C1",X"E1",X"36",X"00", + X"11",X"24",X"FA",X"FA",X"D1",X"08",X"FE",X"70",X"11",X"E0",X"FC",X"DA",X"D1",X"08",X"11",X"30", + X"F8",X"2A",X"3B",X"20",X"19",X"7C",X"A7",X"FA",X"4A",X"09",X"3E",X"04",X"EF",X"0A",X"3E",X"20", + X"EF",X"0B",X"DF",X"03",X"AF",X"32",X"66",X"20",X"D5",X"CD",X"50",X"0A",X"2A",X"49",X"20",X"3A", + X"51",X"20",X"3D",X"32",X"51",X"20",X"0F",X"DA",X"FF",X"08",X"25",X"25",X"C3",X"01",X"09",X"24", + X"24",X"22",X"49",X"20",X"CD",X"1C",X"0A",X"D1",X"2A",X"3B",X"20",X"2B",X"2B",X"2B",X"2B",X"2B", + X"2B",X"00",X"00",X"22",X"3B",X"20",X"13",X"13",X"13",X"13",X"13",X"13",X"00",X"00",X"7A",X"A7", + X"FA",X"E2",X"08",X"06",X"01",X"3E",X"04",X"F7",X"0A",X"3E",X"20",X"F7",X"0B",X"3E",X"01",X"32", + X"30",X"20",X"AF",X"32",X"0A",X"20",X"78",X"E6",X"02",X"C2",X"43",X"09",X"3A",X"48",X"20",X"A7", + X"F2",X"AF",X"07",X"78",X"32",X"2A",X"20",X"CD",X"C0",X"01",X"22",X"3B",X"20",X"3E",X"04",X"EF", + X"0A",X"3E",X"20",X"EF",X"0B",X"2A",X"49",X"20",X"11",X"FE",X"FD",X"19",X"22",X"49",X"20",X"21", + X"05",X"17",X"22",X"4B",X"20",X"21",X"54",X"1C",X"22",X"4D",X"20",X"CD",X"1C",X"0A",X"3E",X"64", + X"32",X"51",X"20",X"21",X"51",X"20",X"35",X"CA",X"7F",X"09",X"DF",X"01",X"C3",X"73",X"09",X"06", + X"03",X"C3",X"25",X"09",X"06",X"83",X"C3",X"25",X"09",X"3E",X"7F",X"32",X"0A",X"20",X"AF",X"32", + X"2E",X"20",X"11",X"18",X"FC",X"C3",X"D1",X"08",X"C1",X"E1",X"CD",X"FC",X"09",X"DF",X"01",X"CD", + X"50",X"0A",X"21",X"18",X"8A",X"22",X"49",X"20",X"CD",X"1C",X"0A",X"DF",X"01",X"3E",X"02",X"32", + X"2D",X"20",X"3E",X"10",X"EF",X"0A",X"11",X"DC",X"05",X"DB",X"02",X"E6",X"08",X"CA",X"C3",X"09", + X"11",X"E8",X"03",X"2A",X"3B",X"20",X"23",X"23",X"23",X"23",X"23",X"23",X"22",X"3B",X"20",X"E5", + X"D5",X"CD",X"1C",X"0A",X"D1",X"E1",X"DF",X"02",X"1B",X"1B",X"1B",X"1B",X"1B",X"1B",X"7A",X"A7", + X"F2",X"C3",X"09",X"3E",X"10",X"F7",X"0A",X"3E",X"80",X"32",X"2D",X"20",X"3C",X"32",X"30",X"20", + X"DF",X"01",X"3A",X"2D",X"20",X"A7",X"C2",X"F0",X"09",X"C3",X"AF",X"07",X"21",X"8F",X"19",X"11", + X"AD",X"1B",X"3A",X"FC",X"1F",X"86",X"23",X"47",X"7D",X"AB",X"C2",X"12",X"0A",X"7C",X"AA",X"CA", + X"16",X"0A",X"78",X"C3",X"05",X"0A",X"78",X"A7",X"C8",X"C3",X"30",X"0A",X"2A",X"49",X"20",X"CD", + X"70",X"15",X"EB",X"2A",X"4B",X"20",X"E5",X"2A",X"4D",X"20",X"C1",X"EB",X"AF",X"32",X"52",X"20", + X"E5",X"C5",X"1A",X"A6",X"CA",X"3A",X"0A",X"32",X"52",X"20",X"1A",X"B6",X"77",X"13",X"23",X"0D", + X"C2",X"32",X"0A",X"C1",X"05",X"E1",X"C8",X"D5",X"11",X"20",X"00",X"19",X"D1",X"C3",X"30",X"0A", + X"2A",X"49",X"20",X"CD",X"70",X"15",X"EB",X"2A",X"4B",X"20",X"E5",X"2A",X"4D",X"20",X"C1",X"EB", + X"E5",X"C5",X"00",X"1A",X"AE",X"77",X"23",X"13",X"0D",X"C2",X"62",X"0A",X"C1",X"E1",X"05",X"C8", + X"D5",X"11",X"20",X"00",X"19",X"D1",X"C3",X"60",X"0A",X"3A",X"48",X"20",X"A7",X"CA",X"9A",X"0A", + X"F2",X"91",X"0A",X"0F",X"DA",X"91",X"0A",X"DB",X"00",X"07",X"07",X"47",X"DB",X"02",X"C3",X"96", + X"0A",X"DB",X"00",X"47",X"DB",X"01",X"0F",X"E6",X"38",X"C9",X"3A",X"5B",X"20",X"C6",X"10",X"07", + X"E6",X"38",X"C9",X"AF",X"32",X"5C",X"20",X"32",X"64",X"20",X"3E",X"64",X"32",X"66",X"20",X"3E", + X"20",X"32",X"65",X"20",X"3E",X"01",X"32",X"5F",X"20",X"3A",X"2C",X"20",X"A7",X"C2",X"8D",X"0C", + X"3A",X"E8",X"20",X"FE",X"40",X"CA",X"9F",X"0C",X"3E",X"0F",X"F7",X"0C",X"3A",X"58",X"20",X"A7", + X"CA",X"FA",X"0A",X"21",X"66",X"20",X"35",X"C2",X"DF",X"0A",X"36",X"64",X"C3",X"14",X"0B",X"CD", + X"DC",X"0C",X"DF",X"01",X"C3",X"B9",X"0A",X"CD",X"79",X"0A",X"E6",X"08",X"C2",X"3E",X"0B",X"3A", + X"5C",X"20",X"E6",X"01",X"32",X"5C",X"20",X"C3",X"3E",X"0B",X"CD",X"79",X"0A",X"E6",X"08",X"C2", + X"0D",X"0B",X"3A",X"5C",X"20",X"E6",X"01",X"32",X"5C",X"20",X"C3",X"DF",X"0A",X"3A",X"5C",X"20", + X"A7",X"C2",X"DF",X"0A",X"3A",X"0A",X"20",X"E6",X"FF",X"C2",X"DF",X"0A",X"3E",X"03",X"32",X"5C", + X"20",X"3E",X"02",X"EF",X"0A",X"3E",X"08",X"32",X"67",X"20",X"F3",X"2A",X"3B",X"20",X"2B",X"2B", + X"22",X"3B",X"20",X"FB",X"2A",X"49",X"20",X"11",X"10",X"07",X"19",X"C3",X"66",X"0B",X"CD",X"DC", + X"0C",X"DF",X"01",X"11",X"05",X"0D",X"06",X"01",X"2A",X"5D",X"20",X"CD",X"DD",X"15",X"21",X"67", + X"20",X"35",X"C2",X"59",X"0B",X"3E",X"02",X"F7",X"0A",X"2A",X"5D",X"20",X"2C",X"2C",X"2C",X"2C", + X"7D",X"FE",X"D8",X"D2",X"D7",X"0B",X"22",X"5D",X"20",X"11",X"05",X"0D",X"06",X"01",X"CD",X"A0", + X"15",X"DF",X"01",X"79",X"A7",X"CA",X"E7",X"0A",X"01",X"00",X"10",X"21",X"E8",X"20",X"7E",X"A7", + X"CA",X"86",X"0B",X"F2",X"94",X"0B",X"23",X"23",X"23",X"23",X"0C",X"05",X"C2",X"7E",X"0B",X"DF", + X"01",X"C3",X"E7",X"0A",X"FE",X"40",X"CA",X"E7",X"0A",X"E5",X"C5",X"57",X"79",X"21",X"68",X"20", + X"87",X"87",X"87",X"CD",X"2D",X"02",X"D5",X"EB",X"2A",X"5D",X"20",X"EB",X"1C",X"1C",X"1C",X"7B", + X"4E",X"B9",X"DA",X"D1",X"0B",X"23",X"7A",X"46",X"B8",X"DA",X"D1",X"0B",X"23",X"23",X"23",X"7E", + X"87",X"87",X"87",X"81",X"BB",X"DA",X"D1",X"0B",X"23",X"7E",X"E6",X"1F",X"80",X"BA",X"D2",X"E2", + X"0B",X"D1",X"C1",X"E1",X"C3",X"86",X"0B",X"3A",X"5C",X"20",X"E6",X"FE",X"32",X"5C",X"20",X"C3", + X"E2",X"0A",X"D1",X"C1",X"E1",X"7A",X"FE",X"40",X"06",X"00",X"D2",X"F8",X"0B",X"3A",X"3D",X"20", + X"E6",X"07",X"47",X"3A",X"3F",X"20",X"80",X"47",X"7A",X"0F",X"0F",X"0F",X"0F",X"E6",X"0F",X"57", + X"59",X"21",X"08",X"0D",X"CD",X"2D",X"02",X"80",X"4F",X"06",X"00",X"2A",X"41",X"20",X"09",X"22", + X"41",X"20",X"3A",X"64",X"20",X"A7",X"CA",X"26",X"0C",X"D5",X"2A",X"63",X"20",X"44",X"4D",X"2A", + X"5F",X"20",X"CD",X"7F",X"15",X"D1",X"7B",X"21",X"E8",X"20",X"87",X"87",X"CD",X"2D",X"02",X"36", + X"00",X"7A",X"FE",X"04",X"D2",X"81",X"0C",X"3E",X"08",X"EF",X"0A",X"7B",X"87",X"87",X"87",X"21", + X"68",X"20",X"CD",X"2D",X"02",X"D6",X"02",X"4F",X"23",X"7E",X"D6",X"02",X"47",X"C5",X"7A",X"87", + X"87",X"21",X"10",X"0D",X"CD",X"2D",X"02",X"5F",X"23",X"56",X"23",X"4E",X"23",X"46",X"21",X"64", + X"20",X"70",X"2B",X"71",X"2B",X"72",X"2B",X"73",X"E1",X"22",X"5F",X"20",X"3A",X"5C",X"20",X"E6", + X"FE",X"32",X"5C",X"20",X"DF",X"01",X"CD",X"25",X"15",X"3E",X"32",X"32",X"65",X"20",X"C3",X"E2", + X"0A",X"FE",X"05",X"C2",X"3B",X"0C",X"3E",X"17",X"E7",X"0B",X"C3",X"3B",X"0C",X"3D",X"57",X"E6", + X"1F",X"4F",X"7A",X"1F",X"57",X"AF",X"32",X"2C",X"20",X"32",X"66",X"20",X"C3",X"E5",X"0B",X"21", + X"65",X"20",X"35",X"F2",X"D0",X"0C",X"36",X"20",X"3A",X"64",X"20",X"3C",X"FE",X"04",X"C2",X"B3", + X"0C",X"3E",X"00",X"32",X"64",X"20",X"3E",X"0F",X"F7",X"0C",X"3A",X"2D",X"20",X"E6",X"02",X"C2", + X"D0",X"0C",X"21",X"D8",X"0C",X"3A",X"64",X"20",X"3D",X"E6",X"03",X"CD",X"2D",X"02",X"EF",X"0C", + X"CD",X"DC",X"0C",X"DF",X"01",X"C3",X"B9",X"0A",X"01",X"04",X"02",X"08",X"3A",X"64",X"20",X"A7", + X"C8",X"21",X"65",X"20",X"35",X"C0",X"2B",X"46",X"36",X"00",X"2B",X"4E",X"2B",X"2B",X"2B",X"7E", + X"2B",X"6E",X"67",X"CD",X"7F",X"15",X"3E",X"08",X"F7",X"0A",X"3A",X"35",X"20",X"FE",X"17",X"C0", + X"3E",X"1F",X"E7",X"0B",X"C9",X"0F",X"00",X"00",X"10",X"20",X"30",X"40",X"05",X"06",X"00",X"80", + X"19",X"1C",X"02",X"13",X"19",X"1C",X"02",X"13",X"19",X"1C",X"02",X"13",X"19",X"1C",X"02",X"13", + X"3F",X"1C",X"01",X"0C",X"3F",X"1C",X"01",X"0C",X"4A",X"1C",X"02",X"07",X"02",X"4F",X"05",X"28", + X"21",X"2D",X"20",X"7E",X"A7",X"36",X"00",X"C2",X"5C",X"0E",X"3A",X"48",X"20",X"A7",X"C4",X"37", + X"0F",X"21",X"E8",X"20",X"06",X"40",X"CD",X"40",X"00",X"CD",X"4F",X"0D",X"C3",X"66",X"0D",X"3E", + X"DF",X"F7",X"0A",X"F7",X"0B",X"F7",X"0C",X"3A",X"40",X"20",X"E6",X"07",X"C8",X"FE",X"06",X"F0", + X"3E",X"15",X"C3",X"DA",X"0F",X"0A",X"DF",X"01",X"3A",X"40",X"20",X"87",X"87",X"21",X"7F",X"0D", + X"CD",X"2D",X"02",X"5F",X"23",X"56",X"23",X"7E",X"23",X"66",X"6F",X"E9",X"06",X"06",X"08",X"49", + X"0D",X"49",X"0D",X"03",X"0F",X"58",X"0E",X"19",X"0F",X"58",X"0E",X"20",X"0F",X"58",X"0E",X"0C", + X"0F",X"58",X"0E",X"30",X"0F",X"58",X"0E",X"FA",X"0E",X"58",X"0E",X"FD",X"0E",X"58",X"0E",X"00", + X"0F",X"6C",X"0E",X"CF",X"0E",X"58",X"0E",X"D8",X"0E",X"58",X"0E",X"DF",X"0E",X"58",X"0E",X"EA", + X"0E",X"58",X"0E",X"F3",X"0E",X"58",X"0E",X"FA",X"0E",X"58",X"0E",X"FD",X"0E",X"58",X"0E",X"00", + X"0F",X"6C",X"0E",X"03",X"0F",X"58",X"0E",X"0C",X"0F",X"58",X"0E",X"10",X"0F",X"58",X"0E",X"19", + X"0F",X"58",X"0E",X"20",X"0F",X"58",X"0E",X"FA",X"0E",X"58",X"0E",X"FD",X"0E",X"58",X"0E",X"00", + X"0F",X"6C",X"0E",X"29",X"0F",X"58",X"0E",X"20",X"0F",X"58",X"0E",X"EA",X"0E",X"58",X"0E",X"03", + X"0F",X"58",X"0E",X"0C",X"0F",X"58",X"0E",X"FA",X"0E",X"58",X"0E",X"FD",X"0E",X"58",X"0E",X"00", + X"0F",X"6C",X"0E",X"7E",X"3C",X"C8",X"3D",X"23",X"32",X"2A",X"21",X"7E",X"23",X"E5",X"CD",X"43", + X"0F",X"E1",X"C3",X"03",X"0E",X"AF",X"32",X"29",X"21",X"3D",X"32",X"2A",X"21",X"3E",X"06",X"C3", + X"26",X"0E",X"0D",X"CD",X"2D",X"02",X"32",X"28",X"21",X"CD",X"ED",X"0F",X"3A",X"2A",X"21",X"FE", + X"10",X"F0",X"21",X"28",X"21",X"35",X"C2",X"29",X"0E",X"DF",X"01",X"C3",X"1D",X"0E",X"DF",X"01", + X"3A",X"29",X"21",X"A7",X"C0",X"3A",X"40",X"20",X"3C",X"32",X"40",X"20",X"FE",X"21",X"DA",X"56", + X"0E",X"3E",X"01",X"32",X"40",X"20",X"AF",X"C9",X"EB",X"CD",X"03",X"0E",X"CD",X"15",X"0E",X"CD", + X"3E",X"0E",X"C2",X"5C",X"0E",X"AF",X"32",X"2D",X"20",X"C3",X"49",X"0D",X"EB",X"3E",X"80",X"32", + X"2B",X"21",X"CD",X"03",X"0E",X"CD",X"15",X"0E",X"3A",X"2D",X"20",X"E6",X"02",X"C2",X"90",X"0E", + X"21",X"2B",X"21",X"35",X"CA",X"BD",X"0E",X"CD",X"3E",X"0E",X"C2",X"75",X"0E",X"C3",X"49",X"0D", + X"DF",X"01",X"CD",X"15",X"0E",X"21",X"26",X"32",X"06",X"08",X"3E",X"AA",X"CD",X"41",X"00",X"DF", + X"01",X"CD",X"15",X"0E",X"21",X"26",X"32",X"06",X"08",X"3E",X"55",X"CD",X"41",X"00",X"3A",X"2D", + X"20",X"A7",X"F2",X"90",X"0E",X"21",X"26",X"32",X"06",X"08",X"CD",X"40",X"00",X"21",X"E9",X"20", + X"06",X"08",X"36",X"00",X"23",X"23",X"23",X"23",X"05",X"C2",X"C2",X"0E",X"C3",X"5C",X"0E",X"00", + X"00",X"01",X"01",X"02",X"02",X"03",X"03",X"FF",X"00",X"04",X"FF",X"FF",X"FF",X"FF",X"FF",X"00", + X"05",X"01",X"06",X"02",X"07",X"03",X"08",X"04",X"09",X"FF",X"00",X"0B",X"01",X"0C",X"FF",X"FF", + X"FF",X"FF",X"FF",X"00",X"0D",X"01",X"0E",X"02",X"0F",X"FF",X"00",X"0A",X"FF",X"00",X"13",X"FF", + X"00",X"12",X"FF",X"00",X"10",X"01",X"11",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"18",X"FF",X"FF", + X"00",X"16",X"01",X"17",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"19",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"14",X"01",X"15",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"1A",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"1B",X"FF",X"FF",X"FF",X"FF",X"FF",X"21",X"DB",X"17",X"11",X"8F",X"19",X"3A",X"FD",X"1F", + X"C3",X"05",X"0A",X"87",X"21",X"00",X"40",X"CD",X"2D",X"02",X"5F",X"23",X"56",X"3A",X"2A",X"21", + X"21",X"68",X"20",X"87",X"87",X"87",X"CD",X"2D",X"02",X"06",X"06",X"3A",X"40",X"20",X"EE",X"07", + X"4F",X"E6",X"07",X"C2",X"77",X"0F",X"79",X"D6",X"08",X"F2",X"6E",X"0F",X"3E",X"18",X"4F",X"05", + X"1A",X"91",X"91",X"00",X"77",X"13",X"23",X"CD",X"34",X"16",X"21",X"E8",X"20",X"3A",X"2A",X"21", + X"87",X"87",X"CD",X"2D",X"02",X"1A",X"13",X"77",X"47",X"78",X"FE",X"38",X"C2",X"96",X"0F",X"3E", + X"01",X"EF",X"0A",X"C3",X"E3",X"0F",X"78",X"FE",X"33",X"C2",X"A3",X"0F",X"3E",X"01",X"E7",X"0B", + X"C3",X"12",X"4D",X"78",X"FE",X"70",X"C2",X"BC",X"0F",X"3E",X"10",X"EF",X"0C",X"D5",X"E5",X"21", + X"AD",X"1B",X"11",X"E0",X"1F",X"3E",X"A3",X"C3",X"EB",X"4F",X"19",X"4D",X"78",X"FE",X"50",X"C2", + X"CD",X"0F",X"3E",X"01",X"EF",X"0A",X"3E",X"1F",X"E7",X"0B",X"C3",X"E3",X"0F",X"78",X"FE",X"3F", + X"C2",X"E5",X"0F",X"3E",X"1F",X"E7",X"0B",X"C3",X"12",X"4D",X"E7",X"0B",X"3E",X"01",X"EF",X"0A", + X"C9",X"4F",X"4F",X"DF",X"01",X"23",X"36",X"00",X"23",X"73",X"23",X"72",X"C9",X"3A",X"2A",X"21", + X"3C",X"32",X"2A",X"21",X"FE",X"10",X"F0",X"21",X"E8",X"20",X"87",X"87",X"F3",X"CD",X"2D",X"02"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/roms/mw03.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/roms/mw03.vhd new file mode 100644 index 00000000..cee80385 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/roms/mw03.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity mw03 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of mw03 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"FB",X"CA",X"ED",X"0F",X"47",X"3A",X"29",X"21",X"3C",X"32",X"29",X"21",X"23",X"7E",X"A7",X"CA", + X"7D",X"10",X"35",X"21",X"68",X"20",X"3A",X"2A",X"21",X"87",X"87",X"87",X"CD",X"2D",X"02",X"FE", + X"20",X"DA",X"E2",X"10",X"5E",X"23",X"56",X"78",X"78",X"FE",X"50",X"DA",X"48",X"10",X"DB",X"02", + X"E6",X"04",X"CA",X"36",X"10",X"1D",X"78",X"FE",X"66",X"C2",X"48",X"10",X"3A",X"4A",X"20",X"C6", + X"04",X"92",X"14",X"D2",X"48",X"10",X"15",X"15",X"C5",X"4B",X"42",X"23",X"5E",X"23",X"56",X"1A", + X"2B",X"77",X"23",X"13",X"1A",X"77",X"13",X"D5",X"23",X"5E",X"23",X"56",X"D5",X"E5",X"23",X"7E", + X"23",X"66",X"81",X"6F",X"7C",X"80",X"67",X"EB",X"E1",X"2B",X"2B",X"2B",X"2B",X"72",X"2B",X"73", + X"EB",X"C1",X"D1",X"F1",X"A7",X"F8",X"C3",X"25",X"15",X"13",X"C3",X"81",X"10",X"23",X"5E",X"23", + X"56",X"1A",X"A7",X"CA",X"79",X"10",X"FE",X"CD",X"CA",X"63",X"11",X"FE",X"EB",X"CA",X"9A",X"11", + X"FE",X"01",X"CA",X"2E",X"11",X"FE",X"C3",X"CA",X"23",X"11",X"FE",X"AF",X"CA",X"F0",X"10",X"21", + X"E8",X"20",X"3A",X"2A",X"21",X"87",X"87",X"CD",X"2D",X"02",X"7E",X"FE",X"70",X"01",X"D4",X"FE", + X"CA",X"BC",X"10",X"01",X"F6",X"FF",X"7E",X"FE",X"40",X"D2",X"C7",X"10",X"EB",X"F3",X"2A",X"3B", + X"20",X"09",X"22",X"3B",X"20",X"FB",X"EB",X"36",X"00",X"21",X"68",X"20",X"3A",X"2A",X"21",X"87", + X"87",X"87",X"CD",X"2D",X"02",X"5E",X"23",X"56",X"23",X"23",X"23",X"4E",X"23",X"46",X"EB",X"C3", + X"7F",X"15",X"3A",X"2A",X"21",X"21",X"E8",X"20",X"87",X"87",X"CD",X"2D",X"02",X"C3",X"AA",X"10", + X"3A",X"2A",X"21",X"21",X"E8",X"20",X"87",X"87",X"CD",X"2D",X"02",X"F6",X"80",X"77",X"13",X"1A", + X"4F",X"13",X"1A",X"47",X"13",X"23",X"1A",X"77",X"13",X"23",X"73",X"23",X"72",X"21",X"68",X"20", + X"3A",X"2A",X"21",X"87",X"87",X"87",X"CD",X"2D",X"02",X"11",X"06",X"00",X"19",X"71",X"23",X"70", + X"C3",X"AA",X"10",X"13",X"1A",X"4F",X"13",X"1A",X"47",X"C5",X"D1",X"C3",X"81",X"10",X"21",X"E8", + X"20",X"3A",X"2A",X"21",X"87",X"87",X"CD",X"2D",X"02",X"E6",X"7F",X"77",X"23",X"13",X"1A",X"4F", + X"13",X"1A",X"47",X"13",X"1A",X"13",X"77",X"23",X"73",X"23",X"72",X"21",X"68",X"20",X"3A",X"2A", + X"21",X"87",X"87",X"87",X"CD",X"2D",X"02",X"11",X"06",X"00",X"19",X"71",X"23",X"70",X"06",X"01", + X"C3",X"13",X"10",X"3A",X"2A",X"21",X"F5",X"06",X"10",X"0E",X"00",X"21",X"E8",X"20",X"7E",X"A7", + X"CA",X"83",X"11",X"23",X"23",X"23",X"23",X"0C",X"05",X"C2",X"6E",X"11",X"F1",X"13",X"13",X"13", + X"C3",X"81",X"10",X"79",X"32",X"2A",X"21",X"EB",X"23",X"5E",X"23",X"56",X"23",X"E5",X"CD",X"4D", + X"0F",X"E1",X"F1",X"EB",X"32",X"2A",X"21",X"C3",X"81",X"10",X"21",X"68",X"20",X"3A",X"2A",X"21", + X"87",X"87",X"87",X"CD",X"2D",X"02",X"23",X"23",X"13",X"06",X"04",X"CD",X"77",X"0F",X"C3",X"81", + X"10",X"21",X"2D",X"21",X"06",X"08",X"CD",X"40",X"00",X"3E",X"0F",X"32",X"45",X"21",X"AF",X"32", + X"2C",X"21",X"3A",X"E8",X"20",X"FE",X"40",X"CA",X"10",X"12",X"3A",X"2D",X"21",X"A7",X"F2",X"EC", + X"11",X"2A",X"C7",X"1C",X"06",X"70",X"CD",X"E1",X"06",X"AF",X"32",X"2D",X"21",X"32",X"2E",X"21", + X"DF",X"01",X"2A",X"D8",X"1C",X"06",X"28",X"CD",X"E1",X"06",X"DF",X"01",X"21",X"2D",X"21",X"3A", + X"2C",X"21",X"CD",X"2D",X"02",X"C2",X"C1",X"12",X"11",X"45",X"21",X"1A",X"21",X"E8",X"20",X"87", + X"87",X"CD",X"2D",X"02",X"C2",X"71",X"12",X"EB",X"35",X"EB",X"F2",X"FB",X"11",X"3E",X"0F",X"12", + X"DF",X"01",X"3A",X"E8",X"20",X"FE",X"40",X"C2",X"54",X"12",X"3A",X"2D",X"21",X"A7",X"FA",X"3F", + X"12",X"3E",X"80",X"32",X"2D",X"21",X"21",X"C7",X"1C",X"CD",X"F4",X"14",X"21",X"3E",X"20",X"34", + X"7E",X"E6",X"0F",X"47",X"0E",X"08",X"21",X"1A",X"39",X"CD",X"3D",X"16",X"C3",X"54",X"12",X"3A", + X"EC",X"20",X"FE",X"40",X"C2",X"54",X"12",X"3A",X"2E",X"21",X"A7",X"FA",X"54",X"12",X"21",X"D8", + X"1C",X"CD",X"F4",X"14",X"21",X"2C",X"21",X"34",X"3A",X"40",X"20",X"06",X"04",X"0E",X"04",X"D6", + X"08",X"DA",X"69",X"12",X"04",X"0D",X"C2",X"5F",X"12",X"78",X"BE",X"D2",X"C2",X"11",X"C3",X"BE", + X"11",X"FE",X"40",X"D2",X"07",X"12",X"21",X"3D",X"20",X"35",X"7E",X"E6",X"35",X"C2",X"07",X"12", + X"1A",X"21",X"68",X"20",X"87",X"87",X"87",X"CD",X"2D",X"02",X"D6",X"08",X"5F",X"23",X"56",X"23", + X"23",X"23",X"23",X"7E",X"1F",X"A7",X"82",X"57",X"FE",X"20",X"DA",X"10",X"12",X"3A",X"2C",X"21", + X"21",X"2D",X"21",X"CD",X"2D",X"02",X"36",X"01",X"3A",X"2C",X"21",X"21",X"35",X"21",X"87",X"CD", + X"2D",X"02",X"73",X"23",X"72",X"EB",X"11",X"58",X"13",X"06",X"03",X"CD",X"A0",X"15",X"C3",X"10", + X"12",X"3A",X"2C",X"21",X"21",X"35",X"21",X"87",X"CD",X"2D",X"02",X"5E",X"23",X"56",X"DB",X"02", + X"E6",X"04",X"3E",X"FA",X"C2",X"D9",X"12",X"3E",X"FB",X"83",X"2B",X"77",X"E5",X"CD",X"4F",X"13", + X"E1",X"7E",X"FE",X"18",X"DA",X"31",X"13",X"23",X"66",X"6F",X"11",X"58",X"13",X"06",X"03",X"CD", + X"A0",X"15",X"DF",X"01",X"79",X"A7",X"CA",X"10",X"12",X"3A",X"2C",X"21",X"21",X"35",X"21",X"87", + X"CD",X"2D",X"02",X"5F",X"FE",X"20",X"DA",X"10",X"12",X"23",X"56",X"FE",X"28",X"D2",X"31",X"13", + X"3A",X"4A",X"20",X"BA",X"D2",X"31",X"13",X"C6",X"0F",X"BA",X"DA",X"31",X"13",X"CD",X"37",X"13", + X"3E",X"01",X"32",X"2E",X"20",X"DF",X"01",X"3A",X"2E",X"20",X"A7",X"C2",X"25",X"13",X"C3",X"10", + X"12",X"CD",X"37",X"13",X"C3",X"10",X"12",X"3A",X"2C",X"21",X"21",X"2D",X"21",X"CD",X"2D",X"02", + X"36",X"00",X"3A",X"2C",X"21",X"21",X"35",X"21",X"87",X"CD",X"2D",X"02",X"5F",X"23",X"56",X"21", + X"58",X"13",X"06",X"03",X"EB",X"C3",X"DD",X"15",X"0F",X"00",X"0F",X"11",X"14",X"1F",X"21",X"46", + X"21",X"06",X"28",X"CD",X"34",X"16",X"DF",X"01",X"06",X"14",X"21",X"46",X"21",X"C5",X"E5",X"7E", + X"23",X"66",X"6F",X"CD",X"0C",X"16",X"E1",X"C1",X"DF",X"01",X"23",X"23",X"05",X"C2",X"6D",X"13", + X"06",X"14",X"21",X"46",X"21",X"3A",X"3F",X"20",X"C6",X"01",X"4F",X"E5",X"7E",X"23",X"66",X"6F", + X"C5",X"CD",X"2C",X"16",X"C1",X"E1",X"E5",X"5E",X"23",X"56",X"1D",X"7B",X"FE",X"28",X"D2",X"A3", + X"13",X"1E",X"D8",X"2B",X"73",X"EB",X"C5",X"CD",X"0C",X"16",X"C1",X"E1",X"23",X"23",X"05",X"C2", + X"B7",X"13",X"06",X"14",X"21",X"46",X"21",X"0D",X"C2",X"8B",X"13",X"DF",X"01",X"C3",X"85",X"13", + X"01",X"00",X"00",X"3A",X"58",X"20",X"A7",X"CA",X"18",X"14",X"0F",X"D2",X"D7",X"13",X"21",X"A5", + X"1D",X"CD",X"F4",X"14",X"C3",X"E4",X"13",X"DF",X"01",X"3A",X"30",X"20",X"A7",X"CA",X"D7",X"13", + X"AF",X"32",X"30",X"20",X"3A",X"58",X"20",X"3D",X"87",X"21",X"F4",X"13",X"CD",X"2D",X"02",X"5F", + X"23",X"56",X"EB",X"E9",X"4E",X"14",X"94",X"14",X"78",X"14",X"EC",X"14",X"7E",X"14",X"B6",X"14", + X"78",X"14",X"D9",X"14",X"3A",X"58",X"20",X"3C",X"32",X"58",X"20",X"FE",X"09",X"DC",X"C0",X"01", + X"3E",X"01",X"32",X"58",X"20",X"CD",X"C0",X"01",X"21",X"A5",X"1D",X"CD",X"F4",X"14",X"21",X"73", + X"1D",X"CD",X"F4",X"14",X"3A",X"46",X"20",X"3D",X"CA",X"31",X"14",X"21",X"90",X"1D",X"CD",X"F4", + X"14",X"CD",X"37",X"14",X"C3",X"1E",X"14",X"21",X"03",X"24",X"3A",X"FB",X"1F",X"01",X"20",X"00", + X"16",X"D0",X"86",X"5F",X"09",X"15",X"C2",X"42",X"14",X"A7",X"C8",X"C3",X"48",X"15",X"21",X"BF", + X"1D",X"CD",X"F4",X"14",X"21",X"1A",X"24",X"3A",X"FA",X"1F",X"CD",X"3D",X"14",X"21",X"F9",X"1D", + X"CD",X"F4",X"14",X"21",X"F4",X"01",X"DF",X"01",X"2B",X"7C",X"B5",X"C2",X"66",X"14",X"3A",X"58", + X"20",X"3C",X"32",X"58",X"20",X"C3",X"C3",X"13",X"21",X"C7",X"1E",X"C3",X"60",X"14",X"21",X"BF", + X"1D",X"CD",X"F4",X"14",X"21",X"38",X"1E",X"DB",X"02",X"E6",X"08",X"CA",X"60",X"14",X"21",X"60", + X"1E",X"C3",X"60",X"14",X"3E",X"01",X"32",X"40",X"20",X"DF",X"02",X"78",X"E6",X"3F",X"47",X"03", + X"0A",X"32",X"5B",X"20",X"3A",X"30",X"20",X"A7",X"C2",X"04",X"14",X"2A",X"3B",X"20",X"7C",X"A7", + X"FA",X"04",X"14",X"C3",X"99",X"14",X"3E",X"08",X"32",X"40",X"20",X"21",X"90",X"01",X"22",X"3B", + X"20",X"01",X"00",X"10",X"3E",X"30",X"32",X"5B",X"20",X"DF",X"02",X"AF",X"32",X"66",X"20",X"3A", + X"30",X"20",X"A7",X"CA",X"C4",X"14",X"C3",X"04",X"14",X"3E",X"0B",X"32",X"40",X"20",X"3E",X"01", + X"32",X"3F",X"20",X"21",X"F4",X"01",X"22",X"3B",X"20",X"C3",X"99",X"14",X"3E",X"0D",X"32",X"40", + X"20",X"C3",X"99",X"14",X"5E",X"23",X"56",X"23",X"4E",X"23",X"46",X"23",X"E5",X"7E",X"C5",X"EB", + X"0E",X"08",X"47",X"CD",X"3D",X"16",X"EB",X"C1",X"E1",X"0D",X"CA",X"1D",X"15",X"78",X"A7",X"CA", + X"FB",X"14",X"C5",X"DF",X"01",X"05",X"C2",X"13",X"15",X"C1",X"C3",X"FB",X"14",X"23",X"7E",X"A7", + X"C8",X"23",X"C3",X"F4",X"14",X"C5",X"CD",X"6C",X"15",X"78",X"C1",X"F5",X"7C",X"FE",X"24",X"DA", + X"62",X"15",X"F1",X"E5",X"36",X"00",X"C5",X"47",X"C5",X"1A",X"13",X"D5",X"EB",X"6F",X"26",X"00", + X"05",X"FA",X"48",X"15",X"29",X"C3",X"40",X"15",X"EB",X"7E",X"B3",X"77",X"23",X"72",X"D1",X"C1", + X"0D",X"C2",X"38",X"15",X"78",X"C1",X"E1",X"05",X"C8",X"D5",X"11",X"20",X"00",X"19",X"D1",X"C3", + X"2B",X"15",X"79",X"3D",X"13",X"C2",X"63",X"15",X"F1",X"C3",X"57",X"15",X"7D",X"E6",X"07",X"47", + X"37",X"0E",X"03",X"7C",X"1F",X"67",X"7D",X"1F",X"6F",X"A7",X"0D",X"C2",X"73",X"15",X"C9",X"C5", + X"CD",X"70",X"15",X"C1",X"11",X"20",X"00",X"AF",X"7C",X"FE",X"24",X"DA",X"9A",X"15",X"AF",X"E5", + X"C5",X"77",X"0D",X"23",X"77",X"C2",X"91",X"15",X"C1",X"E1",X"05",X"C8",X"19",X"C3",X"88",X"15", + X"0E",X"00",X"C5",X"CD",X"6C",X"15",X"78",X"C1",X"E5",X"C5",X"47",X"C5",X"1A",X"13",X"D5",X"EB", + X"6F",X"26",X"00",X"05",X"FA",X"BB",X"15",X"29",X"C3",X"B3",X"15",X"EB",X"7E",X"A3",X"B1",X"4F", + X"7E",X"B3",X"77",X"23",X"7E",X"A2",X"B1",X"4F",X"7E",X"B2",X"77",X"69",X"D1",X"C1",X"78",X"C1", + X"4D",X"E1",X"05",X"C8",X"D5",X"11",X"20",X"00",X"19",X"D1",X"C3",X"A8",X"15",X"C5",X"CD",X"6C", + X"15",X"78",X"C1",X"C5",X"47",X"C5",X"1A",X"13",X"D5",X"EB",X"6F",X"26",X"00",X"05",X"FA",X"F5", + X"15",X"29",X"C3",X"ED",X"15",X"EB",X"7B",X"2F",X"A6",X"77",X"23",X"7A",X"2F",X"A6",X"77",X"11", + X"1F",X"00",X"19",X"D1",X"C1",X"78",X"C1",X"05",X"C2",X"E3",X"15",X"C9",X"CD",X"6C",X"15",X"48", + X"06",X"01",X"11",X"C0",X"13",X"1A",X"13",X"EB",X"6F",X"26",X"00",X"0D",X"FA",X"23",X"16",X"29", + X"C3",X"1B",X"16",X"EB",X"7E",X"B3",X"77",X"23",X"7E",X"B2",X"77",X"C9",X"11",X"C0",X"13",X"06", + X"01",X"C3",X"DD",X"15",X"1A",X"77",X"13",X"23",X"05",X"C2",X"34",X"16",X"C9",X"C5",X"E5",X"21", + X"5B",X"16",X"58",X"16",X"00",X"EB",X"29",X"29",X"29",X"19",X"EB",X"E1",X"1A",X"77",X"13",X"C5", + X"01",X"20",X"00",X"09",X"C1",X"0D",X"C2",X"4C",X"16",X"C1",X"C9",X"00",X"3E",X"45",X"49",X"51", + X"3E",X"00",X"00",X"00",X"00",X"21",X"7F",X"01",X"00",X"00",X"00",X"00",X"23",X"45",X"49",X"49", + X"31",X"00",X"00",X"00",X"42",X"41",X"49",X"59",X"66",X"00",X"00",X"00",X"0C",X"14",X"24",X"7F", + X"04",X"00",X"00",X"00",X"72",X"51",X"51",X"51",X"4E",X"00",X"00",X"00",X"1E",X"29",X"49",X"49", + X"46",X"00",X"00",X"00",X"40",X"47",X"48",X"50",X"60",X"00",X"00",X"00",X"36",X"49",X"49",X"49", + X"36",X"00",X"00",X"00",X"31",X"49",X"49",X"4A",X"3C",X"00",X"00",X"00",X"1F",X"24",X"44",X"24", + X"1F",X"00",X"00",X"00",X"7F",X"49",X"49",X"49",X"36",X"00",X"00",X"00",X"3E",X"41",X"41",X"41", + X"22",X"00",X"00",X"00",X"7F",X"41",X"41",X"41",X"3E",X"00",X"00",X"00",X"7F",X"49",X"49",X"49", + X"41",X"00",X"00",X"00",X"7F",X"48",X"48",X"48",X"40",X"00",X"00",X"00",X"3E",X"41",X"41",X"45", + X"47",X"00",X"00",X"00",X"7F",X"08",X"08",X"08",X"7F",X"00",X"00",X"00",X"00",X"41",X"7F",X"41", + X"00",X"00",X"00",X"00",X"02",X"01",X"01",X"01",X"7E",X"00",X"00",X"00",X"7F",X"08",X"14",X"22", + X"41",X"00",X"00",X"00",X"7F",X"01",X"01",X"01",X"01",X"00",X"00",X"00",X"7F",X"20",X"18",X"20", + X"7F",X"00",X"00",X"00",X"7F",X"10",X"08",X"04",X"7F",X"00",X"00",X"00",X"3E",X"41",X"41",X"41", + X"3E",X"00",X"00",X"00",X"7F",X"48",X"48",X"48",X"30",X"00",X"00",X"00",X"3E",X"41",X"45",X"42", + X"3D",X"00",X"00",X"00",X"7F",X"48",X"4C",X"4A",X"31",X"00",X"00",X"00",X"32",X"49",X"49",X"49", + X"26",X"00",X"00",X"00",X"40",X"40",X"7F",X"40",X"40",X"00",X"00",X"00",X"7E",X"01",X"01",X"01", + X"7E",X"00",X"00",X"00",X"7C",X"02",X"01",X"02",X"7C",X"00",X"00",X"00",X"7F",X"02",X"0C",X"02", + X"7F",X"00",X"00",X"00",X"63",X"14",X"08",X"14",X"63",X"00",X"00",X"00",X"60",X"10",X"0F",X"10", + X"60",X"00",X"00",X"00",X"43",X"45",X"49",X"51",X"61",X"00",X"00",X"00",X"08",X"14",X"22",X"41", + X"00",X"00",X"00",X"00",X"00",X"41",X"22",X"14",X"08",X"00",X"00",X"00",X"14",X"14",X"14",X"14", + X"14",X"00",X"00",X"00",X"22",X"14",X"7F",X"14",X"22",X"00",X"00",X"00",X"30",X"40",X"45",X"48", + X"30",X"00",X"00",X"00",X"36",X"49",X"49",X"35",X"02",X"05",X"00",X"00",X"08",X"08",X"3E",X"08", + X"08",X"00",X"00",X"00",X"08",X"08",X"08",X"08",X"08",X"00",X"00",X"00",X"04",X"08",X"08",X"08", + X"10",X"00",X"00",X"00",X"00",X"00",X"7B",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"10",X"20",X"40",X"00",X"00",X"00",X"FB",X"17",X"00",X"00",X"B0", + X"01",X"B8",X"03",X"5C",X"07",X"EE",X"0E",X"13",X"19",X"4F",X"1E",X"E8",X"02",X"4F",X"1E",X"13", + X"19",X"EE",X"0E",X"5C",X"07",X"B8",X"03",X"B0",X"01",X"00",X"00",X"DB",X"17",X"00",X"00",X"B0"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/roms/mw04.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/roms/mw04.vhd new file mode 100644 index 00000000..3b6861b8 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/roms/mw04.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity mw04 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of mw04 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"01",X"B8",X"03",X"5C",X"07",X"EE",X"0E",X"F3",X"19",X"FF",X"1F",X"F8",X"03",X"FF",X"1F",X"F3", + X"19",X"EE",X"0E",X"5C",X"07",X"B8",X"03",X"B0",X"01",X"00",X"00",X"3B",X"18",X"00",X"00",X"80", + X"07",X"80",X"0F",X"C0",X"1D",X"E0",X"3B",X"F8",X"67",X"5E",X"7C",X"C7",X"08",X"5E",X"7C",X"F8", + X"67",X"E0",X"3B",X"C0",X"1D",X"80",X"0F",X"80",X"07",X"00",X"00",X"1B",X"18",X"00",X"00",X"80", + X"07",X"80",X"0F",X"C0",X"1D",X"E0",X"3B",X"F8",X"7F",X"5E",X"7C",X"FF",X"08",X"5E",X"7C",X"F8", + X"7F",X"E0",X"3B",X"C0",X"1D",X"80",X"0F",X"80",X"07",X"00",X"00",X"7B",X"18",X"00",X"00",X"F0", + X"0F",X"80",X"1F",X"80",X"34",X"E0",X"6F",X"38",X"79",X"9E",X"30",X"BF",X"1F",X"9E",X"30",X"38", + X"79",X"E0",X"6F",X"80",X"34",X"80",X"1F",X"F0",X"0F",X"00",X"00",X"5B",X"18",X"00",X"00",X"F0", + X"0F",X"80",X"1F",X"80",X"34",X"E0",X"6F",X"38",X"7F",X"9E",X"36",X"B1",X"1F",X"9E",X"36",X"38", + X"7F",X"E0",X"6F",X"80",X"34",X"80",X"1F",X"F0",X"0F",X"00",X"00",X"BB",X"18",X"00",X"00",X"F0", + X"0F",X"C8",X"13",X"40",X"02",X"E0",X"07",X"70",X"5F",X"BF",X"7B",X"58",X"70",X"BF",X"7B",X"70", + X"5F",X"E0",X"07",X"40",X"02",X"C8",X"13",X"F0",X"0F",X"00",X"00",X"9B",X"18",X"00",X"00",X"F0", + X"0F",X"C8",X"13",X"40",X"02",X"E0",X"07",X"70",X"5F",X"BF",X"7B",X"5E",X"7C",X"BF",X"7B",X"70", + X"5F",X"E0",X"07",X"40",X"02",X"C8",X"13",X"F0",X"0F",X"00",X"00",X"FB",X"18",X"00",X"00",X"F0", + X"01",X"F8",X"03",X"0C",X"06",X"06",X"0C",X"E3",X"18",X"BF",X"1F",X"1F",X"1F",X"BF",X"1F",X"E3", + X"18",X"06",X"0C",X"0C",X"06",X"F8",X"03",X"F0",X"01",X"00",X"00",X"1B",X"19",X"00",X"00",X"F0", + X"01",X"F8",X"03",X"0C",X"07",X"06",X"0F",X"E3",X"1F",X"B3",X"19",X"13",X"19",X"B3",X"19",X"FF", + X"18",X"1E",X"0C",X"1C",X"06",X"F8",X"03",X"F0",X"01",X"00",X"00",X"3B",X"19",X"00",X"00",X"F0", + X"01",X"F8",X"03",X"EC",X"06",X"E6",X"0C",X"E3",X"18",X"B3",X"19",X"13",X"19",X"B3",X"19",X"E3", + X"18",X"E6",X"0C",X"EC",X"06",X"F8",X"03",X"F0",X"01",X"00",X"00",X"DB",X"18",X"00",X"00",X"F0", + X"01",X"F8",X"03",X"1C",X"06",X"1E",X"0C",X"FF",X"18",X"B3",X"19",X"13",X"19",X"B3",X"19",X"E3", + X"1F",X"06",X"0F",X"0C",X"07",X"F8",X"03",X"F0",X"01",X"00",X"00",X"68",X"19",X"00",X"1C",X"2A", + X"75",X"6B",X"75",X"3D",X"2F",X"1E",X"0C",X"00",X"75",X"19",X"00",X"0C",X"1E",X"2F",X"3B",X"65", + X"7B",X"7D",X"32",X"1C",X"00",X"82",X"19",X"00",X"18",X"3C",X"7E",X"5A",X"5F",X"6B",X"57",X"2A", + X"1C",X"00",X"5B",X"19",X"00",X"1C",X"26",X"5B",X"6F",X"5D",X"72",X"7E",X"3C",X"18",X"00",X"59", + X"1A",X"03",X"00",X"00",X"00",X"00",X"0F",X"00",X"00",X"00",X"00",X"1F",X"00",X"00",X"00",X"00", + X"3E",X"00",X"00",X"00",X"00",X"7C",X"00",X"00",X"00",X"00",X"F8",X"00",X"00",X"00",X"00",X"F0", + X"01",X"00",X"00",X"00",X"E0",X"03",X"00",X"00",X"00",X"C0",X"0F",X"00",X"00",X"00",X"80",X"1F", + X"00",X"00",X"00",X"00",X"2F",X"00",X"00",X"10",X"00",X"7E",X"00",X"00",X"00",X"00",X"7E",X"00", + X"00",X"00",X"00",X"FC",X"00",X"00",X"00",X"00",X"E8",X"03",X"00",X"00",X"00",X"D0",X"0B",X"00", + X"00",X"00",X"F0",X"15",X"00",X"00",X"00",X"A0",X"2B",X"00",X"00",X"00",X"40",X"55",X"00",X"00", + X"00",X"80",X"EA",X"00",X"00",X"00",X"00",X"DD",X"03",X"00",X"00",X"00",X"36",X"05",X"00",X"00", + X"00",X"AA",X"08",X"00",X"00",X"00",X"1C",X"1B",X"00",X"00",X"00",X"58",X"36",X"00",X"00",X"00", + X"A0",X"59",X"00",X"00",X"00",X"40",X"67",X"00",X"00",X"00",X"C0",X"CC",X"01",X"00",X"00",X"80", + X"45",X"01",X"00",X"00",X"00",X"AB",X"03",X"00",X"00",X"00",X"50",X"06",X"00",X"00",X"00",X"A4", + X"0C",X"00",X"00",X"00",X"8C",X"05",X"00",X"00",X"00",X"18",X"09",X"00",X"00",X"00",X"30",X"11", + X"00",X"00",X"00",X"40",X"02",X"00",X"00",X"00",X"80",X"04",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"8F",X"19",X"03",X"00",X"00",X"00",X"00", + X"0F",X"00",X"00",X"00",X"00",X"1F",X"00",X"00",X"00",X"00",X"3E",X"00",X"00",X"00",X"00",X"7C", + X"00",X"00",X"00",X"00",X"F8",X"00",X"00",X"00",X"00",X"F0",X"01",X"00",X"00",X"00",X"E0",X"07", + X"00",X"00",X"00",X"C0",X"0F",X"00",X"00",X"00",X"80",X"1F",X"00",X"00",X"00",X"00",X"2F",X"00", + X"00",X"00",X"00",X"6E",X"00",X"00",X"00",X"00",X"DA",X"00",X"00",X"00",X"00",X"EC",X"01",X"00", + X"00",X"00",X"A8",X"03",X"00",X"00",X"00",X"5C",X"0B",X"00",X"00",X"00",X"E0",X"16",X"00",X"00", + X"00",X"A0",X"2D",X"00",X"00",X"00",X"C0",X"71",X"00",X"00",X"00",X"80",X"E5",X"00",X"00",X"00", + X"00",X"CB",X"01",X"00",X"00",X"00",X"36",X"05",X"00",X"00",X"00",X"68",X"02",X"00",X"00",X"00", + X"94",X"0C",X"00",X"00",X"00",X"48",X"39",X"00",X"00",X"00",X"90",X"52",X"00",X"00",X"00",X"20", + X"A5",X"00",X"00",X"00",X"C0",X"48",X"01",X"00",X"00",X"80",X"05",X"02",X"00",X"00",X"00",X"2B", + X"05",X"00",X"00",X"00",X"54",X"0A",X"00",X"00",X"00",X"A8",X"14",X"00",X"00",X"00",X"94",X"01", + X"00",X"00",X"00",X"08",X"01",X"00",X"00",X"00",X"10",X"02",X"00",X"00",X"00",X"20",X"04",X"00", + X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"23",X"1B",X"00",X"00",X"20",X"00",X"30",X"00",X"30",X"00",X"30",X"00",X"34", + X"00",X"3C",X"00",X"2C",X"00",X"7C",X"00",X"7C",X"00",X"3C",X"00",X"3C",X"00",X"3C",X"00",X"3C", + X"00",X"3C",X"00",X"BC",X"00",X"7C",X"00",X"7C",X"00",X"7C",X"01",X"FE",X"00",X"7E",X"00",X"FE", + X"00",X"FE",X"01",X"7E",X"03",X"FE",X"0F",X"7E",X"0F",X"FC",X"01",X"FC",X"03",X"FC",X"00",X"7C", + X"01",X"7C",X"02",X"7C",X"04",X"3C",X"00",X"38",X"00",X"3C",X"00",X"7A",X"00",X"B8",X"00",X"38", + X"00",X"10",X"00",X"00",X"00",X"75",X"1B",X"40",X"A0",X"00",X"60",X"FF",X"F0",X"FF",X"60",X"00", + X"A0",X"40",X"82",X"1B",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00", + X"00",X"6C",X"00",X"FE",X"03",X"6C",X"00",X"38",X"00",X"F7",X"01",X"7F",X"1F",X"1E",X"FE",X"7F", + X"1F",X"F7",X"01",X"38",X"00",X"6C",X"00",X"FE",X"03",X"6C",X"00",X"00",X"00",X"B9",X"1B",X"00", + X"00",X"1C",X"0E",X"3B",X"3B",X"0E",X"1C",X"00",X"00",X"AD",X"1B",X"00",X"00",X"1C",X"0E",X"3F", + X"3F",X"0E",X"1C",X"00",X"00",X"E3",X"1B",X"3E",X"7C",X"63",X"C6",X"DD",X"BB",X"DD",X"BB",X"63", + X"C6",X"3E",X"7C",X"00",X"00",X"00",X"00",X"3E",X"7C",X"63",X"C6",X"DD",X"BB",X"DD",X"BB",X"63", + X"C6",X"3E",X"7C",X"C5",X"1B",X"3E",X"7C",X"6B",X"B6",X"D5",X"AB",X"D5",X"AB",X"6B",X"D6",X"BE", + X"7D",X"C0",X"03",X"C0",X"03",X"BE",X"7D",X"6B",X"D6",X"D5",X"AB",X"D5",X"AB",X"6B",X"D6",X"3E", + X"7C",X"0D",X"1C",X"00",X"00",X"3C",X"05",X"FF",X"1F",X"3C",X"05",X"00",X"00",X"01",X"1C",X"00", + X"00",X"3C",X"05",X"F7",X"1F",X"3C",X"05",X"00",X"00",X"80",X"00",X"80",X"02",X"50",X"48",X"54", + X"21",X"2A",X"04",X"40",X"0B",X"A8",X"24",X"D2",X"0D",X"E0",X"0A",X"F8",X"C7",X"F0",X"24",X"61", + X"04",X"D8",X"1A",X"54",X"25",X"00",X"02",X"88",X"15",X"A4",X"22",X"00",X"00",X"80",X"00",X"54", + X"2A",X"BB",X"56",X"30",X"E8",X"30",X"56",X"B3",X"2A",X"94",X"80",X"B4",X"28",X"1D",X"80",X"43", + X"52",X"24",X"80",X"5C",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"10",X"20",X"00",X"40",X"20", + X"39",X"12",X"2A",X"80",X"C8",X"46",X"09",X"04",X"10",X"95",X"8F",X"A7",X"02",X"00",X"88",X"F1", + X"5E",X"04",X"00",X"55",X"34",X"29",X"22",X"90",X"B2",X"D2",X"76",X"11",X"24",X"F5",X"6F",X"4B", + X"08",X"40",X"FF",X"FF",X"BB",X"02",X"C0",X"FF",X"FF",X"7F",X"02",X"BB",X"FF",X"FF",X"FF",X"DD", + X"C0",X"FF",X"FF",X"7F",X"00",X"20",X"DF",X"FF",X"1F",X"03",X"00",X"F5",X"EF",X"C9",X"20",X"92", + X"EC",X"52",X"76",X"49",X"48",X"CA",X"7C",X"77",X"10",X"04",X"A5",X"97",X"0D",X"00",X"10",X"52", + X"6A",X"55",X"09",X"08",X"28",X"D5",X"22",X"13",X"00",X"94",X"38",X"05",X"00",X"00",X"04",X"10", + X"08",X"00",X"00",X"20",X"10",X"00",X"00",X"1A",X"2C",X"0C",X"03",X"0D",X"18",X"0C",X"14",X"12", + X"17",X"10",X"2E",X"1D",X"12",X"16",X"0E",X"00",X"18",X"28",X"05",X"03",X"1B",X"0E",X"0A",X"0D", + X"22",X"00",X"10",X"29",X"12",X"00",X"10",X"0A",X"16",X"0E",X"2E",X"18",X"1F",X"0E",X"1B",X"2E", + X"19",X"15",X"0A",X"22",X"0E",X"1B",X"2E",X"01",X"00",X"10",X"29",X"12",X"00",X"10",X"0A",X"16", + X"0E",X"2E",X"18",X"1F",X"0E",X"1B",X"2E",X"19",X"15",X"0A",X"22",X"0E",X"1B",X"2E",X"02",X"00", + X"10",X"2B",X"0D",X"00",X"1D",X"1B",X"22",X"2E",X"19",X"15",X"0A",X"22",X"0E",X"1B",X"24",X"01", + X"25",X"00",X"10",X"2B",X"0D",X"00",X"1D",X"1B",X"22",X"2E",X"19",X"15",X"0A",X"22",X"0E",X"1B", + X"24",X"02",X"25",X"00",X"1E",X"25",X"1A",X"00",X"1C",X"0C",X"18",X"1B",X"0E",X"24",X"01",X"25", + X"2E",X"11",X"12",X"2B",X"1C",X"0C",X"18",X"1B",X"0E",X"2E",X"1C",X"0C",X"18",X"1B",X"0E",X"24", + X"02",X"25",X"00",X"1C",X"2D",X"05",X"00",X"19",X"18",X"12",X"17",X"1D",X"00",X"01",X"36",X"06", + X"00",X"0C",X"1B",X"0E",X"0D",X"12",X"1D",X"00",X"01",X"25",X"06",X"00",X"0E",X"17",X"0E",X"1B", + X"10",X"22",X"00",X"14",X"30",X"04",X"0F",X"19",X"1E",X"1C",X"11",X"01",X"12",X"2A",X"0F",X"0F", + X"01",X"2E",X"19",X"15",X"0A",X"22",X"0E",X"1B",X"2E",X"0B",X"1E",X"1D",X"1D",X"18",X"17",X"00", + X"10",X"2A",X"10",X"0F",X"02",X"2E",X"19",X"15",X"0A",X"22",X"0E",X"1B",X"1C",X"2E",X"0B",X"1E", + X"1D",X"1D",X"18",X"17",X"00",X"03",X"27",X"15",X"00",X"27",X"2E",X"1C",X"11",X"12",X"17",X"2E", + X"17",X"12",X"11",X"18",X"17",X"2E",X"14",X"12",X"14",X"0A",X"14",X"1E",X"2E",X"27",X"00",X"1A", + X"2C",X"0A",X"1F",X"18",X"23",X"16",X"0A",X"2E",X"2E",X"20",X"0A",X"1B",X"1C",X"01",X"18",X"2F", + X"05",X"1F",X"15",X"0E",X"1D",X"2F",X"1C",X"01",X"16",X"2B",X"0C",X"1F",X"1D",X"1B",X"0A",X"1F", + X"0E",X"15",X"29",X"0F",X"12",X"10",X"11",X"1D",X"01",X"14",X"2B",X"0B",X"1F",X"1C",X"19",X"0A", + X"0C",X"0E",X"2E",X"20",X"18",X"1B",X"15",X"0D",X"00",X"10",X"2E",X"07",X"00",X"27",X"1C",X"0C", + X"18",X"1B",X"0E",X"27",X"01",X"0E",X"2B",X"0E",X"00",X"1E",X"0F",X"18",X"2E",X"2E",X"2E",X"2E", + X"01",X"00",X"00",X"2C",X"05",X"00",X"00",X"01",X"0C",X"2B",X"0C",X"00",X"16",X"0E",X"1D",X"0E", + X"18",X"2E",X"2E",X"05",X"00",X"2C",X"07",X"00",X"01",X"0A",X"2B",X"0A",X"00",X"0C",X"18",X"16", + X"0E",X"1D",X"2E",X"2E",X"08",X"00",X"00",X"00",X"12",X"2A",X"0F",X"00",X"27",X"0C",X"11",X"0A", + X"1B",X"10",X"0E",X"2E",X"0E",X"17",X"0E",X"1B",X"10",X"22",X"27",X"01",X"10",X"2B",X"0F",X"00", + X"0D",X"18",X"0C",X"14",X"12",X"17",X"10",X"2E",X"2E",X"2A",X"01",X"05",X"00",X"00",X"00",X"01", + X"0E",X"29",X"13",X"00",X"27",X"0C",X"1B",X"0A",X"1C",X"11",X"2E",X"15",X"18",X"1C",X"1D",X"2E", + X"0E",X"17",X"0E",X"1B",X"10",X"22",X"27",X"01",X"0C",X"2B",X"0F",X"00",X"1E",X"0F",X"18",X"2E", + X"2E",X"2E",X"2E",X"2E",X"2E",X"2B",X"01",X"05",X"00",X"00",X"00",X"01",X"0A",X"2B",X"0E",X"00", + X"16",X"0E",X"1D",X"0E",X"18",X"2E",X"2E",X"2E",X"2E",X"2B",X"08",X"00",X"00",X"00",X"01",X"08", + X"2B",X"0F",X"00",X"0C",X"18",X"16",X"0E",X"1D",X"2E",X"2E",X"2E",X"2E",X"2B",X"02",X"00",X"00", + X"00",X"00",X"01",X"06",X"2B",X"0F",X"00",X"16",X"12",X"1C",X"1C",X"12",X"15",X"0E",X"2E",X"2E", + X"2B",X"01",X"00",X"00",X"00",X"00",X"00",X"14",X"2D",X"0B",X"00",X"12",X"17",X"1C",X"0E",X"1B", + X"1D",X"2E",X"0C",X"18",X"12",X"17",X"01",X"12",X"2B",X"0E",X"00",X"01",X"2E",X"18",X"1B",X"2E", + X"02",X"2E",X"19",X"15",X"0A",X"22",X"0E",X"1B",X"1C",X"01",X"10",X"2B",X"0F",X"00",X"01",X"2E", + X"19",X"15",X"0A",X"22",X"0E",X"1B",X"2E",X"01",X"2E",X"0C",X"18",X"12",X"17",X"01",X"0E",X"2A", + X"11",X"00",X"02",X"2E",X"19",X"15",X"0A",X"22",X"0E",X"1B",X"1C",X"2E",X"02",X"2E",X"0C",X"18", + X"12",X"17",X"1C",X"00",X"DE",X"88",X"D0",X"B8",X"C2",X"26",X"B6",X"CC",X"B0",X"60",X"A8",X"44", + X"A6",X"9C",X"9A",X"FC",X"8B",X"C8",X"7C",X"90",X"76",X"24",X"7C",X"90",X"68",X"C0",X"60",X"60", + X"4C",X"DC",X"48",X"84",X"3E",X"30",X"34",X"F8",X"2C",X"48",X"18",X"30",X"07",X"07",X"07",X"07", + X"45",X"1F",X"0A",X"15",X"0A",X"40",X"1F",X"15",X"0A",X"15",X"51",X"1F",X"00",X"0A",X"07",X"0A", + X"00",X"58",X"1F",X"00",X"05",X"0E",X"05",X"00",X"5F",X"1F",X"00",X"0A",X"0D",X"0A",X"00",X"4A", + X"1F",X"00",X"05",X"0B",X"05",X"00",X"66",X"1F",X"FF",X"0F",X"6A",X"1F",X"00",X"00",X"80",X"07", + X"E0",X"1B",X"F8",X"77",X"47",X"5C",X"FC",X"77",X"F0",X"3B",X"E0",X"1D",X"C0",X"0F",X"80",X"07", + X"00",X"00",X"A6",X"1F",X"00",X"00",X"00",X"00",X"D8",X"00",X"DC",X"01",X"FE",X"03",X"73",X"06", + X"FD",X"05",X"FF",X"07",X"FF",X"07",X"FF",X"07",X"FD",X"05",X"73",X"06",X"FE",X"03",X"DC",X"01", + X"D8",X"00",X"00",X"00",X"00",X"00",X"CA",X"1F",X"00",X"00",X"00",X"00",X"F8",X"00",X"DC",X"01", + X"DE",X"03",X"53",X"06",X"DD",X"05",X"DF",X"07",X"DF",X"07",X"DF",X"07",X"FD",X"05",X"73",X"06", + X"FE",X"03",X"FC",X"01",X"F8",X"00",X"00",X"00",X"00",X"00",X"82",X"1F",X"00",X"00",X"00",X"00", + X"F8",X"00",X"FC",X"01",X"FE",X"03",X"73",X"06",X"FD",X"05",X"DF",X"07",X"DF",X"07",X"DF",X"07", + X"DD",X"05",X"53",X"06",X"DE",X"03",X"DC",X"01",X"F8",X"00",X"00",X"00",X"00",X"00",X"3A",X"2A", + X"21",X"FE",X"10",X"E2",X"EE",X"1F",X"C3",X"4A",X"07",X"FF",X"85",X"78",X"E9",X"01",X"6C",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/roms/mw05.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/roms/mw05.vhd new file mode 100644 index 00000000..02127e5a --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/roms/mw05.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity mw05 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of mw05 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"40",X"40",X"6D",X"40",X"B0",X"40",X"EB",X"40",X"1C",X"41",X"A4",X"41",X"DF",X"41",X"12",X"42", + X"45",X"42",X"78",X"42",X"21",X"46",X"A4",X"42",X"85",X"43",X"62",X"44",X"CA",X"44",X"F6",X"44", + X"22",X"45",X"A3",X"45",X"E4",X"45",X"2D",X"46",X"34",X"49",X"99",X"49",X"FD",X"49",X"27",X"4B", + X"4F",X"4C",X"49",X"4D",X"41",X"4E",X"69",X"4E",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"D0",X"70",X"DB",X"17",X"02",X"0F",X"20",X"01",X"FE",X"00",X"28",X"CD",X"53",X"40",X"01",X"FD", + X"01",X"30",X"76",X"D0",X"70",X"1B",X"18",X"02",X"0F",X"02",X"01",X"FE",X"00",X"20",X"01",X"FE", + X"01",X"00",X"F8",X"00",X"01",X"FE",X"01",X"18",X"01",X"FF",X"FF",X"20",X"76",X"D0",X"30",X"DB", + X"17",X"02",X"0F",X"20",X"01",X"FE",X"00",X"10",X"CD",X"90",X"40",X"01",X"FE",X"01",X"08",X"01", + X"FE",X"FF",X"08",X"01",X"FD",X"01",X"10",X"AF",X"FE",X"FF",X"06",X"01",X"FE",X"01",X"10",X"76", + X"D0",X"30",X"1B",X"18",X"02",X"0F",X"02",X"01",X"FE",X"01",X"18",X"01",X"FE",X"FF",X"10",X"01", + X"FE",X"00",X"10",X"AF",X"FE",X"FF",X"08",X"01",X"FE",X"FF",X"08",X"01",X"FE",X"01",X"10",X"76", + X"D0",X"A0",X"DB",X"17",X"02",X"0F",X"20",X"01",X"FE",X"00",X"18",X"CD",X"C7",X"40",X"01",X"FD", + X"00",X"08",X"01",X"FD",X"FF",X"18",X"76",X"D0",X"A0",X"1B",X"18",X"02",X"0F",X"02",X"01",X"FE", + X"00",X"18",X"01",X"FE",X"01",X"08",X"01",X"FE",X"FF",X"08",X"01",X"FE",X"00",X"10",X"AF",X"FE", + X"FF",X"08",X"01",X"FE",X"01",X"10",X"01",X"FE",X"FF",X"10",X"76",X"D0",X"D0",X"DB",X"17",X"02", + X"0F",X"20",X"01",X"FE",X"00",X"10",X"CD",X"0E",X"41",X"01",X"FE",X"00",X"10",X"AF",X"FF",X"FF", + X"10",X"01",X"FE",X"FF",X"08",X"01",X"FE",X"01",X"10",X"01",X"FD",X"00",X"18",X"76",X"D0",X"D0", + X"1B",X"18",X"02",X"0F",X"02",X"01",X"FE",X"00",X"20",X"C3",X"5E",X"40",X"D0",X"88",X"5B",X"18", + X"02",X"0F",X"10",X"CD",X"3C",X"41",X"CD",X"51",X"41",X"01",X"FE",X"FF",X"0A",X"AF",X"FE",X"FF", + X"02",X"01",X"FE",X"01",X"0A",X"AF",X"FE",X"01",X"02",X"C3",X"29",X"41",X"D0",X"76",X"5B",X"18", + X"02",X"0F",X"10",X"AF",X"00",X"00",X"12",X"CD",X"66",X"41",X"01",X"FF",X"FF",X"10",X"C3",X"29", + X"41",X"D0",X"9A",X"5B",X"18",X"02",X"0F",X"10",X"AF",X"00",X"00",X"12",X"CD",X"77",X"41",X"01", + X"FF",X"01",X"10",X"C3",X"29",X"41",X"D0",X"5C",X"5B",X"18",X"02",X"0F",X"10",X"AF",X"00",X"00", + X"12",X"CD",X"88",X"41",X"C3",X"4A",X"41",X"D0",X"B4",X"5B",X"18",X"02",X"0F",X"10",X"AF",X"00", + X"00",X"12",X"CD",X"96",X"41",X"C3",X"5F",X"41",X"D0",X"40",X"5B",X"18",X"02",X"0F",X"10",X"AF", + X"00",X"00",X"12",X"C3",X"4A",X"41",X"D0",X"CE",X"5B",X"18",X"02",X"0F",X"10",X"AF",X"00",X"00", + X"12",X"C3",X"5F",X"41",X"D0",X"30",X"5B",X"19",X"01",X"0B",X"50",X"CD",X"B9",X"41",X"01",X"FE", + X"01",X"14",X"01",X"FE",X"FF",X"14",X"C3",X"AE",X"41",X"D0",X"40",X"75",X"19",X"01",X"0B",X"50", + X"AF",X"00",X"00",X"10",X"CD",X"CA",X"41",X"C3",X"AE",X"41",X"D0",X"40",X"68",X"19",X"01",X"0B", + X"50",X"AF",X"00",X"00",X"10",X"01",X"FE",X"00",X"28",X"CD",X"40",X"40",X"C3",X"AE",X"41",X"D0", + X"50",X"82",X"19",X"01",X"0B",X"50",X"CD",X"EC",X"41",X"C3",X"AE",X"41",X"D0",X"60",X"75",X"19", + X"01",X"0B",X"50",X"AF",X"00",X"00",X"18",X"CD",X"FD",X"41",X"C3",X"AE",X"41",X"D0",X"50",X"68", + X"19",X"01",X"0B",X"50",X"AF",X"00",X"00",X"10",X"01",X"FE",X"00",X"28",X"CD",X"6D",X"40",X"C3", + X"AE",X"41",X"D0",X"70",X"5B",X"19",X"01",X"0B",X"50",X"CD",X"1F",X"42",X"C3",X"AE",X"41",X"D0", + X"80",X"68",X"19",X"01",X"0B",X"50",X"AF",X"00",X"00",X"10",X"CD",X"30",X"42",X"C3",X"AE",X"41", + X"D0",X"70",X"75",X"19",X"01",X"0B",X"50",X"AF",X"00",X"00",X"10",X"01",X"FE",X"00",X"28",X"CD", + X"B0",X"40",X"C3",X"AE",X"41",X"D0",X"90",X"82",X"19",X"01",X"0B",X"50",X"CD",X"52",X"42",X"C3", + X"AE",X"41",X"D0",X"A0",X"68",X"19",X"01",X"0B",X"50",X"AF",X"00",X"00",X"10",X"CD",X"63",X"42", + X"C3",X"AE",X"41",X"D0",X"90",X"75",X"19",X"01",X"0B",X"50",X"AF",X"00",X"00",X"10",X"01",X"FE", + X"00",X"20",X"CD",X"EB",X"40",X"C3",X"AE",X"41",X"D0",X"B0",X"5B",X"19",X"01",X"0B",X"50",X"CD", + X"85",X"42",X"C3",X"AE",X"41",X"D0",X"C0",X"5B",X"19",X"01",X"0B",X"50",X"AF",X"00",X"00",X"10", + X"CD",X"96",X"42",X"C3",X"AE",X"41",X"D0",X"B0",X"5B",X"19",X"01",X"0B",X"50",X"AF",X"00",X"00", + X"18",X"C3",X"AE",X"41",X"D0",X"80",X"9B",X"18",X"02",X"0F",X"30",X"CD",X"E9",X"42",X"01",X"FF", + X"FF",X"10",X"01",X"FF",X"01",X"10",X"CD",X"1F",X"43",X"01",X"FF",X"00",X"10",X"CD",X"2B",X"43", + X"01",X"FF",X"00",X"10",X"AF",X"FF",X"FF",X"10",X"01",X"FF",X"FF",X"10",X"CD",X"35",X"43",X"01", + X"FF",X"FF",X"10",X"CD",X"3F",X"43",X"01",X"FF",X"FF",X"10",X"CD",X"49",X"43",X"01",X"FF",X"00", + X"10",X"CD",X"53",X"43",X"01",X"FF",X"00",X"30",X"76",X"D0",X"60",X"9B",X"18",X"02",X"0F",X"30", + X"AF",X"00",X"00",X"60",X"01",X"FF",X"FF",X"10",X"01",X"FF",X"01",X"10",X"CD",X"5D",X"43",X"01", + X"FF",X"00",X"10",X"CD",X"67",X"43",X"01",X"FF",X"00",X"20",X"AF",X"FF",X"01",X"10",X"01",X"FF", + X"01",X"10",X"CD",X"71",X"43",X"01",X"FF",X"00",X"10",X"CD",X"7B",X"43",X"C3",X"E4",X"42",X"A0", + X"80",X"01",X"1C",X"02",X"05",X"66",X"01",X"FD",X"00",X"30",X"76",X"90",X"8A",X"01",X"1C",X"02", + X"05",X"66",X"C3",X"26",X"43",X"60",X"60",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"50", + X"58",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"40",X"40",X"01",X"1C",X"02",X"05",X"66", + X"C3",X"26",X"43",X"30",X"4A",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"A0",X"60",X"01", + X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"90",X"6A",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26", + X"43",X"50",X"80",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"38",X"70",X"01",X"1C",X"02", + X"05",X"66",X"C3",X"26",X"43",X"D0",X"A0",X"9B",X"18",X"02",X"0F",X"30",X"CD",X"C8",X"43",X"01", + X"FF",X"00",X"10",X"CD",X"FE",X"43",X"01",X"FF",X"00",X"10",X"CD",X"08",X"44",X"01",X"FF",X"00", + X"10",X"AF",X"FF",X"00",X"10",X"01",X"FF",X"01",X"10",X"CD",X"12",X"44",X"01",X"FF",X"01",X"10", + X"CD",X"1C",X"44",X"01",X"FF",X"01",X"08",X"AF",X"FF",X"01",X"10",X"01",X"FF",X"01",X"08",X"CD", + X"26",X"44",X"CD",X"30",X"44",X"C3",X"E4",X"42",X"D0",X"C0",X"9B",X"18",X"02",X"0F",X"30",X"AF", + X"00",X"00",X"50",X"01",X"FF",X"00",X"10",X"CD",X"3A",X"44",X"01",X"FF",X"00",X"10",X"CD",X"44", + X"44",X"01",X"FF",X"FF",X"10",X"AF",X"FF",X"00",X"10",X"01",X"FF",X"01",X"10",X"01",X"FF",X"FF", + X"10",X"CD",X"4E",X"44",X"01",X"FF",X"FF",X"10",X"CD",X"58",X"44",X"C3",X"E4",X"42",X"A0",X"A0", + X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"A0",X"AA",X"01",X"1C",X"02",X"05",X"66",X"C3", + X"26",X"43",X"60",X"C0",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"60",X"CA",X"01",X"1C", + X"02",X"05",X"66",X"C3",X"26",X"43",X"40",X"E0",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43", + X"40",X"EA",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"A0",X"C0",X"01",X"1C",X"02",X"05", + X"66",X"C3",X"26",X"43",X"A0",X"CA",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"50",X"A0", + X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"50",X"AA",X"01",X"1C",X"02",X"05",X"66",X"C3", + X"26",X"43",X"D0",X"40",X"1B",X"18",X"02",X"0F",X"02",X"CD",X"AB",X"44",X"01",X"FE",X"00",X"12", + X"01",X"FE",X"01",X"04",X"EB",X"6A",X"1F",X"02",X"0B",X"10",X"01",X"FE",X"01",X"04",X"01",X"FE", + X"01",X"04",X"EB",X"7E",X"4E",X"02",X"07",X"20",X"01",X"FE",X"01",X"04",X"AF",X"00",X"04",X"01", + X"EB",X"8E",X"4E",X"02",X"07",X"30",X"01",X"FE",X"02",X"03",X"01",X"FE",X"01",X"03",X"01",X"FE", + X"00",X"08",X"01",X"FE",X"FF",X"08",X"01",X"FE",X"FE",X"30",X"76",X"D0",X"44",X"1B",X"18",X"02", + X"0F",X"02",X"AF",X"00",X"00",X"20",X"CD",X"BC",X"44",X"C3",X"6C",X"44",X"D0",X"38",X"1B",X"18", + X"02",X"0F",X"02",X"AF",X"00",X"00",X"20",X"C3",X"6C",X"44",X"D0",X"80",X"1B",X"18",X"02",X"0F", + X"02",X"CD",X"D7",X"44",X"C3",X"6C",X"44",X"D0",X"84",X"1B",X"18",X"02",X"0F",X"02",X"AF",X"00", + X"00",X"20",X"CD",X"E8",X"44",X"C3",X"6C",X"44",X"D0",X"78",X"1B",X"18",X"02",X"0F",X"02",X"AF", + X"00",X"00",X"20",X"C3",X"6C",X"44",X"D0",X"C0",X"1B",X"18",X"02",X"0F",X"02",X"CD",X"03",X"45", + X"C3",X"6C",X"44",X"D0",X"C4",X"1B",X"18",X"02",X"0F",X"02",X"AF",X"00",X"00",X"20",X"CD",X"14", + X"45",X"C3",X"6C",X"44",X"D0",X"B8",X"1B",X"18",X"02",X"0F",X"02",X"AF",X"00",X"00",X"20",X"C3", + X"6C",X"44",X"D0",X"30",X"9E",X"4E",X"02",X"05",X"20",X"CD",X"79",X"45",X"CD",X"87",X"45",X"CD", + X"95",X"45",X"01",X"FF",X"01",X"10",X"EB",X"AA",X"4E",X"02",X"07",X"20",X"01",X"FF",X"01",X"08", + X"EB",X"BA",X"4E",X"02",X"09",X"20",X"01",X"FE",X"01",X"08",X"EB",X"CE",X"4E",X"02",X"0B",X"20", + X"01",X"FE",X"01",X"04",X"EB",X"E6",X"4E",X"02",X"0D",X"20",X"01",X"FE",X"01",X"02",X"EB",X"DB", + X"17",X"02",X"0F",X"20",X"01",X"FE",X"00",X"08",X"AF",X"FE",X"FF",X"08",X"01",X"FD",X"FF",X"08", + X"01",X"FE",X"01",X"10",X"01",X"FD",X"01",X"16",X"76",X"D0",X"50",X"9E",X"4E",X"02",X"05",X"20", + X"01",X"00",X"00",X"08",X"C3",X"32",X"45",X"D0",X"70",X"9E",X"4E",X"02",X"05",X"20",X"01",X"00", + X"00",X"10",X"C3",X"32",X"45",X"D0",X"90",X"9E",X"4E",X"02",X"05",X"20",X"01",X"00",X"00",X"18", + X"C3",X"32",X"45",X"D0",X"30",X"9E",X"4E",X"02",X"05",X"20",X"CD",X"BA",X"45",X"CD",X"C8",X"45", + X"CD",X"D6",X"45",X"AF",X"00",X"00",X"20",X"C3",X"32",X"45",X"D0",X"50",X"9E",X"4E",X"02",X"05", + X"20",X"AF",X"00",X"00",X"28",X"C3",X"32",X"45",X"D0",X"70",X"9E",X"4E",X"02",X"05",X"20",X"AF", + X"00",X"00",X"30",X"C3",X"32",X"45",X"D0",X"90",X"9E",X"4E",X"02",X"05",X"20",X"AF",X"00",X"00", + X"38",X"C3",X"32",X"45",X"C0",X"BD",X"23",X"1B",X"02",X"28",X"40",X"01",X"FF",X"FF",X"41",X"CD", + X"F7",X"45",X"01",X"00",X"00",X"FF",X"76",X"77",X"8C",X"75",X"1B",X"01",X"0B",X"40",X"CD",X"06", + X"46",X"01",X"00",X"00",X"FF",X"76",X"23",X"90",X"82",X"1B",X"0B",X"01",X"40",X"CD",X"15",X"46", + X"01",X"00",X"00",X"FF",X"76",X"23",X"92",X"82",X"1B",X"0B",X"01",X"40",X"01",X"00",X"00",X"FF", + X"76",X"C0",X"F0",X"8F",X"19",X"05",X"28",X"70",X"01",X"FD",X"FD",X"40",X"76",X"80",X"B0",X"82", + X"1F",X"02",X"11",X"38",X"01",X"00",X"00",X"01",X"CD",X"82",X"47",X"CD",X"8E",X"47",X"CD",X"98", + X"47",X"CD",X"A4",X"47",X"CD",X"AE",X"47",X"AF",X"00",X"FE",X"04",X"CD",X"B8",X"47",X"01",X"00", + X"FE",X"04",X"CD",X"C2",X"47",X"01",X"00",X"FE",X"04",X"CD",X"CC",X"47",X"AF",X"00",X"FE",X"04", + X"CD",X"D6",X"47",X"01",X"00",X"FE",X"04",X"CD",X"E0",X"47",X"01",X"00",X"FE",X"04",X"CD",X"EA", + X"47",X"AF",X"00",X"FF",X"08",X"CD",X"F4",X"47",X"01",X"00",X"FE",X"04",X"CD",X"FE",X"47",X"01", + X"00",X"FE",X"04",X"CD",X"08",X"48",X"01",X"00",X"FF",X"08",X"CD",X"12",X"48",X"CD",X"1C",X"48", + X"AF",X"00",X"FE",X"04",X"CD",X"26",X"48",X"01",X"00",X"FE",X"04",X"CD",X"30",X"48",X"01",X"00", + X"FE",X"04",X"CD",X"3A",X"48",X"01",X"00",X"FE",X"04",X"CD",X"44",X"48",X"01",X"00",X"FE",X"04", + X"CD",X"4E",X"48",X"01",X"00",X"FE",X"04",X"CD",X"58",X"48",X"01",X"00",X"FE",X"04",X"CD",X"62", + X"48",X"01",X"00",X"02",X"04",X"CD",X"6C",X"48",X"AF",X"00",X"02",X"04",X"CD",X"76",X"48",X"01", + X"00",X"02",X"04",X"CD",X"80",X"48",X"AF",X"00",X"02",X"04",X"CD",X"30",X"48",X"01",X"00",X"02", + X"04",X"CD",X"8A",X"48",X"01",X"00",X"01",X"08",X"CD",X"94",X"48",X"AF",X"00",X"01",X"08",X"CD", + X"1C",X"48",X"01",X"00",X"02",X"04",X"CD",X"9E",X"48",X"01",X"00",X"02",X"04",X"CD",X"F4",X"47", + X"AF",X"00",X"02",X"04",X"CD",X"A8",X"48",X"01",X"00",X"02",X"04",X"CD",X"B2",X"48",X"01",X"00", + X"02",X"04",X"CD",X"D6",X"47",X"01",X"00",X"02",X"04",X"CD",X"BC",X"48",X"01",X"00",X"02",X"04", + X"CD",X"C6",X"48",X"AF",X"00",X"02",X"04",X"CD",X"D0",X"48",X"01",X"00",X"02",X"04",X"CD",X"8E", + X"47",X"01",X"00",X"02",X"04",X"CD",X"DA",X"48",X"01",X"00",X"02",X"04",X"CD",X"AE",X"47",X"AF", + X"00",X"02",X"04",X"CD",X"E4",X"48",X"01",X"00",X"02",X"04",X"CD",X"EE",X"48",X"01",X"00",X"02", + X"04",X"CD",X"F8",X"48",X"01",X"00",X"01",X"08",X"CD",X"02",X"49",X"01",X"00",X"02",X"08",X"CD", + X"0C",X"49",X"01",X"00",X"FE",X"08",X"CD",X"16",X"49",X"01",X"00",X"FE",X"04",X"CD",X"20",X"49", + X"01",X"00",X"FE",X"04",X"CD",X"2A",X"49",X"AF",X"00",X"FE",X"0C",X"01",X"00",X"FE",X"04",X"C3", + X"34",X"46",X"70",X"AC",X"66",X"1F",X"02",X"01",X"64",X"01",X"FC",X"00",X"18",X"76",X"70",X"B2", + X"66",X"1F",X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"B6",X"01",X"1C",X"02",X"05",X"66",X"01", + X"FD",X"00",X"20",X"76",X"70",X"BE",X"66",X"1F",X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"C4", + X"66",X"1F",X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"AA",X"01",X"1C",X"02",X"05",X"66",X"C3", + X"9F",X"47",X"70",X"A2",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"9A",X"01",X"1C", + X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"94",X"66",X"1F",X"02",X"01",X"64",X"C3",X"89",X"47", + X"70",X"8A",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"82",X"01",X"1C",X"02",X"05", + X"66",X"C3",X"9F",X"47",X"70",X"7C",X"66",X"1F",X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"72"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/roms/mw06.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/roms/mw06.vhd new file mode 100644 index 00000000..dc5691b4 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/roms/mw06.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity mw06 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of mw06 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"6A",X"01",X"1C",X"02",X"05",X"66",X"C3", + X"9F",X"47",X"70",X"60",X"66",X"1F",X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"6C",X"66",X"1F", + X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"5A",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47", + X"70",X"54",X"66",X"1F",X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"4A",X"01",X"1C",X"02",X"05", + X"66",X"C3",X"9F",X"47",X"70",X"42",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"3A", + X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"32",X"01",X"1C",X"02",X"05",X"66",X"C3", + X"9F",X"47",X"70",X"2C",X"66",X"1F",X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"3B",X"01",X"1C", + X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"43",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47", + X"70",X"4B",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"5B",X"01",X"1C",X"02",X"05", + X"66",X"C3",X"9F",X"47",X"70",X"63",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"73", + X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"83",X"01",X"1C",X"02",X"05",X"66",X"C3", + X"9F",X"47",X"70",X"8B",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"9B",X"01",X"1C", + X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"A3",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47", + X"70",X"AB",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"BB",X"01",X"1C",X"02",X"05", + X"66",X"C3",X"9F",X"47",X"70",X"CB",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"D3", + X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"DB",X"01",X"1C",X"02",X"05",X"66",X"C3", + X"9F",X"47",X"70",X"E3",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"E8",X"66",X"1F", + X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"CA",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47", + X"70",X"C2",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"BA",X"01",X"1C",X"02",X"05", + X"66",X"C3",X"9F",X"47",X"D0",X"60",X"1B",X"18",X"02",X"0F",X"02",X"CD",X"62",X"44",X"01",X"FE", + X"00",X"10",X"AF",X"00",X"04",X"01",X"EB",X"6A",X"1F",X"02",X"0B",X"10",X"01",X"FE",X"01",X"08", + X"AF",X"00",X"04",X"01",X"EB",X"7E",X"4E",X"02",X"07",X"20",X"01",X"FE",X"01",X"04",X"AF",X"00", + X"04",X"01",X"EB",X"8E",X"4E",X"02",X"07",X"30",X"01",X"FE",X"02",X"04",X"01",X"FE",X"01",X"03", + X"CD",X"83",X"49",X"01",X"FE",X"00",X"08",X"01",X"FE",X"FF",X"04",X"CD",X"8F",X"49",X"01",X"FE", + X"FE",X"20",X"76",X"7A",X"78",X"4A",X"1F",X"01",X"05",X"66",X"01",X"FD",X"00",X"20",X"76",X"62", + X"74",X"4A",X"1F",X"01",X"05",X"66",X"C3",X"8A",X"49",X"D0",X"A0",X"1B",X"18",X"02",X"0F",X"02", + X"CD",X"CA",X"44",X"CD",X"F6",X"44",X"01",X"FE",X"00",X"10",X"AF",X"00",X"04",X"01",X"EB",X"6A", + X"1F",X"02",X"0B",X"10",X"01",X"FE",X"01",X"08",X"AF",X"00",X"04",X"01",X"EB",X"7E",X"4E",X"02", + X"07",X"20",X"01",X"FE",X"01",X"04",X"AF",X"00",X"04",X"01",X"EB",X"8E",X"4E",X"02",X"07",X"30", + X"01",X"FE",X"02",X"03",X"CD",X"E9",X"49",X"01",X"FE",X"01",X"04",X"01",X"FE",X"00",X"04",X"CD", + X"F3",X"49",X"01",X"FE",X"00",X"04",X"C3",X"A2",X"44",X"82",X"73",X"4A",X"1F",X"01",X"05",X"66", + X"C3",X"8A",X"49",X"72",X"67",X"4A",X"1F",X"01",X"05",X"66",X"C3",X"8A",X"49",X"D0",X"78",X"DB", + X"18",X"02",X"0F",X"33",X"CD",X"61",X"4A",X"01",X"FF",X"00",X"10",X"CD",X"3F",X"4A",X"01",X"FF", + X"00",X"10",X"01",X"FF",X"01",X"11",X"01",X"FE",X"FF",X"08",X"01",X"FD",X"FF",X"05",X"AF",X"F0", + X"FF",X"02",X"01",X"00",X"00",X"04",X"CD",X"4B",X"4A",X"CD",X"57",X"4A",X"01",X"00",X"00",X"12", + X"CD",X"4B",X"4A",X"CD",X"57",X"4A",X"01",X"FE",X"00",X"10",X"01",X"FD",X"FF",X"10",X"76",X"B8", + X"7F",X"4A",X"1F",X"01",X"05",X"66",X"01",X"FD",X"00",X"40",X"76",X"50",X"7A",X"66",X"1F",X"02", + X"01",X"64",X"01",X"FC",X"00",X"10",X"76",X"50",X"84",X"66",X"1F",X"02",X"01",X"64",X"C3",X"52", + X"4A",X"D0",X"48",X"1B",X"19",X"02",X"0F",X"33",X"AF",X"00",X"00",X"10",X"CD",X"DF",X"4A",X"01", + X"FF",X"00",X"10",X"CD",X"AB",X"4A",X"01",X"FF",X"00",X"11",X"01",X"FE",X"00",X"08",X"01",X"FD", + X"00",X"05",X"AF",X"F0",X"00",X"02",X"01",X"00",X"00",X"06",X"CD",X"B5",X"4A",X"CD",X"C1",X"4A", + X"01",X"00",X"00",X"06",X"CD",X"B5",X"4A",X"CD",X"C1",X"4A",X"01",X"FE",X"00",X"08",X"CD",X"CB", + X"4A",X"CD",X"D5",X"4A",X"01",X"00",X"00",X"10",X"C3",X"9E",X"4A",X"B8",X"4F",X"4A",X"1F",X"01", + X"05",X"66",X"C3",X"46",X"4A",X"60",X"48",X"40",X"1F",X"01",X"03",X"64",X"01",X"FE",X"00",X"30", + X"76",X"60",X"54",X"40",X"1F",X"01",X"03",X"64",X"C3",X"BC",X"4A",X"50",X"48",X"40",X"1F",X"01", + X"03",X"64",X"C3",X"BC",X"4A",X"50",X"54",X"40",X"1F",X"01",X"03",X"64",X"C3",X"BC",X"4A",X"D0", + X"78",X"DB",X"18",X"02",X"0F",X"33",X"AF",X"00",X"00",X"10",X"01",X"FF",X"00",X"11",X"01",X"FE", + X"00",X"08",X"01",X"FD",X"00",X"05",X"AF",X"F0",X"00",X"02",X"01",X"00",X"00",X"10",X"01",X"FE", + X"00",X"09",X"01",X"FD",X"00",X"06",X"CD",X"13",X"4B",X"CD",X"1D",X"4B",X"01",X"00",X"00",X"10", + X"C3",X"06",X"4B",X"40",X"79",X"66",X"1F",X"02",X"01",X"64",X"C3",X"52",X"4A",X"40",X"83",X"66", + X"1F",X"02",X"01",X"64",X"C3",X"52",X"4A",X"D0",X"A8",X"FB",X"18",X"02",X"0F",X"33",X"CD",X"87", + X"4B",X"01",X"FF",X"00",X"18",X"CD",X"69",X"4B",X"01",X"FF",X"00",X"08",X"01",X"FF",X"01",X"11", + X"01",X"FE",X"FF",X"08",X"01",X"FD",X"FF",X"05",X"AF",X"F0",X"FF",X"02",X"01",X"00",X"00",X"02", + X"CD",X"73",X"4B",X"CD",X"7D",X"4B",X"01",X"00",X"00",X"0E",X"CD",X"73",X"4B",X"CD",X"7D",X"4B", + X"01",X"FE",X"00",X"10",X"01",X"FD",X"01",X"10",X"76",X"B0",X"AF",X"4A",X"1F",X"01",X"05",X"66", + X"C3",X"46",X"4A",X"50",X"AA",X"66",X"1F",X"02",X"01",X"64",X"C3",X"52",X"4A",X"50",X"B4",X"66", + X"1F",X"02",X"01",X"64",X"C3",X"52",X"4A",X"D0",X"D8",X"DB",X"18",X"02",X"0F",X"33",X"AF",X"00", + X"00",X"10",X"CD",X"03",X"4C",X"01",X"FF",X"00",X"18",X"CD",X"D1",X"4B",X"01",X"FF",X"00",X"09", + X"01",X"FE",X"00",X"08",X"01",X"FD",X"00",X"05",X"AF",X"F0",X"00",X"02",X"01",X"00",X"00",X"04", + X"CD",X"DB",X"4B",X"CD",X"E5",X"4B",X"01",X"00",X"00",X"08",X"CD",X"DB",X"4B",X"CD",X"E5",X"4B", + X"01",X"FE",X"00",X"08",X"CD",X"EF",X"4B",X"CD",X"F9",X"4B",X"01",X"00",X"00",X"10",X"C3",X"C4", + X"4B",X"B0",X"DF",X"4A",X"1F",X"01",X"05",X"66",X"C3",X"46",X"4A",X"60",X"D8",X"40",X"1F",X"01", + X"03",X"64",X"C3",X"BC",X"4A",X"60",X"E4",X"40",X"1F",X"01",X"03",X"64",X"C3",X"BC",X"4A",X"50", + X"D8",X"40",X"1F",X"01",X"03",X"64",X"C3",X"BC",X"4A",X"50",X"E4",X"40",X"1F",X"01",X"03",X"64", + X"C3",X"BC",X"4A",X"D0",X"A8",X"FB",X"18",X"02",X"0F",X"33",X"AF",X"00",X"00",X"10",X"01",X"FF", + X"00",X"11",X"01",X"FE",X"00",X"08",X"01",X"FD",X"00",X"05",X"AF",X"F0",X"00",X"02",X"01",X"00", + X"00",X"10",X"01",X"FE",X"00",X"09",X"01",X"FD",X"00",X"06",X"01",X"00",X"00",X"04",X"CD",X"3B", + X"4C",X"CD",X"45",X"4C",X"01",X"00",X"00",X"10",X"C3",X"2A",X"4C",X"40",X"A9",X"66",X"1F",X"02", + X"01",X"64",X"C3",X"52",X"4A",X"40",X"B3",X"66",X"1F",X"03",X"01",X"64",X"C3",X"52",X"4A",X"C0", + X"8C",X"C5",X"1B",X"02",X"0E",X"3F",X"00",X"00",X"00",X"CD",X"6C",X"4C",X"CD",X"88",X"4C",X"CD", + X"9A",X"4C",X"CD",X"B0",X"4C",X"01",X"00",X"00",X"20",X"C3",X"56",X"4C",X"AA",X"8A",X"AD",X"1B", + X"01",X"0A",X"08",X"01",X"FE",X"00",X"08",X"01",X"FE",X"00",X"18",X"01",X"FE",X"01",X"10",X"01", + X"FD",X"FE",X"10",X"01",X"FC",X"02",X"10",X"76",X"AA",X"92",X"AD",X"1B",X"01",X"0A",X"08",X"01", + X"FE",X"00",X"08",X"01",X"FE",X"00",X"18",X"C3",X"7B",X"4C",X"B4",X"8A",X"AD",X"1B",X"01",X"0A", + X"08",X"01",X"FE",X"00",X"08",X"01",X"FE",X"FE",X"0C",X"01",X"FE",X"01",X"04",X"C3",X"7B",X"4C", + X"B4",X"92",X"AD",X"1B",X"01",X"0A",X"08",X"01",X"FE",X"00",X"08",X"CD",X"D2",X"4C",X"CD",X"E4", + X"4C",X"CD",X"F6",X"4C",X"CD",X"04",X"4D",X"01",X"FE",X"02",X"14",X"01",X"FE",X"00",X"04",X"C3", + X"7B",X"4C",X"AE",X"8A",X"AD",X"1B",X"01",X"0A",X"08",X"01",X"FE",X"FE",X"11",X"01",X"FE",X"01", + X"0E",X"C3",X"7B",X"4C",X"AE",X"92",X"AD",X"1B",X"01",X"0A",X"08",X"01",X"FE",X"02",X"18",X"01", + X"FE",X"01",X"08",X"C3",X"7B",X"4C",X"B8",X"8A",X"AD",X"1B",X"01",X"0A",X"08",X"01",X"FE",X"FE", + X"24",X"C3",X"7B",X"4C",X"B8",X"92",X"AD",X"1B",X"01",X"0A",X"08",X"01",X"FE",X"02",X"24",X"C3", + X"7B",X"4C",X"3E",X"01",X"F7",X"0A",X"C3",X"E3",X"0F",X"E1",X"C3",X"E3",X"0F",X"76",X"1E",X"4D", + X"00",X"00",X"1E",X"0C",X"3F",X"0C",X"1E",X"00",X"00",X"29",X"4D",X"00",X"00",X"00",X"00",X"F0", + X"00",X"60",X"00",X"F8",X"01",X"7E",X"00",X"FC",X"00",X"3F",X"00",X"FC",X"00",X"7E",X"00",X"F8", + X"01",X"60",X"00",X"F0",X"00",X"00",X"00",X"00",X"00",X"D0",X"48",X"29",X"4D",X"02",X"0F",X"12", + X"CD",X"9C",X"4D",X"CD",X"D3",X"4D",X"CD",X"0A",X"4E",X"01",X"FE",X"FE",X"10",X"01",X"FE",X"02", + X"10",X"CD",X"76",X"4D",X"CD",X"80",X"4D",X"CD",X"8E",X"4D",X"76",X"01",X"FE",X"FE",X"10",X"01", + X"FE",X"02",X"10",X"C3",X"6B",X"4D",X"90",X"4B",X"1E",X"4D",X"01",X"09",X"22",X"C3",X"6B",X"4D", + X"93",X"48",X"1E",X"4D",X"01",X"09",X"22",X"01",X"FF",X"FE",X"10",X"C3",X"6B",X"4D",X"93",X"4E", + X"1E",X"4D",X"01",X"09",X"22",X"01",X"FF",X"02",X"08",X"C3",X"6B",X"4D",X"D0",X"78",X"29",X"4D", + X"02",X"0F",X"12",X"01",X"FE",X"FE",X"10",X"01",X"FE",X"02",X"10",X"CD",X"B5",X"4D",X"CD",X"BF", + X"4D",X"CD",X"C9",X"4D",X"76",X"90",X"7B",X"1E",X"4D",X"01",X"09",X"22",X"C3",X"6B",X"4D",X"93", + X"78",X"1E",X"4D",X"01",X"09",X"22",X"C3",X"87",X"4D",X"93",X"7E",X"1E",X"4D",X"01",X"09",X"22", + X"C3",X"95",X"4D",X"D0",X"B8",X"29",X"4D",X"02",X"0F",X"12",X"01",X"FE",X"FE",X"10",X"01",X"FE", + X"02",X"10",X"CD",X"EC",X"4D",X"CD",X"F6",X"4D",X"CD",X"00",X"4E",X"76",X"90",X"BB",X"1E",X"4D", + X"01",X"09",X"22",X"C3",X"6B",X"4D",X"93",X"B8",X"1E",X"4D",X"01",X"09",X"22",X"C3",X"87",X"4D", + X"93",X"BE",X"1E",X"4D",X"01",X"09",X"22",X"C3",X"95",X"4D",X"D0",X"E8",X"29",X"4D",X"02",X"0F", + X"12",X"01",X"FE",X"FE",X"10",X"01",X"FF",X"02",X"10",X"CD",X"23",X"4E",X"CD",X"2D",X"4E",X"CD", + X"37",X"4E",X"76",X"90",X"EB",X"1E",X"4D",X"01",X"09",X"22",X"C3",X"6B",X"4D",X"93",X"E8",X"1E", + X"4D",X"01",X"09",X"22",X"C3",X"87",X"4D",X"93",X"EE",X"1E",X"4D",X"01",X"09",X"22",X"C3",X"95", + X"4D",X"D0",X"88",X"DB",X"18",X"02",X"0F",X"33",X"CD",X"49",X"4D",X"AF",X"00",X"00",X"20",X"CD", + X"49",X"4D",X"01",X"00",X"00",X"04",X"AF",X"00",X"04",X"02",X"01",X"00",X"00",X"04",X"AF",X"00", + X"FC",X"02",X"01",X"00",X"00",X"04",X"C3",X"4F",X"4E",X"D0",X"10",X"AD",X"1B",X"01",X"0A",X"08", + X"CD",X"49",X"4D",X"AF",X"00",X"00",X"10",X"CD",X"FD",X"49",X"CD",X"27",X"4B",X"76",X"7E",X"4E", + X"00",X"00",X"E0",X"1F",X"78",X"7C",X"FF",X"7F",X"FC",X"3F",X"F0",X"1F",X"00",X"00",X"8E",X"4E", + X"00",X"00",X"00",X"00",X"C0",X"0F",X"FE",X"7F",X"E0",X"0F",X"00",X"00",X"00",X"00",X"9E",X"4E", + X"00",X"00",X"40",X"00",X"E0",X"00",X"40",X"00",X"00",X"00",X"AA",X"4E",X"00",X"00",X"E0",X"00", + X"F0",X"01",X"B0",X"01",X"F0",X"01",X"E0",X"00",X"00",X"00",X"BA",X"4E",X"00",X"00",X"E0",X"00", + X"50",X"01",X"E8",X"02",X"B8",X"03",X"E8",X"02",X"50",X"01",X"E0",X"00",X"00",X"00",X"CE",X"4E", + X"00",X"00",X"B0",X"01",X"F8",X"03",X"EC",X"06",X"B4",X"05",X"58",X"03",X"B4",X"05",X"EC",X"06", + X"F8",X"03",X"B0",X"01",X"00",X"00",X"E6",X"4E",X"00",X"00",X"B0",X"01",X"F8",X"03",X"5C",X"07", + X"AE",X"0E",X"56",X"0D",X"F8",X"03",X"56",X"0D",X"AE",X"0E",X"5C",X"07",X"F8",X"03",X"B0",X"01", + X"00",X"00",X"C0",X"04",X"00",X"00",X"00",X"10",X"C6",X"00",X"00",X"00",X"6C",X"29",X"10",X"01", + X"00",X"16",X"04",X"06",X"11",X"00",X"6E",X"C9",X"00",X"00",X"00",X"34",X"C2",X"05",X"90",X"00", + X"DF",X"08",X"02",X"00",X"00",X"CC",X"25",X"08",X"02",X"10",X"BA",X"43",X"92",X"80",X"00",X"A1", + X"4C",X"08",X"21",X"02",X"2F",X"2B",X"31",X"04",X"10",X"D0",X"6A",X"04",X"81",X"20",X"0A",X"95", + X"02",X"10",X"02",X"A0",X"A8",X"45",X"01",X"04",X"10",X"51",X"00",X"92",X"00",X"01",X"44",X"06", + X"20",X"01",X"36",X"92",X"44",X"42",X"00",X"C2",X"A0",X"91",X"04",X"00",X"00",X"10",X"03",X"01", + X"02",X"28",X"08",X"0C",X"20",X"00",X"80",X"92",X"02",X"41",X"08",X"04",X"00",X"25",X"90",X"00", + X"50",X"05",X"4A",X"24",X"00",X"00",X"20",X"D4",X"48",X"00",X"8A",X"42",X"80",X"81",X"42",X"02", + X"10",X"00",X"21",X"04",X"40",X"01",X"20",X"02",X"08",X"04",X"48",X"44",X"00",X"00",X"20",X"10", + X"88",X"00",X"00",X"00",X"04",X"10",X"10",X"01",X"10",X"01",X"21",X"00",X"20",X"28",X"08",X"00", + X"40",X"44",X"80",X"00",X"04",X"02",X"00",X"00",X"14",X"00",X"04",X"00",X"20",X"20",X"01",X"09", + X"00",X"00",X"02",X"02",X"00",X"08",X"00",X"01",X"20",X"00",X"00",X"40",X"80",X"00",X"00",X"20", + X"00",X"10",X"80",X"00",X"40",X"00",X"20",X"00",X"00",X"80",X"FF",X"FF",X"07",X"07",X"07",X"07", + X"07",X"07",X"07",X"07",X"07",X"02",X"03",X"04",X"05",X"06",X"12",X"2D",X"0A",X"00",X"0E",X"17", + X"0E",X"1B",X"10",X"22",X"2E",X"18",X"1E",X"1D",X"00",X"3E",X"09",X"CD",X"05",X"0A",X"E1",X"D1", + X"C3",X"12",X"4D",X"3E",X"E1",X"C3",X"EB",X"4F",X"F7",X"0A",X"F7",X"0C",X"AF",X"E7",X"0B",X"C9"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/spram.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/spram.vhd new file mode 100644 index 00000000..d8043481 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/spram.vhd @@ -0,0 +1,55 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY spram IS + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clken : IN STD_LOGIC := '1'; + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END spram; + + +ARCHITECTURE SYN OF spram IS + +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "NORMAL", + clock_enable_output_a => "BYPASS", + intended_device_family => "Cyclone III", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + width_a => data_width_g, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + clocken0 => clken, + data_a => data, + wren_a => wren, + q_a => q + ); + + + +END SYN; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/sprom.vhd new file mode 100644 index 00000000..a81ac959 --- /dev/null +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/sprom.vhd @@ -0,0 +1,82 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY sprom IS + GENERIC + ( + init_file : string := ""; + widthad_a : natural; + width_a : natural := 8; + outdata_reg_a : string := "UNREGISTERED" + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); +END sprom; + + +ARCHITECTURE SYN OF sprom IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + address_aclr_a : STRING; + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + clock0 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(width_a-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_aclr_a => "NONE", + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => init_file, + intended_device_family => "Cyclone III", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2**widthad_a, + operation_mode => "ROM", + outdata_aclr_a => "NONE", + outdata_reg_a => outdata_reg_a, + widthad_a => widthad_a, + width_a => width_a, + width_byteena_a => 1 + ) + PORT MAP ( + clock0 => clock, + address_a => address, + q_a => sub_wire0 + ); + + + +END SYN; diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/SpaceWalk_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/SpaceWalk_MiST/rtl/invaders.vhd index 56e9bbe9..84a21f33 100644 --- a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/SpaceWalk_MiST/rtl/invaders.vhd +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/SpaceWalk_MiST/rtl/invaders.vhd @@ -198,32 +198,32 @@ begin GDB2 when "10", S when others; - GDB0(0) <= '1';--DIP(8); -- Unused ? - GDB0(1) <= '1';--DIP(7); - GDB0(2) <= '1';--DIP(6); -- Unused ? - GDB0(3) <= '1'; -- Unused ? - GDB0(4) <= not Fire; - GDB0(5) <= not MoveLeft; - GDB0(6) <= not MoveRight; - GDB0(7) <= '1';--DIP(5); -- Unused ? + GDB0(0) <= '0';-- + GDB0(1) <= '1';-- + GDB0(2) <= '1';-- + GDB0(3) <= '1';-- + GDB0(4) <= '1';-- + GDB0(5) <= '1';-- + GDB0(6) <= '1';-- + GDB0(7) <= '1';-- - GDB1(0) <= not Coin;-- Active High ! - GDB1(1) <= not Sel2Player; - GDB1(2) <= not Sel1Player; - GDB1(3) <= '1';-- Unused ? - GDB1(4) <= not Fire; - GDB1(5) <= not MoveLeft; - GDB1(6) <= not MoveRight; + GDB1(0) <= '1';-- Unused ? + GDB1(1) <= '1';-- Unused ? + GDB1(2) <= '1';-- Unused ? + GDB1(2) <= '1';-- Unused ? + GDB1(4) <= not Sel2Player; + GDB1(5) <= not Sel1Player; + GDB1(6) <= not Coin; GDB1(7) <= '1';-- Unused ? - GDB2(0) <= '1';--DIP(4); -- LSB Lives 3-6 - GDB2(1) <= '1';--DIP(3); -- MSB Lives 3-6 - GDB2(2) <= '1';-- Tilt ? - GDB2(3) <= '1';--DIP(2); -- Bonus life at 1000 or 1500 - GDB2(4) <= not Fire; - GDB2(5) <= not MoveLeft; - GDB2(6) <= not MoveRight; - GDB2(7) <= '1';--DIP(1); -- Coin info + GDB2(0) <= '0';--RAM-ROM Test + GDB2(1) <= '0';--RAM-ROM Test + GDB2(2) <= '0';--Springboard Alignment + GDB2(3) <= '0';--Extended Time At + GDB2(4) <= '0';--Coinage + GDB2(5) <= '0';--Game_Time + GDB2(6) <= '0';--Game_Time + GDB2(7) <= '0';--Game_Time PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0'; PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';