diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/ReadMe.txt b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/ReadMe.txt new file mode 100644 index 00000000..eff56ba4 --- /dev/null +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/ReadMe.txt @@ -0,0 +1,19 @@ +Traverse USA by Dar (darfpga@aol.fr) (16/03/2019) + +Port to MiST + +TRAVRUSA.ROM or SHTRIDER.ROM is required at the root of the SD-Card. + +Creating in Windows: +copy /B zr1-0.m3 + zr1-5.l3 + zr1-6a.k3 + zr1-7.j3 + mr10.1a + mr10.1a + zippyrac.001 + mr8.3c + mr9.3a + zr1-8.n3 + zr1-9.l3 + zr1-10.k3 + mmi6349.ij + tbp24s10.3 + tbp18s.2 > TRAVRUSA.ROM +copy /B sr01a.bin + sr02a.bin + sr03a.bin + sr04a.bin + sr11a.bin + sr05a.bin + sr06a.bin + sr07a.bin + sr08a.bin + sr09a.bin + sr10b.bin + 1.bpr + 2.bpr + 3.bpr + 4.bpr > SHTRIDER.ROM + +Creating in Linux: +cat zr1-0.m3 zr1-5.l3 zr1-6a.k3 zr1-7.j3 mr10.1a mr10.1a zippyrac.001 mr8.3c mr9.3a zr1-8.n3 zr1-9.l3 zr1-10.k3 mmi6349.ij tbp24s10.3 tbp18s.2 > TRAVRUSA.ROM +cat sr01a.bin sr02a.bin sr03a.bin sr04a.bin sr11a.bin sr05a.bin sr06a.bin sr07a.bin sr08a.bin sr09a.bin sr10b.bin 1.bpr 2.bpr 3.bpr 4.bpr > SHTRIDER.ROM + +Some ROM files contain different names, like: +zippyrac.000 +zippyrac.005 +zippyrac.006 +zippyrac.007 diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/Release/TROPANG.ROM b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/Release/TROPANG.ROM new file mode 100644 index 00000000..3ccdd717 Binary files /dev/null and b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/Release/TROPANG.ROM differ diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel_MiST.qpf b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel_MiST.qpf new file mode 100644 index 00000000..da6c73ef --- /dev/null +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel_MiST.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "TropicalAngel_MiST" diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel_MiST.qsf b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel_MiST.qsf new file mode 100644 index 00000000..057b13fa --- /dev/null +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel_MiST.qsf @@ -0,0 +1,198 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 32-bit +# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition +# Date created = 21:22:13 June 04, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# TraverseUSA_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + +# Project-Wide Assignments +# ======================== +set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:22:13 JUNE 04, 2019" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PIN_49 -to SDRAM_A[0] +set_location_assignment PIN_44 -to SDRAM_A[1] +set_location_assignment PIN_42 -to SDRAM_A[2] +set_location_assignment PIN_39 -to SDRAM_A[3] +set_location_assignment PIN_4 -to SDRAM_A[4] +set_location_assignment PIN_6 -to SDRAM_A[5] +set_location_assignment PIN_8 -to SDRAM_A[6] +set_location_assignment PIN_10 -to SDRAM_A[7] +set_location_assignment PIN_11 -to SDRAM_A[8] +set_location_assignment PIN_28 -to SDRAM_A[9] +set_location_assignment PIN_50 -to SDRAM_A[10] +set_location_assignment PIN_30 -to SDRAM_A[11] +set_location_assignment PIN_32 -to SDRAM_A[12] +set_location_assignment PIN_83 -to SDRAM_DQ[0] +set_location_assignment PIN_79 -to SDRAM_DQ[1] +set_location_assignment PIN_77 -to SDRAM_DQ[2] +set_location_assignment PIN_76 -to SDRAM_DQ[3] +set_location_assignment PIN_72 -to SDRAM_DQ[4] +set_location_assignment PIN_71 -to SDRAM_DQ[5] +set_location_assignment PIN_69 -to SDRAM_DQ[6] +set_location_assignment PIN_68 -to SDRAM_DQ[7] +set_location_assignment PIN_86 -to SDRAM_DQ[8] +set_location_assignment PIN_87 -to SDRAM_DQ[9] +set_location_assignment PIN_98 -to SDRAM_DQ[10] +set_location_assignment PIN_99 -to SDRAM_DQ[11] +set_location_assignment PIN_100 -to SDRAM_DQ[12] +set_location_assignment PIN_101 -to SDRAM_DQ[13] +set_location_assignment PIN_103 -to SDRAM_DQ[14] +set_location_assignment PIN_104 -to SDRAM_DQ[15] +set_location_assignment PIN_58 -to SDRAM_BA[0] +set_location_assignment PIN_51 -to SDRAM_BA[1] +set_location_assignment PIN_85 -to SDRAM_DQMH +set_location_assignment PIN_67 -to SDRAM_DQML +set_location_assignment PIN_60 -to SDRAM_nRAS +set_location_assignment PIN_64 -to SDRAM_nCAS +set_location_assignment PIN_66 -to SDRAM_nWE +set_location_assignment PIN_59 -to SDRAM_nCS +set_location_assignment PIN_33 -to SDRAM_CKE +set_location_assignment PIN_43 -to SDRAM_CLK +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] + +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO + +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name TOP_LEVEL_ENTITY TraverseUSA_MiST +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON +set_global_assignment -name SYSTEMVERILOG_FILE rtl/TraverseUSA_MiST.sv +set_global_assignment -name VHDL_FILE rtl/traverse_usa.vhd +set_global_assignment -name VHDL_FILE rtl/moon_patrol_sound_board.vhd +set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd +set_global_assignment -name VHDL_FILE rtl/cpu68.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv +set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip +set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel_MiST.sdc b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel_MiST.sdc new file mode 100644 index 00000000..405fa6c6 --- /dev/null +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel_MiST.sdc @@ -0,0 +1,135 @@ +## Generated SDC file "vectrex_MiST.out.sdc" + +## Copyright (C) 1991-2013 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +## DATE "Sun Jun 24 12:53:00 2018" + +## +## DEVICE "EP3C25E144C8" +## + +# Clock constraints + +# Automatically constrain PLL and other generated clocks +derive_pll_clocks -create_base_clocks + +# Automatically calculate clock uncertainty to jitter and other effects. +derive_clock_uncertainty + +# tsu/th constraints + +# tco constraints + +# tpd constraints + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] + +#************************************************************** +# Create Generated Clock +#************************************************************** + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +#************************************************************** +# Set Input Delay +#************************************************************** + +set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] + +set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports {SDRAM_CLK}] -max 6.4 [get_ports SDRAM_DQ[*]] +set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports {SDRAM_CLK}] -min 3.2 [get_ports SDRAM_DQ[*]] + +#************************************************************** +# Set Output Delay +#************************************************************** + +set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] 1.000 [get_ports {AUDIO_L}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] 1.000 [get_ports {AUDIO_R}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}] + +set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] +set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] + +#************************************************************** +# Set Clock Groups +#************************************************************** + +set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] + +#************************************************************** +# Set False Path +#************************************************************** + +set_false_path -to [get_ports {SDRAM_CLK}] + +#************************************************************** +# Set Multicycle Path +#************************************************************** + +set_multicycle_path -to {VGA_*[*]} -setup 2 +set_multicycle_path -to {VGA_*[*]} -hold 1 + +set_multicycle_path -from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 2 +set_multicycle_path -from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 1 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/clean.bat b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/clean.bat new file mode 100644 index 00000000..c9a2cb06 --- /dev/null +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/clean.bat @@ -0,0 +1,15 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output +rmdir /s /q simulation +rmdir /s /q greybox_tmp +del PLLJ_PLLSPE_INFO.txt +del *.qws +del *.ppf +del *.qip +del *.ddb +pause diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/TraverseUSA_MiST.sv b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/TraverseUSA_MiST.sv new file mode 100644 index 00000000..6f25bfa1 --- /dev/null +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/TraverseUSA_MiST.sv @@ -0,0 +1,320 @@ +//============================================================================ +// Arcade: TraverseUSA, ShotRider +// +// DarFPGA's core ported to MiST by (C) 2019 Szombathelyi György +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module TraverseUSA_MiST( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27, + + output [12:0] SDRAM_A, + inout [15:0] SDRAM_DQ, + output SDRAM_DQML, + output SDRAM_DQMH, + output SDRAM_nWE, + output SDRAM_nCAS, + output SDRAM_nRAS, + output SDRAM_nCS, + output [1:0] SDRAM_BA, + output SDRAM_CLK, + output SDRAM_CKE +); + +`include "rtl/build_id.v" + +reg shtrider = 1; + +wire [7:0] dip1 = 8'hff; +reg [7:0] dip2 = 8'hff; + + +localparam CONF_STR = { + "TROPANG;rom;", + "O2,Rotate Controls,Off,On;", + "O34,Scanlines,Off,25%,50%,75%;", + "OA,Blending,Off,On;", + "T0,Reset;", + "V,v1.0.",`BUILD_DATE +}; + +assign LED = 1; +assign AUDIO_R = AUDIO_L; +assign SDRAM_CLK = clk_sys; +assign SDRAM_CKE = 1; + +wire clk_sys, clk_aud; +wire pll_locked; +pll_mist pll( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_sys), + .c1(clk_aud), + .locked(pll_locked) + ); + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoublerD; +wire ypbpr; +wire [10:0] ps2_key; +wire [10:0] audio; +wire hs, vs; +wire blankn; +wire [2:0] g,b; +wire [1:0] r; + +wire [14:0] cart_addr; +wire [15:0] sdram_do; +wire cart_rd; +wire [12:0] snd_addr; +wire [15:0] snd_do; + +wire ioctl_downl; +wire [7:0] ioctl_index; +wire ioctl_wr; +wire [24:0] ioctl_addr; +wire [7:0] ioctl_dout; + +/* ROM structure +00000-07FFF CPU ROM 32k zr1-0.m3 zr1-5.l3 zr1-6a.k3 zr1-7.j3 +08000-09FFF SND ROM 8k mr10.1a mr10.1a +0A000-0FFFF GFX1 24k zippyrac.001 mr8.3c mr9.3a +10000-15FFF GFX2 24k zr1-8.n3 zr1-9.l3 zr1-10.k3 +16000-161FF CHR PAL 512b mmi6349.ij +16200-162FF SPR PAL 256b tbp24s10.3 +16300-1631F SPR LUT 32b tbp18s.2 +*/ +data_io data_io ( + .clk_sys ( clk_sys ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS2 ( SPI_SS2 ), + .SPI_DI ( SPI_DI ), + .ioctl_download( ioctl_downl ), + .ioctl_index ( ioctl_index ), + .ioctl_wr ( ioctl_wr ), + .ioctl_addr ( ioctl_addr ), + .ioctl_dout ( ioctl_dout ) +); + +reg port1_req, port2_req; +sdram sdram( + .*, + .init_n ( pll_locked ), + .clk ( clk_sys ), + + // port1 used for main CPU + .port1_req ( port1_req ), + .port1_ack ( ), + .port1_a ( ioctl_addr[23:1] ), + .port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ), + .port1_we ( ioctl_downl ), + .port1_d ( {ioctl_dout, ioctl_dout} ), + .port1_q ( ), + + .cpu1_addr ( ioctl_downl ? 15'h7fff : {1'b0, cart_addr[14:1]} ), + .cpu1_q ( sdram_do ), + + // port2 for sound board + .port2_req ( port2_req ), + .port2_ack ( ), + .port2_a ( ioctl_addr[23:1] - 16'h4000 ), + .port2_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ), + .port2_we ( ioctl_downl ), + .port2_d ( {ioctl_dout, ioctl_dout} ), + .port2_q ( ), + + .snd_addr ( ioctl_downl ? 15'h7fff : {3'b000, snd_addr[12:1]} ), + .snd_q ( snd_do ) +); + +always @(posedge clk_sys) begin + reg ioctl_wr_last = 0; + + ioctl_wr_last <= ioctl_wr; + if (ioctl_downl) begin + if (~ioctl_wr_last && ioctl_wr) begin + port1_req <= ~port1_req; + port2_req <= ~port2_req; + end + end +end + +reg reset = 1; +reg rom_loaded = 0; +always @(posedge clk_sys) begin + reg ioctl_downlD; + ioctl_downlD <= ioctl_downl; + + if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1; + reset <= status[0] | buttons[1] | ~rom_loaded; +end + + +// Traverse_usa +traverse_usa traverse_usa ( + .clock_36 ( clk_sys ), + .clock_0p895 ( clk_aud ), + .reset ( reset ), + + .shtrider ( shtrider ), + + .video_r ( r ), + .video_g ( g ), + .video_b ( b ), + .video_hs ( hs ), + .video_vs ( vs ), + .video_blankn ( blankn ), + + .audio_out ( audio ), + + .dip_switch_1 ( dip1 ), + .dip_switch_2 ( dip2 ), + + .start2 ( btn_two_players ), + .start1 ( btn_one_player ), + .coin1 ( btn_coin ), + + .right1 ( m_right ), + .left1 ( m_left ), + .brake1 ( m_down ), + .accel1 ( m_up ), + + .right2 ( m_right ), + .left2 ( m_left ), + .brake2 ( m_down ), + .accel2 ( m_up ), + + .cpu_rom_addr ( cart_addr ), + .cpu_rom_do ( cart_addr[0] ? sdram_do[15:8] : sdram_do[7:0] ), + .cpu_rom_rd ( cart_rd ), + .snd_rom_addr ( snd_addr ), + .snd_rom_do ( snd_addr[0] ? snd_do[15:8] : snd_do[7:0] ), + .dl_addr ( ioctl_addr[16:0]), + .dl_data ( ioctl_dout ), + .dl_wr ( ioctl_wr ) +); + +mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video( + .clk_sys ( clk_sys ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS3 ( SPI_SS3 ), + .SPI_DI ( SPI_DI ), + .R ( blankn ? {r, r[1] } : 0 ), + .G ( blankn ? g : 0 ), + .B ( blankn ? b : 0 ), + .HSync ( hs ), + .VSync ( vs ), + .VGA_R ( VGA_R ), + .VGA_G ( VGA_G ), + .VGA_B ( VGA_B ), + .VGA_VS ( VGA_VS ), + .VGA_HS ( VGA_HS ), + .rotate ( {1'b1,status[2]} ), + .scandoubler_disable( scandoublerD ), + .scanlines ( status[4:3] ), + .ypbpr ( ypbpr ), + .ce_divider ( 1'b0 ), + .blend ( status[10] ) + ); + +user_io #( + .STRLEN(($size(CONF_STR)>>3))) +user_io( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable (scandoublerD ), + .ypbpr (ypbpr ), + .key_strobe (key_strobe ), + .key_pressed (key_pressed ), + .key_code (key_code ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) + ); + +dac #( + .C_bits(11)) +dac( + .clk_i(clk_aud), + .res_n_i(~reset), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +// Rotated Normal +wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3]; +wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2]; +wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1]; +wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0]; +wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; +wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; + +reg btn_one_player = 0; +reg btn_two_players = 0; +reg btn_left = 0; +reg btn_right = 0; +reg btn_down = 0; +reg btn_up = 0; +reg btn_fire1 = 0; +reg btn_fire2 = 0; +reg btn_fire3 = 0; +reg btn_coin = 0; +wire key_pressed; +wire [7:0] key_code; +wire key_strobe; + +always @(posedge clk_sys) begin + if(key_strobe) begin + case(key_code) + 'h75: btn_up <= key_pressed; // up + 'h72: btn_down <= key_pressed; // down + 'h6B: btn_left <= key_pressed; // left + 'h74: btn_right <= key_pressed; // right + 'h76: btn_coin <= key_pressed; // ESC + 'h05: btn_one_player <= key_pressed; // F1 + 'h06: btn_two_players <= key_pressed; // F2 + 'h14: btn_fire3 <= key_pressed; // ctrl + 'h11: btn_fire2 <= key_pressed; // alt + 'h29: btn_fire1 <= key_pressed; // Space + endcase + end +end + +endmodule diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/YM2149.sv b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/YM2149.sv new file mode 100644 index 00000000..eae73bb3 --- /dev/null +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/YM2149.sv @@ -0,0 +1,329 @@ +// +// Copyright (c) MikeJ - Jan 2005 +// Copyright (c) 2016-2018 Sorgelig +// +// All rights reserved +// +// Redistribution and use in source and synthezised forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// Redistributions in synthesized form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// Neither the name of the author nor the names of other contributors may +// be used to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// + + +// BDIR BC MODE +// 0 0 inactive +// 0 1 read value +// 1 0 write value +// 1 1 set address +// + +module YM2149 +( + input CLK, // Global clock + input CE, // PSG Clock enable + input RESET, // Chip RESET (set all Registers to '0', active hi) + input BDIR, // Bus Direction (0 - read , 1 - write) + input BC, // Bus control + input A8, + input A9_L, + input [7:0] DI, // Data In + output [7:0] DO, // Data Out + output [7:0] CHANNEL_A, // PSG Output channel A + output [7:0] CHANNEL_B, // PSG Output channel B + output [7:0] CHANNEL_C, // PSG Output channel C + + input SEL, + input MODE, + + output [5:0] ACTIVE, + + input [7:0] IOA_in, + output [7:0] IOA_out, + + input [7:0] IOB_in, + output [7:0] IOB_out +); + +assign ACTIVE = ~ymreg[7][5:0]; +assign IOA_out = ymreg[7][6] ? ymreg[14] : 8'hff; +assign IOB_out = ymreg[7][7] ? ymreg[15] : 8'hff; + +reg [7:0] addr; +reg [7:0] ymreg[16]; +wire cs = !A9_L & A8; + +// Write to PSG +reg env_reset; +always @(posedge CLK) begin + if(RESET) begin + ymreg <= '{default:0}; + ymreg[7] <= '1; + addr <= '0; + env_reset <= 0; + end else begin + env_reset <= 0; + if(cs & BDIR) begin + if(BC) addr <= DI; + else if(!addr[7:4]) begin + ymreg[addr[3:0]] <= DI; + env_reset <= (addr == 13); + end + end + end +end + +// Read from PSG +assign DO = dout; +reg [7:0] dout; +always_comb begin + dout = 8'hFF; + if(cs & ~BDIR & BC & !addr[7:4]) begin + case(addr[3:0]) + 0: dout = ymreg[0]; + 1: dout = ymreg[1][3:0]; + 2: dout = ymreg[2]; + 3: dout = ymreg[3][3:0]; + 4: dout = ymreg[4]; + 5: dout = ymreg[5][3:0]; + 6: dout = ymreg[6][4:0]; + 7: dout = ymreg[7]; + 8: dout = ymreg[8][4:0]; + 9: dout = ymreg[9][4:0]; + 10: dout = ymreg[10][4:0]; + 11: dout = ymreg[11]; + 12: dout = ymreg[12]; + 13: dout = ymreg[13][3:0]; + 14: dout = ymreg[7][6] ? ymreg[14] : IOA_in; + 15: dout = ymreg[7][7] ? ymreg[15] : IOB_in; + endcase + end +end + +reg ena_div; +reg ena_div_noise; + +// p_divider +always @(posedge CLK) begin + reg [3:0] cnt_div; + reg noise_div; + + if(CE) begin + ena_div <= 0; + ena_div_noise <= 0; + if(!cnt_div) begin + cnt_div <= {SEL, 3'b111}; + ena_div <= 1; + + noise_div <= (~noise_div); + if (noise_div) ena_div_noise <= 1; + end else begin + cnt_div <= cnt_div - 1'b1; + end + end +end + + +reg [2:0] noise_gen_op; + +// p_noise_gen +always @(posedge CLK) begin + reg [16:0] poly17; + reg [4:0] noise_gen_cnt; + + if(CE) begin + if (ena_div_noise) begin + if (!ymreg[6][4:0] || noise_gen_cnt >= ymreg[6][4:0] - 1'd1) begin + noise_gen_cnt <= 0; + poly17 <= {(poly17[0] ^ poly17[2] ^ !poly17), poly17[16:1]}; + end else begin + noise_gen_cnt <= noise_gen_cnt + 1'd1; + end + noise_gen_op <= {3{poly17[0]}}; + end + end +end + +wire [11:0] tone_gen_freq[1:3]; +assign tone_gen_freq[1] = {ymreg[1][3:0], ymreg[0]}; +assign tone_gen_freq[2] = {ymreg[3][3:0], ymreg[2]}; +assign tone_gen_freq[3] = {ymreg[5][3:0], ymreg[4]}; + +reg [3:1] tone_gen_op; + +//p_tone_gens +always @(posedge CLK) begin + integer i; + reg [11:0] tone_gen_cnt[1:3]; + + if(CE) begin + // looks like real chips count up - we need to get the Exact behaviour .. + + for (i = 1; i <= 3; i = i + 1) begin + if(ena_div) begin + if (tone_gen_freq[i]) begin + if (tone_gen_cnt[i] >= (tone_gen_freq[i] - 1'd1)) begin + tone_gen_cnt[i] <= 0; + tone_gen_op[i] <= ~tone_gen_op[i]; + end else begin + tone_gen_cnt[i] <= tone_gen_cnt[i] + 1'd1; + end + end else begin + tone_gen_op[i] <= ymreg[7][i]; + tone_gen_cnt[i] <= 0; + end + end + end + end +end + +reg env_ena; +wire [15:0] env_gen_comp = {ymreg[12], ymreg[11]} ? {ymreg[12], ymreg[11]} - 1'd1 : 16'd0; + +//p_envelope_freq +always @(posedge CLK) begin + reg [15:0] env_gen_cnt; + + if(CE) begin + env_ena <= 0; + if(ena_div) begin + if (env_gen_cnt >= env_gen_comp) begin + env_gen_cnt <= 0; + env_ena <= 1; + end else begin + env_gen_cnt <= (env_gen_cnt + 1'd1); + end + end + end +end + +reg [4:0] env_vol; + +wire is_bot = (env_vol == 5'b00000); +wire is_bot_p1 = (env_vol == 5'b00001); +wire is_top_m1 = (env_vol == 5'b11110); +wire is_top = (env_vol == 5'b11111); + +always @(posedge CLK) begin + reg env_hold; + reg env_inc; + + // envelope shapes + // C AtAlH + // 0 0 x x \___ + // + // 0 1 x x /___ + // + // 1 0 0 0 \\\\ + // + // 1 0 0 1 \___ + // + // 1 0 1 0 \/\/ + // ___ + // 1 0 1 1 \ + // + // 1 1 0 0 //// + // ___ + // 1 1 0 1 / + // + // 1 1 1 0 /\/\ + // + // 1 1 1 1 /___ + + if(env_reset | RESET) begin + // load initial state + if(!ymreg[13][2]) begin // attack + env_vol <= 5'b11111; + env_inc <= 0; // -1 + end else begin + env_vol <= 5'b00000; + env_inc <= 1; // +1 + end + env_hold <= 0; + end + else if(CE) begin + if (env_ena) begin + if (!env_hold) begin + if (env_inc) env_vol <= (env_vol + 5'b00001); + else env_vol <= (env_vol + 5'b11111); + end + + // envelope shape control. + if(!ymreg[13][3]) begin + if(!env_inc) begin // down + if(is_bot_p1) env_hold <= 1; + end else if (is_top) env_hold <= 1; + end else if(ymreg[13][0]) begin // hold = 1 + if(!env_inc) begin // down + if(ymreg[13][1]) begin // alt + if(is_bot) env_hold <= 1; + end else if(is_bot_p1) env_hold <= 1; + end else if(ymreg[13][1]) begin // alt + if(is_top) env_hold <= 1; + end else if(is_top_m1) env_hold <= 1; + end else if(ymreg[13][1]) begin // alternate + if(env_inc == 1'b0) begin // down + if(is_bot_p1) env_hold <= 1; + if(is_bot) begin + env_hold <= 0; + env_inc <= 1; + end + end else begin + if(is_top_m1) env_hold <= 1; + if(is_top) begin + env_hold <= 0; + env_inc <= 0; + end + end + end + end + end +end + +reg [5:0] A,B,C; +always @(posedge CLK) begin + A <= {MODE, ~((ymreg[7][0] | tone_gen_op[1]) & (ymreg[7][3] | noise_gen_op[0])) ? 5'd0 : ymreg[8][4] ? env_vol[4:0] : { ymreg[8][3:0], ymreg[8][3]}}; + B <= {MODE, ~((ymreg[7][1] | tone_gen_op[2]) & (ymreg[7][4] | noise_gen_op[1])) ? 5'd0 : ymreg[9][4] ? env_vol[4:0] : { ymreg[9][3:0], ymreg[9][3]}}; + C <= {MODE, ~((ymreg[7][2] | tone_gen_op[3]) & (ymreg[7][5] | noise_gen_op[2])) ? 5'd0 : ymreg[10][4] ? env_vol[4:0] : {ymreg[10][3:0], ymreg[10][3]}}; +end + +wire [7:0] volTable[64] = '{ + //YM2149 + 8'h00, 8'h01, 8'h01, 8'h02, 8'h02, 8'h03, 8'h03, 8'h04, + 8'h06, 8'h07, 8'h09, 8'h0a, 8'h0c, 8'h0e, 8'h11, 8'h13, + 8'h17, 8'h1b, 8'h20, 8'h25, 8'h2c, 8'h35, 8'h3e, 8'h47, + 8'h54, 8'h66, 8'h77, 8'h88, 8'ha1, 8'hc0, 8'he0, 8'hff, + + //AY8910 + 8'h00, 8'h00, 8'h03, 8'h03, 8'h04, 8'h04, 8'h06, 8'h06, + 8'h0a, 8'h0a, 8'h0f, 8'h0f, 8'h15, 8'h15, 8'h22, 8'h22, + 8'h28, 8'h28, 8'h41, 8'h41, 8'h5b, 8'h5b, 8'h72, 8'h72, + 8'h90, 8'h90, 8'hb5, 8'hb5, 8'hd7, 8'hd7, 8'hff, 8'hff +}; + +assign CHANNEL_A = volTable[A]; +assign CHANNEL_B = volTable[B]; +assign CHANNEL_C = volTable[C]; + +endmodule diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/build_id.tcl b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/cpu68.vhd b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/cpu68.vhd new file mode 100644 index 00000000..016bd9a9 --- /dev/null +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/cpu68.vhd @@ -0,0 +1,3963 @@ +--===========================================================================-- +-- +-- S Y N T H E Z I A B L E CPU68 C O R E +-- +-- www.OpenCores.Org - December 2002 +-- This core adheres to the GNU public license +-- +-- File name : cpu68.vhd +-- +-- Purpose : Implements a 6800 compatible CPU core with some +-- additional instructions found in the 6801 +-- +-- Dependencies : ieee.Std_Logic_1164 +-- ieee.std_logic_unsigned +-- +-- Author : John E. Kent +-- +--===========================================================================---- +-- +-- Revision History: +-- +-- Date: Revision Author +-- 22 Sep 2002 0.1 John Kent +-- +-- 30 Oct 2002 0.2 John Kent +-- made NMI edge triggered +-- +-- 30 Oct 2002 0.3 John Kent +-- more corrections to NMI +-- added wai_wait_state to prevent stack overflow on wai. +-- +-- 1 Nov 2002 0.4 John Kent +-- removed WAI states and integrated WAI with the interrupt service routine +-- replace Data out (do) and Data in (di) register with a single Memory Data (md) reg. +-- Added Multiply instruction states. +-- run ALU and CC out of CPU module for timing measurements. +-- +-- 3 Nov 2002 0.5 John Kent +-- Memory Data Register was not loaded on Store instructions +-- SEV and CLV were not defined in the ALU +-- Overflow Flag on NEG was incorrect +-- +-- 16th Feb 2003 0.6 John Kent +-- Rearranged the execution cycle for dual operand instructions +-- so that occurs during the following fetch cycle. +-- This allows the reduction of one clock cycle from dual operand +-- instruction. Note that this also necessitated re-arranging the +-- program counter so that it is no longer incremented in the ALU. +-- The effective address has also been re-arranged to include a +-- separate added. The STD (store accd) now sets the condition codes. +-- +-- 28th Jun 2003 0.7 John Kent +-- Added Hold and Halt signals. Hold is used to steal cycles from the +-- CPU or add wait states. Halt puts the CPU in the inactive state +-- and is only honoured in the fetch cycle. Both signals are active high. +-- +-- 9th Jan 2004 0.8 John Kent +-- Clear instruction did an alu_ld8 rather than an alu_clr, so +-- the carry bit was not cleared correctly. +-- This error was picked up by Michael Hassenfratz. +-- + +library ieee; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity cpu68 is + port ( + clk: in std_logic; + rst: in std_logic; + rw: out std_logic; + vma: out std_logic; + address: out std_logic_vector(15 downto 0); + data_in: in std_logic_vector(7 downto 0); + data_out: out std_logic_vector(7 downto 0); + hold: in std_logic; + halt: in std_logic; + irq: in std_logic; + nmi: in std_logic; + test_alu: out std_logic_vector(15 downto 0); + test_cc: out std_logic_vector(7 downto 0) + ); +end; + +architecture CPU_ARCH of cpu68 is + + constant SBIT : integer := 7; + constant XBIT : integer := 6; + constant HBIT : integer := 5; + constant IBIT : integer := 4; + constant NBIT : integer := 3; + constant ZBIT : integer := 2; + constant VBIT : integer := 1; + constant CBIT : integer := 0; + + type state_type is (reset_state, fetch_state, decode_state, + extended_state, indexed_state, read8_state, read16_state, immediate16_state, + write8_state, write16_state, + execute_state, halt_state, error_state, + mul_state, mulea_state, muld_state, + mul0_state, mul1_state, mul2_state, mul3_state, + mul4_state, mul5_state, mul6_state, mul7_state, + jmp_state, jsr_state, jsr1_state, + branch_state, bsr_state, bsr1_state, + rts_hi_state, rts_lo_state, + int_pcl_state, int_pch_state, + int_ixl_state, int_ixh_state, + int_cc_state, int_acca_state, int_accb_state, + int_wai_state, int_mask_state, + rti_state, rti_cc_state, rti_acca_state, rti_accb_state, + rti_ixl_state, rti_ixh_state, + rti_pcl_state, rti_pch_state, + pula_state, psha_state, pulb_state, pshb_state, + pulx_lo_state, pulx_hi_state, pshx_lo_state, pshx_hi_state, + vect_lo_state, vect_hi_state ); + type addr_type is (idle_ad, fetch_ad, read_ad, write_ad, push_ad, pull_ad, int_hi_ad, int_lo_ad ); + type dout_type is (md_lo_dout, md_hi_dout, acca_dout, accb_dout, ix_lo_dout, ix_hi_dout, cc_dout, pc_lo_dout, pc_hi_dout ); + type op_type is (reset_op, fetch_op, latch_op ); + type acca_type is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca ); + type accb_type is (reset_accb, load_accb, pull_accb, latch_accb ); + type cc_type is (reset_cc, load_cc, pull_cc, latch_cc ); + type ix_type is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix ); + type sp_type is (reset_sp, latch_sp, load_sp ); + type pc_type is (reset_pc, latch_pc, load_ea_pc, add_ea_pc, pull_lo_pc, pull_hi_pc, inc_pc ); + type md_type is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md ); + type ea_type is (reset_ea, latch_ea, add_ix_ea, load_accb_ea, inc_ea, fetch_first_ea, fetch_next_ea ); + type iv_type is (reset_iv, latch_iv, swi_iv, nmi_iv, irq_iv ); + type nmi_type is (reset_nmi, set_nmi, latch_nmi ); + type left_type is (acca_left, accb_left, accd_left, md_left, ix_left, sp_left ); + type right_type is (md_right, zero_right, plus_one_right, accb_right ); + type alu_type is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc, + alu_and, alu_ora, alu_eor, + alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com, + alu_inx, alu_dex, alu_cpx, + alu_lsr16, alu_lsl16, + alu_ror8, alu_rol8, + alu_asr8, alu_asl8, alu_lsr8, + alu_sei, alu_cli, alu_sec, alu_clc, alu_sev, alu_clv, alu_tpa, alu_tap, + alu_ld8, alu_st8, alu_ld16, alu_st16, alu_nop, alu_daa ); + + signal op_code: std_logic_vector(7 downto 0); + signal acca: std_logic_vector(7 downto 0); + signal accb: std_logic_vector(7 downto 0); + signal cc: std_logic_vector(7 downto 0); + signal cc_out: std_logic_vector(7 downto 0); + signal xreg: std_logic_vector(15 downto 0); + signal sp: std_logic_vector(15 downto 0); + signal ea: std_logic_vector(15 downto 0); + signal pc: std_logic_vector(15 downto 0); + signal md: std_logic_vector(15 downto 0); + signal left: std_logic_vector(15 downto 0); + signal right: std_logic_vector(15 downto 0); + signal out_alu: std_logic_vector(15 downto 0); + signal iv: std_logic_vector(1 downto 0); + signal nmi_req: std_logic; + signal nmi_ack: std_logic; + + signal state: state_type; + signal next_state: state_type; + signal pc_ctrl: pc_type; + signal ea_ctrl: ea_type; + signal op_ctrl: op_type; + signal md_ctrl: md_type; + signal acca_ctrl: acca_type; + signal accb_ctrl: accb_type; + signal ix_ctrl: ix_type; + signal cc_ctrl: cc_type; + signal sp_ctrl: sp_type; + signal iv_ctrl: iv_type; + signal left_ctrl: left_type; + signal right_ctrl: right_type; + signal alu_ctrl: alu_type; + signal addr_ctrl: addr_type; + signal dout_ctrl: dout_type; + signal nmi_ctrl: nmi_type; + + +begin + +---------------------------------- +-- +-- Address bus multiplexer +-- +---------------------------------- + +addr_mux: process( clk, addr_ctrl, pc, ea, sp, iv ) +begin + case addr_ctrl is + when idle_ad => + address <= "1111111111111111"; + vma <= '0'; + rw <= '1'; + when fetch_ad => + address <= pc; + vma <= '1'; + rw <= '1'; + when read_ad => + address <= ea; + vma <= '1'; + rw <= '1'; + when write_ad => + address <= ea; + vma <= '1'; + rw <= '0'; + when push_ad => + address <= sp; + vma <= '1'; + rw <= '0'; + when pull_ad => + address <= sp; + vma <= '1'; + rw <= '1'; + when int_hi_ad => + address <= "1111111111111" & iv & "0"; + vma <= '1'; + rw <= '1'; + when int_lo_ad => + address <= "1111111111111" & iv & "1"; + vma <= '1'; + rw <= '1'; + when others => + address <= "1111111111111111"; + vma <= '0'; + rw <= '1'; + end case; +end process; + +-------------------------------- +-- +-- Data Bus output +-- +-------------------------------- +dout_mux : process( clk, dout_ctrl, md, acca, accb, xreg, pc, cc ) +begin + case dout_ctrl is + when md_hi_dout => -- alu output + data_out <= md(15 downto 8); + when md_lo_dout => + data_out <= md(7 downto 0); + when acca_dout => -- accumulator a + data_out <= acca; + when accb_dout => -- accumulator b + data_out <= accb; + when ix_lo_dout => -- index reg + data_out <= xreg(7 downto 0); + when ix_hi_dout => -- index reg + data_out <= xreg(15 downto 8); + when cc_dout => -- condition codes + data_out <= cc; + when pc_lo_dout => -- low order pc + data_out <= pc(7 downto 0); + when pc_hi_dout => -- high order pc + data_out <= pc(15 downto 8); + when others => + data_out <= "00000000"; + end case; +end process; + + +---------------------------------- +-- +-- Program Counter Control +-- +---------------------------------- + +pc_mux: process( clk, pc_ctrl, pc, out_alu, data_in, ea, hold ) +variable tempof : std_logic_vector(15 downto 0); +variable temppc : std_logic_vector(15 downto 0); +begin + case pc_ctrl is + when add_ea_pc => + if ea(7) = '0' then + tempof := "00000000" & ea(7 downto 0); + else + tempof := "11111111" & ea(7 downto 0); + end if; + when inc_pc => + tempof := "0000000000000001"; + when others => + tempof := "0000000000000000"; + end case; + + case pc_ctrl is + when reset_pc => + temppc := "1111111111111110"; + when load_ea_pc => + temppc := ea; + when pull_lo_pc => + temppc(7 downto 0) := data_in; + temppc(15 downto 8) := pc(15 downto 8); + when pull_hi_pc => + temppc(7 downto 0) := pc(7 downto 0); + temppc(15 downto 8) := data_in; + when others => + temppc := pc; + end case; + + if clk'event and clk = '0' then + if hold = '1' then + pc <= pc; + else + pc <= temppc + tempof; + end if; + end if; +end process; + +---------------------------------- +-- +-- Effective Address Control +-- +---------------------------------- + +ea_mux: process( clk, ea_ctrl, ea, out_alu, data_in, accb, xreg, hold ) +variable tempind : std_logic_vector(15 downto 0); +variable tempea : std_logic_vector(15 downto 0); +begin + case ea_ctrl is + when add_ix_ea => + tempind := "00000000" & ea(7 downto 0); + when inc_ea => + tempind := "0000000000000001"; + when others => + tempind := "0000000000000000"; + end case; + + case ea_ctrl is + when reset_ea => + tempea := "0000000000000000"; + when load_accb_ea => + tempea := "00000000" & accb(7 downto 0); + when add_ix_ea => + tempea := xreg; + when fetch_first_ea => + tempea(7 downto 0) := data_in; + tempea(15 downto 8) := "00000000"; + when fetch_next_ea => + tempea(7 downto 0) := data_in; + tempea(15 downto 8) := ea(7 downto 0); + when others => + tempea := ea; + end case; + + if clk'event and clk = '0' then + if hold = '1' then + ea <= ea; + else + ea <= tempea + tempind; + end if; + end if; +end process; + +-------------------------------- +-- +-- Accumulator A +-- +-------------------------------- +acca_mux : process( clk, acca_ctrl, out_alu, acca, data_in, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + acca <= acca; + else + case acca_ctrl is + when reset_acca => + acca <= "00000000"; + when load_acca => + acca <= out_alu(7 downto 0); + when load_hi_acca => + acca <= out_alu(15 downto 8); + when pull_acca => + acca <= data_in; + when others => +-- when latch_acca => + acca <= acca; + end case; + end if; + end if; +end process; + +-------------------------------- +-- +-- Accumulator B +-- +-------------------------------- +accb_mux : process( clk, accb_ctrl, out_alu, accb, data_in, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + accb <= accb; + else + case accb_ctrl is + when reset_accb => + accb <= "00000000"; + when load_accb => + accb <= out_alu(7 downto 0); + when pull_accb => + accb <= data_in; + when others => +-- when latch_accb => + accb <= accb; + end case; + end if; + end if; +end process; + +-------------------------------- +-- +-- X Index register +-- +-------------------------------- +ix_mux : process( clk, ix_ctrl, out_alu, xreg, data_in, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + xreg <= xreg; + else + case ix_ctrl is + when reset_ix => + xreg <= "0000000000000000"; + when load_ix => + xreg <= out_alu(15 downto 0); + when pull_hi_ix => + xreg(15 downto 8) <= data_in; + when pull_lo_ix => + xreg(7 downto 0) <= data_in; + when others => +-- when latch_ix => + xreg <= xreg; + end case; + end if; + end if; +end process; + +-------------------------------- +-- +-- stack pointer +-- +-------------------------------- +sp_mux : process( clk, sp_ctrl, out_alu, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + sp <= sp; + else + case sp_ctrl is + when reset_sp => + sp <= "0000000000000000"; + when load_sp => + sp <= out_alu(15 downto 0); + when others => +-- when latch_sp => + sp <= sp; + end case; + end if; + end if; +end process; + +-------------------------------- +-- +-- Memory Data +-- +-------------------------------- +md_mux : process( clk, md_ctrl, out_alu, data_in, md, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + md <= md; + else + case md_ctrl is + when reset_md => + md <= "0000000000000000"; + when load_md => + md <= out_alu(15 downto 0); + when fetch_first_md => + md(15 downto 8) <= "00000000"; + md(7 downto 0) <= data_in; + when fetch_next_md => + md(15 downto 8) <= md(7 downto 0); + md(7 downto 0) <= data_in; + when shiftl_md => + md(15 downto 1) <= md(14 downto 0); + md(0) <= '0'; + when others => +-- when latch_md => + md <= md; + end case; + end if; + end if; +end process; + + +---------------------------------- +-- +-- Condition Codes +-- +---------------------------------- + +cc_mux: process( clk, cc_ctrl, cc_out, cc, data_in, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + cc <= cc; + else + case cc_ctrl is + when reset_cc => + cc <= "11000000"; + when load_cc => + cc <= cc_out; + when pull_cc => + cc <= data_in; + when others => +-- when latch_cc => + cc <= cc; + end case; + end if; + end if; +end process; + +---------------------------------- +-- +-- interrupt vector +-- +---------------------------------- + +iv_mux: process( clk, iv_ctrl, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + iv <= iv; + else + case iv_ctrl is + when reset_iv => + iv <= "11"; + when nmi_iv => + iv <= "10"; + when swi_iv => + iv <= "01"; + when irq_iv => + iv <= "00"; + when others => + iv <= iv; + end case; + end if; + end if; +end process; + +---------------------------------- +-- +-- op code fetch +-- +---------------------------------- + +op_fetch: process( clk, data_in, op_ctrl, op_code, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + op_code <= op_code; + else + case op_ctrl is + when reset_op => + op_code <= "00000001"; -- nop + when fetch_op => + op_code <= data_in; + when others => +-- when latch_op => + op_code <= op_code; + end case; + end if; + end if; +end process; + +---------------------------------- +-- +-- Left Mux +-- +---------------------------------- + +left_mux: process( left_ctrl, acca, accb, xreg, sp, pc, ea, md ) +begin + case left_ctrl is + when acca_left => + left(15 downto 8) <= "00000000"; + left(7 downto 0) <= acca; + when accb_left => + left(15 downto 8) <= "00000000"; + left(7 downto 0) <= accb; + when accd_left => + left(15 downto 8) <= acca; + left(7 downto 0) <= accb; + when ix_left => + left <= xreg; + when sp_left => + left <= sp; + when others => +-- when md_left => + left <= md; + end case; +end process; +---------------------------------- +-- +-- Right Mux +-- +---------------------------------- + +right_mux: process( right_ctrl, data_in, md, accb, ea ) +begin + case right_ctrl is + when zero_right => + right <= "0000000000000000"; + when plus_one_right => + right <= "0000000000000001"; + when accb_right => + right <= "00000000" & accb; + when others => +-- when md_right => + right <= md; + end case; +end process; + +---------------------------------- +-- +-- Arithmetic Logic Unit +-- +---------------------------------- + +mux_alu: process( alu_ctrl, cc, left, right, out_alu, cc_out ) +variable valid_lo, valid_hi : boolean; +variable carry_in : std_logic; +variable daa_reg : std_logic_vector(7 downto 0); +begin + + case alu_ctrl is + when alu_adc | alu_sbc | + alu_rol8 | alu_ror8 => + carry_in := cc(CBIT); + when others => + carry_in := '0'; + end case; + + valid_lo := left(3 downto 0) <= 9; + valid_hi := left(7 downto 4) <= 9; + + if (cc(CBIT) = '0') then + if( cc(HBIT) = '1' ) then + if valid_hi then + daa_reg := "00000110"; + else + daa_reg := "01100110"; + end if; + else + if valid_lo then + if valid_hi then + daa_reg := "00000000"; + else + daa_reg := "01100000"; + end if; + else + if( left(7 downto 4) <= 8 ) then + daa_reg := "00000110"; + else + daa_reg := "01100110"; + end if; + end if; + end if; + else + if ( cc(HBIT) = '1' )then + daa_reg := "01100110"; + else + if valid_lo then + daa_reg := "01100000"; + else + daa_reg := "01100110"; + end if; + end if; + end if; + + case alu_ctrl is + when alu_add8 | alu_inc | + alu_add16 | alu_inx | + alu_adc => + out_alu <= left + right + ("000000000000000" & carry_in); + when alu_sub8 | alu_dec | + alu_sub16 | alu_dex | + alu_sbc | alu_cpx => + out_alu <= left - right - ("000000000000000" & carry_in); + when alu_and => + out_alu <= left and right; -- and/bit + when alu_ora => + out_alu <= left or right; -- or + when alu_eor => + out_alu <= left xor right; -- eor/xor + when alu_lsl16 | alu_asl8 | alu_rol8 => + out_alu <= left(14 downto 0) & carry_in; -- rol8/asl8/lsl16 + when alu_lsr16 | alu_lsr8 => + out_alu <= carry_in & left(15 downto 1); -- lsr + when alu_ror8 => + out_alu <= "00000000" & carry_in & left(7 downto 1); -- ror + when alu_asr8 => + out_alu <= "00000000" & left(7) & left(7 downto 1); -- asr + when alu_neg => + out_alu <= right - left; -- neg (right=0) + when alu_com => + out_alu <= not left; + when alu_clr | alu_ld8 | alu_ld16 => + out_alu <= right; -- clr, ld + when alu_st8 | alu_st16 => + out_alu <= left; + when alu_daa => + out_alu <= left + ("00000000" & daa_reg); + when alu_tpa => + out_alu <= "00000000" & cc; + when others => + out_alu <= left; -- nop + end case; + + -- + -- carry bit + -- + case alu_ctrl is + when alu_add8 | alu_adc => + cc_out(CBIT) <= (left(7) and right(7)) or + (left(7) and not out_alu(7)) or + (right(7) and not out_alu(7)); + when alu_sub8 | alu_sbc => + cc_out(CBIT) <= ((not left(7)) and right(7)) or + ((not left(7)) and out_alu(7)) or + (right(7) and out_alu(7)); + when alu_add16 => + cc_out(CBIT) <= (left(15) and right(15)) or + (left(15) and not out_alu(15)) or + (right(15) and not out_alu(15)); + when alu_sub16 => + cc_out(CBIT) <= ((not left(15)) and right(15)) or + ((not left(15)) and out_alu(15)) or + (right(15) and out_alu(15)); + when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 => + cc_out(CBIT) <= left(0); + when alu_rol8 | alu_asl8 => + cc_out(CBIT) <= left(7); + when alu_lsl16 => + cc_out(CBIT) <= left(15); + when alu_com => + cc_out(CBIT) <= '1'; + when alu_neg | alu_clr => + cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or + out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0); + when alu_daa => + if ( daa_reg(7 downto 4) = "0110" ) then + cc_out(CBIT) <= '1'; + else + cc_out(CBIT) <= '0'; + end if; + when alu_sec => + cc_out(CBIT) <= '1'; + when alu_clc => + cc_out(CBIT) <= '0'; + when alu_tap => + cc_out(CBIT) <= left(CBIT); + when others => -- carry is not affected by cpx + cc_out(CBIT) <= cc(CBIT); + end case; + -- + -- Zero flag + -- + case alu_ctrl is + when alu_add8 | alu_sub8 | + alu_adc | alu_sbc | + alu_and | alu_ora | alu_eor | + alu_inc | alu_dec | + alu_neg | alu_com | alu_clr | + alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 | + alu_ld8 | alu_st8 => + cc_out(ZBIT) <= not( out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or + out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) ); + when alu_add16 | alu_sub16 | + alu_lsl16 | alu_lsr16 | + alu_inx | alu_dex | + alu_ld16 | alu_st16 | alu_cpx => + cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or + out_alu(11) or out_alu(10) or out_alu(9) or out_alu(8) or + out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or + out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) ); + when alu_tap => + cc_out(ZBIT) <= left(ZBIT); + when others => + cc_out(ZBIT) <= cc(ZBIT); + end case; + + -- + -- negative flag + -- + case alu_ctrl is + when alu_add8 | alu_sub8 | + alu_adc | alu_sbc | + alu_and | alu_ora | alu_eor | + alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 | + alu_inc | alu_dec | alu_neg | alu_com | alu_clr | + alu_ld8 | alu_st8 => + cc_out(NBIT) <= out_alu(7); + when alu_add16 | alu_sub16 | + alu_lsl16 | alu_lsr16 | + alu_ld16 | alu_st16 | alu_cpx => + cc_out(NBIT) <= out_alu(15); + when alu_tap => + cc_out(NBIT) <= left(NBIT); + when others => + cc_out(NBIT) <= cc(NBIT); + end case; + + -- + -- Interrupt mask flag + -- + case alu_ctrl is + when alu_sei => + cc_out(IBIT) <= '1'; -- set interrupt mask + when alu_cli => + cc_out(IBIT) <= '0'; -- clear interrupt mask + when alu_tap => + cc_out(IBIT) <= left(IBIT); + when others => + cc_out(IBIT) <= cc(IBIT); -- interrupt mask + end case; + + -- + -- Half Carry flag + -- + case alu_ctrl is + when alu_add8 | alu_adc => + cc_out(HBIT) <= (left(3) and right(3)) or + (right(3) and not out_alu(3)) or + (left(3) and not out_alu(3)); + when alu_tap => + cc_out(HBIT) <= left(HBIT); + when others => + cc_out(HBIT) <= cc(HBIT); + end case; + + -- + -- Overflow flag + -- + case alu_ctrl is + when alu_add8 | alu_adc => + cc_out(VBIT) <= (left(7) and right(7) and (not out_alu(7))) or + ((not left(7)) and (not right(7)) and out_alu(7)); + when alu_sub8 | alu_sbc => + cc_out(VBIT) <= (left(7) and (not right(7)) and (not out_alu(7))) or + ((not left(7)) and right(7) and out_alu(7)); + when alu_add16 => + cc_out(VBIT) <= (left(15) and right(15) and (not out_alu(15))) or + ((not left(15)) and (not right(15)) and out_alu(15)); + when alu_sub16 | alu_cpx => + cc_out(VBIT) <= (left(15) and (not right(15)) and (not out_alu(15))) or + ((not left(15)) and right(15) and out_alu(15)); + when alu_inc => + cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and + left(3) and left(2) and left(1) and left(0)); + when alu_dec | alu_neg => + cc_out(VBIT) <= (left(7) and (not left(6)) and (not left(5)) and (not left(4)) and + (not left(3)) and (not left(2)) and (not left(1)) and (not left(0))); + when alu_asr8 => + cc_out(VBIT) <= left(0) xor left(7); + when alu_lsr8 | alu_lsr16 => + cc_out(VBIT) <= left(0); + when alu_ror8 => + cc_out(VBIT) <= left(0) xor cc(CBIT); + when alu_lsl16 => + cc_out(VBIT) <= left(15) xor left(14); + when alu_rol8 | alu_asl8 => + cc_out(VBIT) <= left(7) xor left(6); + when alu_tap => + cc_out(VBIT) <= left(VBIT); + when alu_and | alu_ora | alu_eor | alu_com | + alu_st8 | alu_st16 | alu_ld8 | alu_ld16 | + alu_clv => + cc_out(VBIT) <= '0'; + when alu_sev => + cc_out(VBIT) <= '1'; + when others => + cc_out(VBIT) <= cc(VBIT); + end case; + + case alu_ctrl is + when alu_tap => + cc_out(XBIT) <= cc(XBIT) and left(XBIT); + cc_out(SBIT) <= left(SBIT); + when others => + cc_out(XBIT) <= cc(XBIT) and left(XBIT); + cc_out(SBIT) <= cc(SBIT); + end case; + + test_alu <= out_alu; + test_cc <= cc_out; +end process; + +------------------------------------ +-- +-- Detect Edge of NMI interrupt +-- +------------------------------------ + +nmi_handler : process( clk, rst, nmi, nmi_ack ) +begin + if clk'event and clk='0' then + if hold = '1' then + nmi_req <= nmi_req; + else + if rst='1' then + nmi_req <= '0'; + else + if (nmi='1') and (nmi_ack='0') then + nmi_req <= '1'; + else + if (nmi='0') and (nmi_ack='1') then + nmi_req <= '0'; + else + nmi_req <= nmi_req; + end if; + end if; + end if; + end if; + end if; +end process; + +------------------------------------ +-- +-- Nmi mux +-- +------------------------------------ + +nmi_mux: process( clk, nmi_ctrl, nmi_ack, hold ) +begin + if clk'event and clk='0' then + if hold = '1' then + nmi_ack <= nmi_ack; + else + case nmi_ctrl is + when set_nmi => + nmi_ack <= '1'; + when reset_nmi => + nmi_ack <= '0'; + when others => +-- when latch_nmi => + nmi_ack <= nmi_ack; + end case; + end if; + end if; +end process; + +------------------------------------ +-- +-- state sequencer +-- +------------------------------------ +process( state, op_code, cc, ea, irq, nmi_req, nmi_ack, hold, halt ) + begin + case state is + when reset_state => -- released from reset + -- reset the registers + op_ctrl <= reset_op; + acca_ctrl <= reset_acca; + accb_ctrl <= reset_accb; + ix_ctrl <= reset_ix; + sp_ctrl <= reset_sp; + pc_ctrl <= reset_pc; + ea_ctrl <= reset_ea; + md_ctrl <= reset_md; + iv_ctrl <= reset_iv; + nmi_ctrl <= reset_nmi; + -- idle the ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= reset_cc; + -- idle the bus + dout_ctrl <= md_lo_dout; + addr_ctrl <= idle_ad; + next_state <= vect_hi_state; + + -- + -- Jump via interrupt vector + -- iv holds interrupt type + -- fetch PC hi from vector location + -- + when vect_hi_state => + -- default the registers + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + md_ctrl <= latch_md; + ea_ctrl <= latch_ea; + iv_ctrl <= latch_iv; + -- idle the ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- fetch pc low interrupt vector + pc_ctrl <= pull_hi_pc; + addr_ctrl <= int_hi_ad; + dout_ctrl <= pc_hi_dout; + next_state <= vect_lo_state; + -- + -- jump via interrupt vector + -- iv holds vector type + -- fetch PC lo from vector location + -- + when vect_lo_state => + -- default the registers + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + md_ctrl <= latch_md; + ea_ctrl <= latch_ea; + iv_ctrl <= latch_iv; + -- idle the ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- fetch the vector low byte + pc_ctrl <= pull_lo_pc; + addr_ctrl <= int_lo_ad; + dout_ctrl <= pc_lo_dout; + next_state <= fetch_state; + + -- + -- Here to fetch an instruction + -- PC points to opcode + -- Should service interrupt requests at this point + -- either from the timer + -- or from the external input. + -- + when fetch_state => + case op_code(7 downto 4) is + when "0000" | + "0001" | + "0010" | -- branch conditional + "0011" | + "0100" | -- acca single op + "0101" | -- accb single op + "0110" | -- indexed single op + "0111" => -- extended single op + -- idle ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + + when "1000" | -- acca immediate + "1001" | -- acca direct + "1010" | -- acca indexed + "1011" => -- acca extended + case op_code(3 downto 0) is + when "0000" => -- suba + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0001" => -- cmpa + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0010" => -- sbca + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sbc; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0011" => -- subd + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0100" => -- anda + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_and; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0101" => -- bita + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_and; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0110" => -- ldaa + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0111" => -- staa + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1000" => -- eora + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_eor; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1001" => -- adca + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_adc; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1010" => -- oraa + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ora; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1011" => -- adda + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1100" => -- cpx + left_ctrl <= ix_left; + right_ctrl <= md_right; + alu_ctrl <= alu_cpx; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1101" => -- bsr / jsr + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1110" => -- lds + left_ctrl <= sp_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld16; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + when "1111" => -- sts + left_ctrl <= sp_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st16; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when others => + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + end case; + when "1100" | -- accb immediate + "1101" | -- accb direct + "1110" | -- accb indexed + "1111" => -- accb extended + case op_code(3 downto 0) is + when "0000" => -- subb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0001" => -- cmpb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0010" => -- sbcb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sbc; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0011" => -- addd + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0100" => -- andb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_and; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0101" => -- bitb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_and; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0110" => -- ldab + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0111" => -- stab + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1000" => -- eorb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_eor; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1001" => -- adcb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_adc; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1010" => -- orab + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ora; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1011" => -- addb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1100" => -- ldd + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld16; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1101" => -- std + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st16; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1110" => -- ldx + left_ctrl <= ix_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld16; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= load_ix; + sp_ctrl <= latch_sp; + when "1111" => -- stx + left_ctrl <= ix_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st16; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when others => + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + end case; + when others => + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + end case; + md_ctrl <= latch_md; + -- fetch the op code + op_ctrl <= fetch_op; + ea_ctrl <= reset_ea; + addr_ctrl <= fetch_ad; + dout_ctrl <= md_lo_dout; + iv_ctrl <= latch_iv; + if halt = '1' then + pc_ctrl <= latch_pc; + nmi_ctrl <= latch_nmi; + next_state <= halt_state; + -- service non maskable interrupts + elsif (nmi_req = '1') and (nmi_ack = '0') then + pc_ctrl <= latch_pc; + nmi_ctrl <= set_nmi; + next_state <= int_pcl_state; + -- service maskable interrupts + else + -- + -- nmi request is not cleared until nmi input goes low + -- + if(nmi_req = '0') and (nmi_ack='1') then + nmi_ctrl <= reset_nmi; + else + nmi_ctrl <= latch_nmi; + end if; + -- + -- IRQ is level sensitive + -- + if (irq = '1') and (cc(IBIT) = '0') then + pc_ctrl <= latch_pc; + next_state <= int_pcl_state; + else + -- Advance the PC to fetch next instruction byte + pc_ctrl <= inc_pc; + next_state <= decode_state; + end if; + end if; + -- + -- Here to decode instruction + -- and fetch next byte of intruction + -- whether it be necessary or not + -- + when decode_state => + -- fetch first byte of address or immediate data + ea_ctrl <= fetch_first_ea; + addr_ctrl <= fetch_ad; + dout_ctrl <= md_lo_dout; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + iv_ctrl <= latch_iv; + case op_code(7 downto 4) is + when "0000" => + md_ctrl <= fetch_first_md; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + case op_code(3 downto 0) is + when "0001" => -- nop + left_ctrl <= accd_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "0100" => -- lsrd + left_ctrl <= accd_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_lsr16; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + when "0101" => -- lsld + left_ctrl <= accd_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_lsl16; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + when "0110" => -- tap + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_tap; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "0111" => -- tpa + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_tpa; + cc_ctrl <= latch_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "1000" => -- inx + left_ctrl <= ix_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_inx; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= load_ix; + when "1001" => -- dex + left_ctrl <= ix_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_dex; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= load_ix; + when "1010" => -- clv + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_clv; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "1011" => -- sev + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_sev; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "1100" => -- clc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_clc; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "1101" => -- sec + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_sec; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "1110" => -- cli + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_cli; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "1111" => -- sei + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_sei; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + end case; + next_state <= fetch_state; + -- acca / accb inherent instructions + when "0001" => + md_ctrl <= fetch_first_md; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + left_ctrl <= acca_left; + right_ctrl <= accb_right; + case op_code(3 downto 0) is + when "0000" => -- sba + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + when "0001" => -- cba + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + when "0110" => -- tab + alu_ctrl <= alu_st8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + when "0111" => -- tba + alu_ctrl <= alu_ld8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + when "1001" => -- daa + alu_ctrl <= alu_daa; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + when "1011" => -- aba + alu_ctrl <= alu_add8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + when others => + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end case; + next_state <= fetch_state; + when "0010" => -- branch conditional + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- increment the pc + pc_ctrl <= inc_pc; + case op_code(3 downto 0) is + when "0000" => -- bra + next_state <= branch_state; + when "0001" => -- brn + next_state <= fetch_state; + when "0010" => -- bhi + if (cc(CBIT) or cc(ZBIT)) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "0011" => -- bls + if (cc(CBIT) or cc(ZBIT)) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "0100" => -- bcc/bhs + if cc(CBIT) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "0101" => -- bcs/blo + if cc(CBIT) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "0110" => -- bne + if cc(ZBIT) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "0111" => -- beq + if cc(ZBIT) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1000" => -- bvc + if cc(VBIT) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1001" => -- bvs + if cc(VBIT) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1010" => -- bpl + if cc(NBIT) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1011" => -- bmi + if cc(NBIT) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1100" => -- bge + if (cc(NBIT) xor cc(VBIT)) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1101" => -- blt + if (cc(NBIT) xor cc(VBIT)) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1110" => -- bgt + if (cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1111" => -- ble + if (cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when others => + next_state <= fetch_state; + end case; + -- + -- Single byte stack operators + -- Do not advance PC + -- + when "0011" => + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + pc_ctrl <= latch_pc; + case op_code(3 downto 0) is + when "0000" => -- tsx + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= load_ix; + sp_ctrl <= latch_sp; + next_state <= fetch_state; + when "0001" => -- ins + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= fetch_state; + when "0010" => -- pula + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= pula_state; + when "0011" => -- pulb + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= pulb_state; + when "0100" => -- des + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= fetch_state; + when "0101" => -- txs + left_ctrl <= ix_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= fetch_state; + when "0110" => -- psha + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= psha_state; + when "0111" => -- pshb + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= pshb_state; + when "1000" => -- pulx + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= pulx_hi_state; + when "1001" => -- rts + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= rts_hi_state; + when "1010" => -- abx + left_ctrl <= ix_left; + right_ctrl <= accb_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= load_ix; + sp_ctrl <= latch_sp; + next_state <= fetch_state; + when "1011" => -- rti + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= rti_cc_state; + when "1100" => -- pshx + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= pshx_lo_state; + when "1101" => -- mul + left_ctrl <= acca_left; + right_ctrl <= accb_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= mul_state; + when "1110" => -- wai + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= int_pcl_state; + when "1111" => -- swi + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= int_pcl_state; + when others => + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= fetch_state; + end case; + -- + -- Accumulator A Single operand + -- source = Acc A dest = Acc A + -- Do not advance PC + -- + when "0100" => -- acca single op + md_ctrl <= fetch_first_md; + accb_ctrl <= latch_accb; + pc_ctrl <= latch_pc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + left_ctrl <= acca_left; + case op_code(3 downto 0) is + when "0000" => -- neg + right_ctrl <= zero_right; + alu_ctrl <= alu_neg; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "0011" => -- com + right_ctrl <= zero_right; + alu_ctrl <= alu_com; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "0100" => -- lsr + right_ctrl <= zero_right; + alu_ctrl <= alu_lsr8; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "0110" => -- ror + right_ctrl <= zero_right; + alu_ctrl <= alu_ror8; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "0111" => -- asr + right_ctrl <= zero_right; + alu_ctrl <= alu_asr8; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "1000" => -- asl + right_ctrl <= zero_right; + alu_ctrl <= alu_asl8; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "1001" => -- rol + right_ctrl <= zero_right; + alu_ctrl <= alu_rol8; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "1010" => -- dec + right_ctrl <= plus_one_right; + alu_ctrl <= alu_dec; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "1011" => -- undefined + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + acca_ctrl <= latch_acca; + cc_ctrl <= latch_cc; + when "1100" => -- inc + right_ctrl <= plus_one_right; + alu_ctrl <= alu_inc; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "1101" => -- tst + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + acca_ctrl <= latch_acca; + cc_ctrl <= load_cc; + when "1110" => -- jmp + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + acca_ctrl <= latch_acca; + cc_ctrl <= latch_cc; + when "1111" => -- clr + right_ctrl <= zero_right; + alu_ctrl <= alu_clr; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when others => + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + acca_ctrl <= latch_acca; + cc_ctrl <= latch_cc; + end case; + next_state <= fetch_state; + -- + -- single operand acc b + -- Do not advance PC + -- + when "0101" => + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + pc_ctrl <= latch_pc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + left_ctrl <= accb_left; + case op_code(3 downto 0) is + when "0000" => -- neg + right_ctrl <= zero_right; + alu_ctrl <= alu_neg; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "0011" => -- com + right_ctrl <= zero_right; + alu_ctrl <= alu_com; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "0100" => -- lsr + right_ctrl <= zero_right; + alu_ctrl <= alu_lsr8; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "0110" => -- ror + right_ctrl <= zero_right; + alu_ctrl <= alu_ror8; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "0111" => -- asr + right_ctrl <= zero_right; + alu_ctrl <= alu_asr8; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "1000" => -- asl + right_ctrl <= zero_right; + alu_ctrl <= alu_asl8; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "1001" => -- rol + right_ctrl <= zero_right; + alu_ctrl <= alu_rol8; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "1010" => -- dec + right_ctrl <= plus_one_right; + alu_ctrl <= alu_dec; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "1011" => -- undefined + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + accb_ctrl <= latch_accb; + cc_ctrl <= latch_cc; + when "1100" => -- inc + right_ctrl <= plus_one_right; + alu_ctrl <= alu_inc; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "1101" => -- tst + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + accb_ctrl <= latch_accb; + cc_ctrl <= load_cc; + when "1110" => -- jmp + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + accb_ctrl <= latch_accb; + cc_ctrl <= latch_cc; + when "1111" => -- clr + right_ctrl <= zero_right; + alu_ctrl <= alu_clr; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when others => + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + accb_ctrl <= latch_accb; + cc_ctrl <= latch_cc; + end case; + next_state <= fetch_state; + -- + -- Single operand indexed + -- Two byte instruction so advance PC + -- EA should hold index offset + -- + when "0110" => -- indexed single op + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + next_state <= indexed_state; + -- + -- Single operand extended addressing + -- three byte instruction so advance the PC + -- Low order EA holds high order address + -- + when "0111" => -- extended single op + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + next_state <= extended_state; + + when "1000" => -- acca immediate + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + case op_code(3 downto 0) is + when "0011" | -- subdd # + "1100" | -- cpx # + "1110" => -- lds # + next_state <= immediate16_state; + when "1101" => -- bsr + next_state <= bsr_state; + when others => + next_state <= fetch_state; + end case; + + when "1001" => -- acca direct + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + pc_ctrl <= inc_pc; + case op_code(3 downto 0) is + when "0111" => -- staa direct + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1111" => -- sts direct + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when "1101" => -- jsr direct + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + next_state <= jsr_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + next_state <= read8_state; + end case; + + when "1010" => -- acca indexed + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + next_state <= indexed_state; + + when "1011" => -- acca extended + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + next_state <= extended_state; + + when "1100" => -- accb immediate + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + case op_code(3 downto 0) is + when "0011" | -- addd # + "1100" | -- ldd # + "1110" => -- ldx # + next_state <= immediate16_state; + when others => + next_state <= fetch_state; + end case; + + when "1101" => -- accb direct + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + pc_ctrl <= inc_pc; + case op_code(3 downto 0) is + when "0111" => -- stab direct + left_ctrl <= accb_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1101" => -- std direct + left_ctrl <= accd_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when "1111" => -- stx direct + left_ctrl <= ix_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + next_state <= read8_state; + end case; + + when "1110" => -- accb indexed + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + next_state <= indexed_state; + + when "1111" => -- accb extended + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + next_state <= extended_state; + + when others => + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- idle the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= latch_pc; + next_state <= fetch_state; + end case; + + when immediate16_state => + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + op_ctrl <= latch_op; + iv_ctrl <= latch_iv; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + -- fetch next immediate byte + md_ctrl <= fetch_next_md; + addr_ctrl <= fetch_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + -- + -- ea holds 8 bit index offet + -- calculate the effective memory address + -- using the alu + -- + when indexed_state => + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + -- calculate effective address from index reg + -- index offest is not sign extended + ea_ctrl <= add_ix_ea; + -- idle the bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + -- work out next state + case op_code(7 downto 4) is + when "0110" => -- single op indexed + md_ctrl <= latch_md; + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + case op_code(3 downto 0) is + when "1011" => -- undefined + next_state <= fetch_state; + when "1110" => -- jmp + next_state <= jmp_state; + when others => + next_state <= read8_state; + end case; + when "1010" => -- acca indexed + case op_code(3 downto 0) is + when "0111" => -- staa + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1101" => -- jsr + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= jsr_state; + when "1111" => -- sts + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= read8_state; + end case; + when "1110" => -- accb indexed + case op_code(3 downto 0) is + when "0111" => -- stab direct + left_ctrl <= accb_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1101" => -- std direct + left_ctrl <= accd_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when "1111" => -- stx direct + left_ctrl <= ix_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= read8_state; + end case; + when others => + md_ctrl <= latch_md; + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + next_state <= fetch_state; + end case; + -- + -- ea holds the low byte of the absolute address + -- Move ea low byte into ea high byte + -- load new ea low byte to for absolute 16 bit address + -- advance the program counter + -- + when extended_state => -- fetch ea low byte + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + -- increment pc + pc_ctrl <= inc_pc; + -- fetch next effective address bytes + ea_ctrl <= fetch_next_ea; + addr_ctrl <= fetch_ad; + dout_ctrl <= md_lo_dout; + -- work out the next state + case op_code(7 downto 4) is + when "0111" => -- single op extended + md_ctrl <= latch_md; + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + case op_code(3 downto 0) is + when "1011" => -- undefined + next_state <= fetch_state; + when "1110" => -- jmp + next_state <= jmp_state; + when others => + next_state <= read8_state; + end case; + when "1011" => -- acca extended + case op_code(3 downto 0) is + when "0111" => -- staa + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1101" => -- jsr + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= jsr_state; + when "1111" => -- sts + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= read8_state; + end case; + when "1111" => -- accb extended + case op_code(3 downto 0) is + when "0111" => -- stab + left_ctrl <= accb_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1101" => -- std + left_ctrl <= accd_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when "1111" => -- stx + left_ctrl <= ix_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= read8_state; + end case; + when others => + md_ctrl <= latch_md; + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + next_state <= fetch_state; + end case; + -- + -- here if ea holds low byte (direct page) + -- can enter here from extended addressing + -- read memory location + -- note that reads may be 8 or 16 bits + -- + when read8_state => -- read data + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + -- + addr_ctrl <= read_ad; + dout_ctrl <= md_lo_dout; + case op_code(7 downto 4) is + when "0110" | "0111" => -- single operand + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + ea_ctrl <= latch_ea; + next_state <= execute_state; + + when "1001" | "1010" | "1011" => -- acca + case op_code(3 downto 0) is + when "0011" | -- subd + "1110" | -- lds + "1100" => -- cpx + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + -- increment the effective address in case of 16 bit load + ea_ctrl <= inc_ea; + next_state <= read16_state; +-- when "0111" => -- staa +-- left_ctrl <= acca_left; +-- right_ctrl <= zero_right; +-- alu_ctrl <= alu_st8; +-- cc_ctrl <= latch_cc; +-- md_ctrl <= load_md; +-- ea_ctrl <= latch_ea; +-- next_state <= write8_state; +-- when "1101" => -- jsr +-- left_ctrl <= acca_left; +-- right_ctrl <= zero_right; +-- alu_ctrl <= alu_nop; +-- cc_ctrl <= latch_cc; +-- md_ctrl <= latch_md; +-- ea_ctrl <= latch_ea; +-- next_state <= jsr_state; +-- when "1111" => -- sts +-- left_ctrl <= sp_left; +-- right_ctrl <= zero_right; +-- alu_ctrl <= alu_st16; +-- cc_ctrl <= latch_cc; +-- md_ctrl <= load_md; +-- ea_ctrl <= latch_ea; +-- next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + ea_ctrl <= latch_ea; + next_state <= fetch_state; + end case; + + when "1101" | "1110" | "1111" => -- accb + case op_code(3 downto 0) is + when "0011" | -- addd + "1100" | -- ldd + "1110" => -- ldx + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + -- increment the effective address in case of 16 bit load + ea_ctrl <= inc_ea; + next_state <= read16_state; +-- when "0111" => -- stab +-- left_ctrl <= accb_left; +-- right_ctrl <= zero_right; +-- alu_ctrl <= alu_st8; +-- cc_ctrl <= latch_cc; +-- md_ctrl <= load_md; +-- ea_ctrl <= latch_ea; +-- next_state <= write8_state; +-- when "1101" => -- std +-- left_ctrl <= accd_left; +-- right_ctrl <= zero_right; +-- alu_ctrl <= alu_st16; +-- cc_ctrl <= latch_cc; +-- md_ctrl <= load_md; +-- ea_ctrl <= latch_ea; +-- next_state <= write16_state; +-- when "1111" => -- stx +-- left_ctrl <= ix_left; +-- right_ctrl <= zero_right; +-- alu_ctrl <= alu_st16; +-- cc_ctrl <= latch_cc; +-- md_ctrl <= load_md; +-- ea_ctrl <= latch_ea; +-- next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + ea_ctrl <= latch_ea; + next_state <= execute_state; + end case; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + ea_ctrl <= latch_ea; + next_state <= fetch_state; + end case; + + when read16_state => -- read second data byte from ea + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- idle the effective address + ea_ctrl <= latch_ea; + -- read the low byte of the 16 bit data + md_ctrl <= fetch_next_md; + addr_ctrl <= read_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + -- + -- 16 bit Write state + -- write high byte of ALU output. + -- EA hold address of memory to write to + -- Advance the effective address in ALU + -- + when write16_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + -- increment the effective address + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ea_ctrl <= inc_ea; + -- write the ALU hi byte to ea + addr_ctrl <= write_ad; + dout_ctrl <= md_hi_dout; + next_state <= write8_state; + -- + -- 8 bit write + -- Write low 8 bits of ALU output + -- + when write8_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- idle the ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- write ALU low byte output + addr_ctrl <= write_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + + when jmp_state => + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- load PC with effective address + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= load_ea_pc; + -- idle the bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + + when jsr_state => -- JSR + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write pc low + addr_ctrl <= push_ad; + dout_ctrl <= pc_lo_dout; + next_state <= jsr1_state; + + when jsr1_state => -- JSR + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write pc hi + addr_ctrl <= push_ad; + dout_ctrl <= pc_hi_dout; + next_state <= jmp_state; + + when branch_state => -- Bcc + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- calculate signed branch + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= add_ea_pc; + -- idle the bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + + when bsr_state => -- BSR + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write pc low + addr_ctrl <= push_ad; + dout_ctrl <= pc_lo_dout; + next_state <= bsr1_state; + + when bsr1_state => -- BSR + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write pc hi + addr_ctrl <= push_ad; + dout_ctrl <= pc_hi_dout; + next_state <= branch_state; + + when rts_hi_state => -- RTS + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment the sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- read pc hi + pc_ctrl <= pull_hi_pc; + addr_ctrl <= pull_ad; + dout_ctrl <= pc_hi_dout; + next_state <= rts_lo_state; + + when rts_lo_state => -- RTS1 + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- idle the ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- read pc low + pc_ctrl <= pull_lo_pc; + addr_ctrl <= pull_ad; + dout_ctrl <= pc_lo_dout; + next_state <= fetch_state; + + when mul_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- move acca to md + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mulea_state; + + when mulea_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + md_ctrl <= latch_md; + -- idle ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- move accb to ea + ea_ctrl <= load_accb_ea; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= muld_state; + + when muld_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + md_ctrl <= latch_md; + -- clear accd + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_ld8; + cc_ctrl <= latch_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul0_state; + + when mul0_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 0 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(0) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul1_state; + + when mul1_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 1 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(1) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul2_state; + + when mul2_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 2 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(2) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul3_state; + + when mul3_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 3 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(3) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul4_state; + + when mul4_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 4 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(4) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul5_state; + + when mul5_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 5 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(5) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul6_state; + + when mul6_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 6 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(6) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul7_state; + + when mul7_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 7 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(7) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + + when execute_state => -- execute single operand instruction + -- default + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + case op_code(7 downto 4) is + when "0110" | -- indexed single op + "0111" => -- extended single op + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + ea_ctrl <= latch_ea; + -- idle the bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + left_ctrl <= md_left; + case op_code(3 downto 0) is + when "0000" => -- neg + right_ctrl <= zero_right; + alu_ctrl <= alu_neg; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "0011" => -- com + right_ctrl <= zero_right; + alu_ctrl <= alu_com; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "0100" => -- lsr + right_ctrl <= zero_right; + alu_ctrl <= alu_lsr8; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "0110" => -- ror + right_ctrl <= zero_right; + alu_ctrl <= alu_ror8; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "0111" => -- asr + right_ctrl <= zero_right; + alu_ctrl <= alu_asr8; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1000" => -- asl + right_ctrl <= zero_right; + alu_ctrl <= alu_asl8; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1001" => -- rol + right_ctrl <= zero_right; + alu_ctrl <= alu_rol8; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1010" => -- dec + right_ctrl <= plus_one_right; + alu_ctrl <= alu_dec; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1011" => -- undefined + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= fetch_state; + when "1100" => -- inc + right_ctrl <= plus_one_right; + alu_ctrl <= alu_inc; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1101" => -- tst + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= load_cc; + md_ctrl <= latch_md; + next_state <= fetch_state; + when "1110" => -- jmp + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= fetch_state; + when "1111" => -- clr + right_ctrl <= zero_right; + alu_ctrl <= alu_clr; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when others => + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= fetch_state; + end case; + + when others => + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + ea_ctrl <= latch_ea; + -- idle the bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + end case; + + when psha_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write acca + addr_ctrl <= push_ad; + dout_ctrl <= acca_dout; + next_state <= fetch_state; + + when pula_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- idle sp + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + sp_ctrl <= latch_sp; + -- read acca + acca_ctrl <= pull_acca; + addr_ctrl <= pull_ad; + dout_ctrl <= acca_dout; + next_state <= fetch_state; + + when pshb_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write accb + addr_ctrl <= push_ad; + dout_ctrl <= accb_dout; + next_state <= fetch_state; + + when pulb_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- idle sp + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + sp_ctrl <= latch_sp; + -- read accb + accb_ctrl <= pull_accb; + addr_ctrl <= pull_ad; + dout_ctrl <= accb_dout; + next_state <= fetch_state; + + when pshx_lo_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write ix low + addr_ctrl <= push_ad; + dout_ctrl <= ix_lo_dout; + next_state <= pshx_hi_state; + + when pshx_hi_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write ix hi + addr_ctrl <= push_ad; + dout_ctrl <= ix_hi_dout; + next_state <= fetch_state; + + when pulx_hi_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- pull ix hi + ix_ctrl <= pull_hi_ix; + addr_ctrl <= pull_ad; + dout_ctrl <= ix_hi_dout; + next_state <= pulx_lo_state; + + when pulx_lo_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- idle sp + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + sp_ctrl <= latch_sp; + -- read ix low + ix_ctrl <= pull_lo_ix; + addr_ctrl <= pull_ad; + dout_ctrl <= ix_lo_dout; + next_state <= fetch_state; + + -- + -- return from interrupt + -- enter here from bogus interrupts + -- + when rti_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- idle address bus + cc_ctrl <= latch_cc; + addr_ctrl <= idle_ad; + dout_ctrl <= cc_dout; + next_state <= rti_cc_state; + + when rti_cc_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- read cc + cc_ctrl <= pull_cc; + addr_ctrl <= pull_ad; + dout_ctrl <= cc_dout; + next_state <= rti_accb_state; + + when rti_accb_state => + -- default registers + acca_ctrl <= latch_acca; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- read accb + accb_ctrl <= pull_accb; + addr_ctrl <= pull_ad; + dout_ctrl <= accb_dout; + next_state <= rti_acca_state; + + when rti_acca_state => + -- default registers + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- read acca + acca_ctrl <= pull_acca; + addr_ctrl <= pull_ad; + dout_ctrl <= acca_dout; + next_state <= rti_ixh_state; + + when rti_ixh_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- read ix hi + ix_ctrl <= pull_hi_ix; + addr_ctrl <= pull_ad; + dout_ctrl <= ix_hi_dout; + next_state <= rti_ixl_state; + + when rti_ixl_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- read ix low + ix_ctrl <= pull_lo_ix; + addr_ctrl <= pull_ad; + dout_ctrl <= ix_lo_dout; + next_state <= rti_pch_state; + + when rti_pch_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- pull pc hi + pc_ctrl <= pull_hi_pc; + addr_ctrl <= pull_ad; + dout_ctrl <= pc_hi_dout; + next_state <= rti_pcl_state; + + when rti_pcl_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- idle sp + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + sp_ctrl <= latch_sp; + -- pull pc low + pc_ctrl <= pull_lo_pc; + addr_ctrl <= pull_ad; + dout_ctrl <= pc_lo_dout; + next_state <= fetch_state; + + -- + -- here on interrupt + -- iv register hold interrupt type + -- + when int_pcl_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write pc low + addr_ctrl <= push_ad; + dout_ctrl <= pc_lo_dout; + next_state <= int_pch_state; + + when int_pch_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write pc hi + addr_ctrl <= push_ad; + dout_ctrl <= pc_hi_dout; + next_state <= int_ixl_state; + + when int_ixl_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write ix low + addr_ctrl <= push_ad; + dout_ctrl <= ix_lo_dout; + next_state <= int_ixh_state; + + when int_ixh_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write ix hi + addr_ctrl <= push_ad; + dout_ctrl <= ix_hi_dout; + next_state <= int_acca_state; + + when int_acca_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write acca + addr_ctrl <= push_ad; + dout_ctrl <= acca_dout; + next_state <= int_accb_state; + + + when int_accb_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write accb + addr_ctrl <= push_ad; + dout_ctrl <= accb_dout; + next_state <= int_cc_state; + + when int_cc_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write cc + addr_ctrl <= push_ad; + dout_ctrl <= cc_dout; + nmi_ctrl <= latch_nmi; + -- + -- nmi is edge triggered + -- nmi_req is cleared when nmi goes low. + -- + if nmi_req = '1' then + iv_ctrl <= nmi_iv; + next_state <= vect_hi_state; + else + -- + -- IRQ is level sensitive + -- + if (irq = '1') and (cc(IBIT) = '0') then + iv_ctrl <= irq_iv; + next_state <= int_mask_state; + else + case op_code is + when "00111110" => -- WAI (wait for interrupt) + iv_ctrl <= latch_iv; + next_state <= int_wai_state; + when "00111111" => -- SWI (Software interrupt) + iv_ctrl <= swi_iv; + next_state <= vect_hi_state; + when others => -- bogus interrupt (return) + iv_ctrl <= latch_iv; + next_state <= rti_state; + end case; + end if; + end if; + + when int_wai_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + op_ctrl <= latch_op; + ea_ctrl <= latch_ea; + -- enable interrupts + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_cli; + cc_ctrl <= load_cc; + sp_ctrl <= latch_sp; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= cc_dout; + if (nmi_req = '1') and (nmi_ack='0') then + iv_ctrl <= nmi_iv; + nmi_ctrl <= set_nmi; + next_state <= vect_hi_state; + else + -- + -- nmi request is not cleared until nmi input goes low + -- + if (nmi_req = '0') and (nmi_ack='1') then + nmi_ctrl <= reset_nmi; + else + nmi_ctrl <= latch_nmi; + end if; + -- + -- IRQ is level sensitive + -- + if (irq = '1') and (cc(IBIT) = '0') then + iv_ctrl <= irq_iv; + next_state <= int_mask_state; + else + iv_ctrl <= latch_iv; + next_state <= int_wai_state; + end if; + end if; + + when int_mask_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- Mask IRQ + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_sei; + cc_ctrl <= load_cc; + sp_ctrl <= latch_sp; + -- idle bus cycle + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= vect_hi_state; + + when halt_state => -- halt CPU. + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- do nothing in ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- idle bus cycle + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + if halt = '1' then + next_state <= halt_state; + else + next_state <= fetch_state; + end if; + + when others => -- error state halt on undefine states + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- do nothing in ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- idle bus cycle + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= error_state; + end case; +end process; + +-------------------------------- +-- +-- state machine +-- +-------------------------------- + +change_state: process( clk, rst, state, hold ) +begin + if clk'event and clk = '0' then + if rst = '1' then + state <= reset_state; + elsif hold = '1' then + state <= state; + else + state <= next_state; + end if; + end if; +end process; + -- output + +end CPU_ARCH; + diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/dpram.vhd b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..284194c5 --- /dev/null +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/dpram.vhd @@ -0,0 +1,81 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- dpram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity dpram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk_a : in std_logic; + we_a : in std_logic := '0'; + addr_a : in std_logic_vector((aWidth-1) downto 0); + d_a : in std_logic_vector((dWidth-1) downto 0) := (others => '0'); + q_a : out std_logic_vector((dWidth-1) downto 0); + + clk_b : in std_logic; + we_b : in std_logic := '0'; + addr_b : in std_logic_vector((aWidth-1) downto 0); + d_b : in std_logic_vector((dWidth-1) downto 0) := (others => '0'); + q_b : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of dpram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; + signal addr_a_reg: std_logic_vector((aWidth-1) downto 0); + signal addr_b_reg: std_logic_vector((aWidth-1) downto 0); +begin + +-- ----------------------------------------------------------------------- + process(clk_a) + begin + if rising_edge(clk_a) then + if we_a = '1' then + ram(to_integer(unsigned(addr_a))) <= d_a; + end if; + q_a <= ram(to_integer(unsigned(addr_a))); + end if; + end process; + + process(clk_b) + begin + if rising_edge(clk_b) then + if we_b = '1' then + ram(to_integer(unsigned(addr_b))) <= d_b; + end if; + q_b <= ram(to_integer(unsigned(addr_b))); + end if; + end process; + +end architecture; + diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/gen_ram.vhd b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/gen_ram.vhd new file mode 100644 index 00000000..f1a95608 --- /dev/null +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/gen_ram.vhd @@ -0,0 +1,84 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- gen_rwram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity gen_ram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk : in std_logic; + we : in std_logic; + addr : in std_logic_vector((aWidth-1) downto 0); + d : in std_logic_vector((dWidth-1) downto 0); + q : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of gen_ram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; + + signal rAddrReg : std_logic_vector((aWidth-1) downto 0); + signal qReg : std_logic_vector((dWidth-1) downto 0); +begin +-- ----------------------------------------------------------------------- +-- Signals to entity interface +-- ----------------------------------------------------------------------- +-- q <= qReg; + +-- ----------------------------------------------------------------------- +-- Memory write +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if we = '1' then + ram(to_integer(unsigned(addr))) <= d; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Memory read +-- ----------------------------------------------------------------------- +process(clk) + begin + if rising_edge(clk) then +-- qReg <= ram(to_integer(unsigned(rAddrReg))); +-- rAddrReg <= addr; +---- qReg <= ram(to_integer(unsigned(addr))); + q <= ram(to_integer(unsigned(addr))); + end if; + end process; +--q <= ram(to_integer(unsigned(addr))); +end architecture; + diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/moon_patrol_sound_board.vhd b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/moon_patrol_sound_board.vhd new file mode 100644 index 00000000..509e1825 --- /dev/null +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/moon_patrol_sound_board.vhd @@ -0,0 +1,428 @@ +--------------------------------------------------------------------------------- +-- Moon patrol sound board by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- gen_ram.vhd +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- cpu68 - Version 9th Jan 2004 0.8 +-- 6800/01 compatible CPU core +-- GNU public license - December 2002 : John E. Kent +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- Version 0.0 -- 24/11/2017 -- +-- initial version +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity moon_patrol_sound_board is +port( + clock_E : in std_logic; -- 3.58 Mhz/4 + areset : in std_logic; + + select_sound : in std_logic_vector(7 downto 0); + audio_out : out std_logic_vector(11 downto 0); + + rom_addr : out std_logic_vector(12 downto 0); + rom_do : in std_logic_vector( 7 downto 0); + + dbg_cpu_addr : out std_logic_vector(15 downto 0) +); +end moon_patrol_sound_board; + +architecture struct of moon_patrol_sound_board is + component YM2149 + port ( + CLK : in std_logic; + CE : in std_logic; + RESET : in std_logic; + A8 : in std_logic := '1'; + A9_L : in std_logic := '0'; + BDIR : in std_logic; -- Bus Direction (0 - read , 1 - write) + BC : in std_logic; -- Bus control + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + CHANNEL_A : out std_logic_vector(7 downto 0); + CHANNEL_B : out std_logic_vector(7 downto 0); + CHANNEL_C : out std_logic_vector(7 downto 0); + + SEL : in std_logic; + MODE : in std_logic; + + ACTIVE : out std_logic_vector(5 downto 0); + + IOA_in : in std_logic_vector(7 downto 0); + IOA_out : out std_logic_vector(7 downto 0); + + IOB_in : in std_logic_vector(7 downto 0); + IOB_out : out std_logic_vector(7 downto 0) + ); + end component; + + signal reset : std_logic := '1'; + signal reset_cnt : integer range 0 to 1000000 := 1000000; + + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_rw : std_logic; + signal cpu_irq : std_logic; + signal cpu_nmi : std_logic; + + signal irqraz_cs : std_logic; + signal irqraz_we : std_logic; + + signal wram_cs : std_logic; + signal wram_we : std_logic; + signal wram_do : std_logic_vector( 7 downto 0); + + signal rom_cs : std_logic; +-- signal rom_do : std_logic_vector( 7 downto 0); + + signal ay1_chan_a : std_logic_vector(7 downto 0); + signal ay1_chan_b : std_logic_vector(7 downto 0); + signal ay1_chan_c : std_logic_vector(7 downto 0); + signal ay1_do : std_logic_vector(7 downto 0); + signal ay1_audio : std_logic_vector(9 downto 0); + signal ay1_port_b_do : std_logic_vector(7 downto 0); + + signal ay2_chan_a : std_logic_vector(7 downto 0); + signal ay2_chan_b : std_logic_vector(7 downto 0); + signal ay2_chan_c : std_logic_vector(7 downto 0); + signal ay2_do : std_logic_vector(7 downto 0); + signal ay2_audio : std_logic_vector(9 downto 0); + + signal ports_cs : std_logic; + signal ports_we : std_logic; + + signal port1_bus : std_logic_vector(7 downto 0); + signal port1_data : std_logic_vector(7 downto 0); + signal port1_ddr : std_logic_vector(7 downto 0); + signal port1_in : std_logic_vector(7 downto 0); + + signal port2_bus : std_logic_vector(7 downto 0); + signal port2_data : std_logic_vector(7 downto 0); + signal port2_ddr : std_logic_vector(7 downto 0); + signal port2_in : std_logic_vector(7 downto 0); + + signal adpcm_cs : std_logic; + signal adpcm_we : std_logic; + signal adpcm_0_di : std_logic_vector(3 downto 0); + + signal select_sound_r : std_logic_vector(7 downto 0); + + signal audio : std_logic_vector(12 downto 0); + + type t_step_size is array(0 to 48) of integer range 0 to 1552; + constant step_size : t_step_size := ( + 16, 17, 19, 21, 23, 25, 28, 31, + 34, 37, 41, 45, 50, 55, 60, 66, + 73, 80, 88, 97, 107, 118, 130, 143, + 157, 173, 190, 209, 230, 253, 279, 307, + 337, 371, 408, 449, 494, 544, 598, 658, + 724, 796, 876, 963, 1060, 1166, 1282, 1411, 1552); + + type t_delta_step is array(0 to 7) of integer range -1 to 8; + constant delta_step : t_delta_step := (-1,-1,-1,-1,2,4,6,8); + + signal adpcm_vclk : std_logic := '0'; + signal adpcm_signal : integer range -16384 to 16383 := 0; + +-- adpcm algorithm (4bits) [no pcm here] +-- +-- val : input value 3bits (0 - 7 : b2b1b0) +-- sign : input value sign (4th bit : 0=>sign=1 ,1=>sign=-1) +-- +-- step : internal data, init = 0 +-- signal : output value, init = 0; +-- +-- for each new val (and sign) : +-- | +-- | step_size = 16*1.1^(step) +-- | delta = sign * (step_size/8 + step_size/4*b0 + step_size/2*b1 + step_size*b2) +-- | signal = signal + delta +-- | step = step + delta_step(val) +-- | +-- | signal is then limited between -2048..2047 +-- | step is then limited between 0..48 + +begin + +dbg_cpu_addr <= cpu_addr; + +-- cs +wram_cs <= '1' when cpu_addr(15 downto 7) = X"00"&'1' else '0'; -- 0080-00FF +ports_cs <= '1' when cpu_addr(15 downto 4) = X"000" else '0'; -- 0000-000F +adpcm_cs <= '1' when cpu_addr(14 downto 11) = "0001" else '0'; -- 0800-0FFF / 8800-8FFF +irqraz_cs <= '1' when cpu_addr(14 downto 12) = "001" else '0'; -- 1000-1FFF / 9000-9FFF +rom_cs <= '1' when cpu_addr(14 downto 13) = "11" else '0'; -- 6000-7FFF / E000-FFFF + +-- write enables +wram_we <= '1' when cpu_rw = '0' and wram_cs = '1' else '0'; +ports_we <= '1' when cpu_rw = '0' and ports_cs = '1' else '0'; +adpcm_we <= '1' when cpu_rw = '0' and adpcm_cs = '1' else '0'; +irqraz_we <= '1' when cpu_rw = '0' and irqraz_cs = '1' else '0'; + +-- mux cpu in data between roms/io/wram +cpu_di <= + wram_do when wram_cs = '1' else + port1_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"0" else + port2_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"1" else + port1_in when ports_cs = '1' and cpu_addr(3 downto 0) = X"2" else + port2_in when ports_cs = '1' and cpu_addr(3 downto 0) = X"3" else + rom_do when rom_cs = '1' else X"55"; + +process (clock_E) +begin + if rising_edge(clock_E) then + reset <= '0'; + if reset_cnt /= 0 then + reset_cnt <= reset_cnt - 1; + reset <= '1'; + end if; + if areset = '1' then + reset_cnt <= 1000000; + end if; + end if; +end process; + +-- irq to cpu +process (reset, clock_E) +begin + if reset='1' then + cpu_irq <= '0'; + select_sound_r(7) <= '1'; + elsif rising_edge(clock_E) then + select_sound_r <= select_sound; + if select_sound_r(7) = '0' then + cpu_irq <= '1'; + end if; + if irqraz_we = '1' then + cpu_irq <= '0'; + end if; + end if; +end process; + +-- cpu nmi +cpu_nmi <= adpcm_vclk; + +-- 6803 ports 1 and 2 (only) +process (reset, clock_E) +begin + if reset='1' then + port1_ddr <= (others=>'0'); -- port1 set as input + port1_data <= (others=>'0'); -- port1 data set to 0 + port2_ddr <= ("11100000"); -- port2 bit 7 to 5 should always remain output to simulate mode data + port2_data <= ("01000000"); -- port2 data bit 7 to 5 set to 2 (for mode 2 at start up) + elsif rising_edge(clock_E) then + if ports_cs = '1' and ports_we = '1' then + if cpu_addr(3 downto 0) = X"0" then port1_ddr <= cpu_do; end if; + if cpu_addr(3 downto 0) = X"1" then port2_ddr <= cpu_do and "11100000"; end if; + if cpu_addr(3 downto 0) = X"2" then port1_data <= cpu_do; end if; + if cpu_addr(3 downto 0) = X"3" then port2_data <= cpu_do; end if; + end if; + end if; +end process; + +port1_in <= (port1_bus and not(port1_ddr)) or (port1_data and port1_ddr); +port2_in <= (port2_bus and not(port2_ddr)) or (port2_data and port2_ddr); + +-- port1 bus mux +port1_bus <= ay1_do when port2_data(4) = '0' else + ay2_do when port2_data(3) = '0' else X"FF"; + +-- port2 bus +port2_bus <= X"FF"; + + +-- latch adpcm (msm5205) data in +process (reset, clock_E) +begin + if reset='1' then + adpcm_0_di <= (others=>'0'); + elsif rising_edge(clock_E) then + if adpcm_cs = '1' and adpcm_we = '1' then + if cpu_addr(1) = '0' then adpcm_0_di <= cpu_do(3 downto 0); end if; + end if; + end if; +end process; + +-- adcpm clocks and computation -- make 24kHz and vclk 8/6/4kHz +adpcm_clocks : process(clock_E, ay1_port_b_do) + variable clock_div_a : integer range 0 to 148 := 0; + variable clock_div_b : integer range 0 to 5 := 0; + variable step : integer range 0 to 48; + variable step_n : integer range -1 to 48+8; + variable sz : integer range 0 to 1552; + variable dn : integer range -32768 to 32767; + variable adpcm_signal_n : integer range -32768 to 32767; +begin + if rising_edge(clock_E) then + if clock_div_a = 37 then -- 24kHz + clock_div_a := 0; + + case ay1_port_b_do(3 downto 2) is + when "00" => if clock_div_b = 5 then clock_div_b := 0; else clock_div_b := clock_div_b +1; end if; -- 4kHz + when "01" => if clock_div_b = 2 then clock_div_b := 0; else clock_div_b := clock_div_b +1; end if; -- 8kHz + when "10" => if clock_div_b = 3 then clock_div_b := 0; else clock_div_b := clock_div_b +1; end if; -- 6kHz + when others => null; + end case; + + if clock_div_b = 0 then adpcm_vclk <= '1'; else adpcm_vclk <= '0'; end if; + else + clock_div_a := clock_div_a + 1; + end if; + + if ay1_port_b_do(0) = '1' then + step := 0; + adpcm_signal <= 0; + else + + if clock_div_b = 0 then + case clock_div_a is + + when 0 => -- it's time to get new nibble (adpcm_0_di) + + sz := step_size(step); + dn := sz/8; + if adpcm_0_di(0) = '1' then dn := dn + sz/4; end if; + if adpcm_0_di(1) = '1' then dn := dn + sz/2; end if; + if adpcm_0_di(2) = '1' then dn := dn + sz ; end if; + + if adpcm_0_di(3) = '1' then + dn := -dn; + end if; + + step_n := step + delta_step(to_integer(unsigned(adpcm_0_di(2 downto 0)))); + + when 4 => + + adpcm_signal_n := adpcm_signal + dn; + + if step_n > 48 then step := 48; else step := step_n; end if; + if step_n < 0 then step := 0; else step := step_n; end if; + + when 8 => + + if adpcm_signal_n > 2040 then adpcm_signal <= 2040; else adpcm_signal <= adpcm_signal_n; end if; + if adpcm_signal_n < -2040 then adpcm_signal <= -2040; else adpcm_signal <= adpcm_signal_n; end if; + + when others => null; + + end case; + end if; + + end if; + end if; +end process; + +-- audio mux +audio <= ("000"&ay1_audio) + ("000"&ay2_audio) + ('0'&std_logic_vector(to_unsigned((adpcm_signal)+2048,12))); +audio_out <= audio(12 downto 1); + +-- microprocessor 6800/01/03 +main_cpu : entity work.cpu68 +port map( + clk => clock_E, -- E clock input (falling edge) + rst => reset, -- reset input (active high) + rw => cpu_rw, -- read not write output + vma => open, -- valid memory address (active high) + address => cpu_addr, -- address bus output + data_in => cpu_di, -- data bus input + data_out => cpu_do, -- data bus output + hold => '0', -- hold input (active high) extend bus cycle + halt => '0', -- halt input (active high) grants DMA + irq => cpu_irq, -- interrupt request input (active high) + nmi => cpu_nmi, -- non maskable interrupt request input (active high) + test_alu => open, + test_cc => open +); + +-- cpu program rom +--cpu_prog_rom : entity work.travusa_sound +--port map( +-- clk => clock_E, +-- addr => cpu_addr(11 downto 0), +-- data => rom_do +--); +rom_addr <= cpu_addr(12 downto 0); + +-- cpu wram +cpu_ram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 7) +port map( + clk => clock_E, + we => wram_we, + addr => cpu_addr(6 downto 0), + d => cpu_do, + q => wram_do +); + + ay83910_inst1: YM2149 + port map ( + CLK => clock_E, + CE => '1', + RESET => reset, + A8 => '1', + A9_L => port2_data(4), + BDIR => port2_data(0), + BC => port2_data(2), + DI => port1_data, + DO => ay1_do, + CHANNEL_A => ay1_chan_a, + CHANNEL_B => ay1_chan_b, + CHANNEL_C => ay1_chan_c, + + SEL => '0', + MODE => '1', + + ACTIVE => open, + + IOA_in => select_sound_r, + IOA_out => open, + + IOB_in => (others => '0'), + IOB_out => ay1_port_b_do + ); + + ay1_audio <= "0000000000" + ay1_chan_a + ay1_chan_b + ay1_chan_c; + + ay83910_inst2: YM2149 + port map ( + CLK => clock_E, + CE => '1', + RESET => reset, + A8 => '1', + A9_L => port2_data(3), + BDIR => port2_data(0), + BC => port2_data(2), + DI => port1_data, + DO => ay2_do, + CHANNEL_A => ay2_chan_a, + CHANNEL_B => ay2_chan_b, + CHANNEL_C => ay2_chan_c, + + SEL => '0', + MODE => '1', + + ACTIVE => open, + + IOA_in => (others => '0'), + IOA_out => open, + + IOB_in => (others => '0'), + IOB_out => open + ); + + ay2_audio <= "0000000000" + ay2_chan_a + ay2_chan_b + ay2_chan_c; + +end struct; \ No newline at end of file diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/pll_mist.vhd b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/pll_mist.vhd new file mode 100644 index 00000000..7afa03b7 --- /dev/null +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/pll_mist.vhd @@ -0,0 +1,397 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll_mist.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll_mist IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll_mist; + + +ARCHITECTURE SYN OF pll_mist IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire6_bv(0 DOWNTO 0) <= "0"; + sub_wire6 <= To_stdlogicvector(sub_wire6_bv); + sub_wire3 <= sub_wire0(0); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + locked <= sub_wire2; + c0 <= sub_wire3; + sub_wire4 <= inclk0; + sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 30, + clk0_duty_cycle => 50, + clk0_multiply_by => 41, + clk0_phase_shift => "0", + clk1_divide_by => 1200, + clk1_duty_cycle => 50, + clk1_multiply_by => 41, + clk1_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll_mist", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire5, + clk => sub_wire0, + locked => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "30" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1200" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "36.900002" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.922500" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "41" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "41" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "36.86400000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.89500000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "30" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "41" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1200" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "41" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/sdram.sv b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/sdram.sv new file mode 100644 index 00000000..baeb7b5e --- /dev/null +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/sdram.sv @@ -0,0 +1,327 @@ +// +// sdram.v +// +// sdram controller implementation for the MiST board +// https://github.com/mist-devel/mist-board +// +// Copyright (c) 2013 Till Harbaum +// Copyright (c) 2019 Gyorgy Szombathelyi +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +module sdram ( + + // interface to the MT48LC16M16 chip + inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus + output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus + output reg SDRAM_DQML, // two byte masks + output reg SDRAM_DQMH, // two byte masks + output reg [1:0] SDRAM_BA, // two banks + output SDRAM_nCS, // a single chip select + output SDRAM_nWE, // write enable + output SDRAM_nRAS, // row address select + output SDRAM_nCAS, // columns address select + + // cpu/chipset interface + input init_n, // init signal after FPGA config to initialize RAM + input clk, // sdram clock + + input port1_req, + output reg port1_ack, + input port1_we, + input [23:1] port1_a, + input [1:0] port1_ds, + input [15:0] port1_d, + output [15:0] port1_q, + + input [15:1] cpu1_addr, + output reg [15:0] cpu1_q, + + input port2_req, + output reg port2_ack, + input port2_we, + input [23:1] port2_a, + input [1:0] port2_ds, + input [15:0] port2_d, + output [15:0] port2_q, + + input [15:1] snd_addr, + output reg [15:0] snd_q +); + +localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz +localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8 +localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved +localparam CAS_LATENCY = 3'd2; // 2/3 allowed +localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed +localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write + +localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; + +// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz +localparam RFRSH_CYCLES = 10'd842; + +// --------------------------------------------------------------------- +// ------------------------ cycle state machine ------------------------ +// --------------------------------------------------------------------- + +/* + SDRAM state machine for 2 bank interleaved access + 1 word burst, CL2 +cmd issued registered + 0 RAS0 cas1 + 1 ras0 + 2 CAS0 data1 returned + 3 RAS1 cas0 + 4 ras1 + 5 CAS1 data0 returned +*/ + +localparam STATE_RAS0 = 3'd0; // first state in cycle +localparam STATE_RAS1 = 3'd3; // Second ACTIVE command after RAS0 + tRRD (15ns) +localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY; // CAS phase - 3 +localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 5 +localparam STATE_READ0 = 3'd0; //STATE_CAS0 + CAS_LATENCY + 1'd1; // 7 +localparam STATE_READ1 = 3'd3; +localparam STATE_LAST = 3'd5; + +reg [2:0] t; + +always @(posedge clk) begin + t <= t + 1'd1; + if (t == STATE_LAST) t <= STATE_RAS0; +end + +// --------------------------------------------------------------------- +// --------------------------- startup/reset --------------------------- +// --------------------------------------------------------------------- + +// wait 1ms (32 8Mhz cycles) after FPGA config is done before going +// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0) +reg [4:0] reset; +reg init = 1'b1; +always @(posedge clk, negedge init_n) begin + if(!init_n) begin + reset <= 5'h1f; + init <= 1'b1; + end else begin + if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1; + init <= !(reset == 0); + end +end + +// --------------------------------------------------------------------- +// ------------------ generate ram control signals --------------------- +// --------------------------------------------------------------------- + +// all possible commands +localparam CMD_INHIBIT = 4'b1111; +localparam CMD_NOP = 4'b0111; +localparam CMD_ACTIVE = 4'b0011; +localparam CMD_READ = 4'b0101; +localparam CMD_WRITE = 4'b0100; +localparam CMD_BURST_TERMINATE = 4'b0110; +localparam CMD_PRECHARGE = 4'b0010; +localparam CMD_AUTO_REFRESH = 4'b0001; +localparam CMD_LOAD_MODE = 4'b0000; + +reg [3:0] sd_cmd; // current command sent to sd ram +reg [15:0] sd_din; +// drive control signals according to current command +assign SDRAM_nCS = sd_cmd[3]; +assign SDRAM_nRAS = sd_cmd[2]; +assign SDRAM_nCAS = sd_cmd[1]; +assign SDRAM_nWE = sd_cmd[0]; + +reg [24:1] addr_latch[2]; +reg [24:1] addr_latch_next[2]; +reg [15:1] addr_last[2]; +reg [15:1] addr_last2[2]; +reg [15:0] din_latch[2]; +reg [1:0] oe_latch; +reg [1:0] we_latch; +reg [1:0] ds[2]; + +localparam PORT_NONE = 2'd0; +localparam PORT_CPU1 = 2'd1; +localparam PORT_REQ = 2'd2; + +localparam PORT_SND = 2'd1; + +reg [2:0] next_port[2]; +reg [2:0] port[2]; +reg port1_state; +reg port2_state; + +reg refresh; +reg [10:0] refresh_cnt; +wire need_refresh = (refresh_cnt >= RFRSH_CYCLES); + +// PORT1: bank 0,1 +always @(*) begin + if (refresh) begin + next_port[0] = PORT_NONE; + addr_latch_next[0] = addr_latch[0]; + end else if (port1_req ^ port1_state) begin + next_port[0] = PORT_REQ; + addr_latch_next[0] = { 1'b0, port1_a }; + end else if (cpu1_addr != addr_last[PORT_CPU1]) begin + next_port[0] = PORT_CPU1; + addr_latch_next[0] = { 9'd0, cpu1_addr }; + end else begin + next_port[0] = PORT_NONE; + addr_latch_next[0] = addr_latch[0]; + end +end + +// PORT2: bank 2,3 +always @(*) begin + if (port2_req ^ port2_state) begin + next_port[1] = PORT_REQ; + addr_latch_next[1] = { 1'b1, port2_a }; + end else if (snd_addr != addr_last2[PORT_SND]) begin + next_port[1] = PORT_SND; + addr_latch_next[1] = { 1'b1, 8'd0, snd_addr }; + end else begin + next_port[1] = PORT_NONE; + addr_latch_next[1] = addr_latch[1]; + end +end + +always @(posedge clk) begin + + // permanently latch ram data to reduce delays + sd_din <= SDRAM_DQ; + SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; + { SDRAM_DQMH, SDRAM_DQML } <= 2'b11; + sd_cmd <= CMD_NOP; // default: idle + refresh_cnt <= refresh_cnt + 1'd1; + + if(init) begin + // initialization takes place at the end of the reset phase + if(t == STATE_RAS0) begin + + if(reset == 15) begin + sd_cmd <= CMD_PRECHARGE; + SDRAM_A[10] <= 1'b1; // precharge all banks + end + + if(reset == 10 || reset == 8) begin + sd_cmd <= CMD_AUTO_REFRESH; + end + + if(reset == 2) begin + sd_cmd <= CMD_LOAD_MODE; + SDRAM_A <= MODE; + SDRAM_BA <= 2'b00; + end + end + end else begin + // RAS phase + // bank 0,1 + if(t == STATE_RAS0) begin + addr_latch[0] <= addr_latch_next[0]; + port[0] <= next_port[0]; + { oe_latch[0], we_latch[0] } <= 2'b00; + + if (next_port[0] != PORT_NONE) begin + port1_state <= port1_req; + sd_cmd <= CMD_ACTIVE; + SDRAM_A <= addr_latch_next[0][22:10]; + SDRAM_BA <= addr_latch_next[0][24:23]; + addr_last[next_port[0]] <= addr_latch_next[0][15:1]; + if (next_port[0] == PORT_REQ) begin + { oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we }; + ds[0] <= port1_ds; + din_latch[0] <= port1_d; + end else begin + { oe_latch[0], we_latch[0] } <= 2'b10; + ds[0] <= 2'b11; + end + end + end + + // bank 2,3 + if(t == STATE_RAS1) begin + refresh <= 1'b0; + addr_latch[1] <= addr_latch_next[1]; + { oe_latch[1], we_latch[1] } <= 2'b00; + port[1] <= next_port[1]; + + if (next_port[1] != PORT_NONE) begin + port2_state <= port2_req; + sd_cmd <= CMD_ACTIVE; + SDRAM_A <= addr_latch_next[1][22:10]; + SDRAM_BA <= addr_latch_next[1][24:23]; + addr_last2[next_port[1]] <= addr_latch_next[1][15:1]; + if (next_port[1] == PORT_REQ) begin + { oe_latch[1], we_latch[1] } <= { ~port2_we, port2_we }; + ds[1] <= port2_ds; + din_latch[1] <= port2_d; + end else begin + { oe_latch[1], we_latch[1] } <= 2'b10; + ds[1] <= 2'b11; + end + end + + if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin + refresh <= 1'b1; + refresh_cnt <= 0; + sd_cmd <= CMD_AUTO_REFRESH; + end + end + + // CAS phase + if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin + sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ; + { SDRAM_DQMH, SDRAM_DQML } <= ~ds[0]; + if (we_latch[0]) begin + SDRAM_DQ <= din_latch[0]; + port1_ack <= port1_req; + end + SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge + SDRAM_BA <= addr_latch[0][24:23]; + end + + if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin + sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ; + { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1]; + if (we_latch[1]) begin + SDRAM_DQ <= din_latch[1]; + port2_ack <= port2_req; + end + SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge + SDRAM_BA <= addr_latch[1][24:23]; + end + + // Data returned + if(t == STATE_READ0 && oe_latch[0]) begin + case(port[0]) + PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end + PORT_CPU1: begin cpu1_q <= sd_din; end + default: ; + endcase; + end + if(t == STATE_READ1 && oe_latch[1]) begin + case(port[1]) + PORT_REQ: begin port2_q <= sd_din; port2_ack <= port2_req; end + PORT_SND: begin snd_q <= sd_din; end + default: ; + endcase; + end + end +end + +endmodule diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/traverse_usa.vhd b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/traverse_usa.vhd new file mode 100644 index 00000000..ecacd4ab --- /dev/null +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/traverse_usa.vhd @@ -0,0 +1,1006 @@ +--------------------------------------------------------------------------------- +-- Traverse USA by Dar (darfpga@aol.fr) (16/03/2019) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T80/T80se - Version : 0247 +----------------------------- +-- Z80 compatible microprocessor core +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +--------------------------------------------------------------------------------- +-- cpu68 - Version 9th Jan 2004 0.8 +-- 6800/01 compatible CPU core +-- GNU public license - December 2002 : John E. Kent +--------------------------------------------------------------------------------- +-- YM2149 (AY-3-8910) +-- Copyright (c) MikeJ - Jan 2005 +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- + +-- Features : +-- Video : TV 15KHz mode only (atm) +-- Coctail mode : OK +-- Sound : OK + +-- Use with MAME roms from travusa.zip +-- +-- Use make_travusa_proms.bat to build vhd file from binaries +-- (CRC list included) + +-- Traverse USA (irem M52) Hardware caracteristics : +-- +-- VIDEO : 1xZ80@3MHz CPU accessing its program rom, working ram, +-- sprite data ram, I/O, sound board register and trigger. +-- 32Kx8bits program rom +-- +-- One char tile map 64x32 with H scrolling (32x32 visible) +-- 8Kx24bits graphics rom 3bits/pixel +-- 8colors per tile / 16 color sets +-- rbg palette 128 colors 8bits : 2red 3green 3blue +-- +-- 72 sprites / line, 16x16 with flip H/V +-- (schematics seems too allow only 24 sprites / line with bank switch +-- at mid screen. This doesn't allow showing all needed sprite) +-- +-- 8Kx24bits graphics rom 3bits/pixel +-- 8colors per sprite / 32 color sets among 16 colors; +-- rbg palette 16 colors 8bits : 2red 3green 3blue +-- +-- Working ram : 4Kx8bits +-- Sprites data ram : 256x8bits +-- Sprites line buffer rams : 1 scan line delay flip/flop 2x256x4bits +-- +-- SOUND : 1x6803@3.58MHz CPU accessing its program rom, working ram, 2x-AY3-8910, 1xMSM5205 +-- 4Kx8bits program rom +-- 128x8bits working ram +-- +-- 1xAY-3-8910 +-- I/O to MSM5205 and command/trigger from video board. +-- 3 sound channels +-- +-- 1xAY-3-8910 +-- 3 sound channels +-- +--------------------------------------------------------------------------------- +-- Schematics remarks : +-- +-- Frame is 384 x 282 (H x V) which is too much lines for standard TV set (262.5 lines) +-- This create a display artefact near end of frame since already entering composite +-- sync egalisation pulses. Line number cannot be reduced since CPU need enough fly back +-- time to update every sprites position. (Reducing line count will result in missing sprites) +-- May be this can be achieved by increasing CPU clock speed (web site and MAME report 4Mhz) +-- My M52-A schematic clearly shows 18.432/6. +-- +-- => I give more CPU time to access sprite ram data by allowing CPU access as soon as video +-- scanner V is outside the sprite zone i.e. outside the scroling part of screen (which +-- depends on the flip screen state). +-- +-- Moreover M52-B schematic doesn't show to allow seeking more than 24 sprites data per +-- line from : +-- - C820 to C87F for half upper screen (vertical) +-- - C8A0 to C8FF for half lower screen (vertical) +-- +-- But, at beginning of the game, during starting count downto, 5 cars are diplayed + +-- moto + count down numbers. At least some sprite cars data comes not only from +-- C820-C87F but also from C920 to C97F. Which involves at least 2 sprite data regions +-- for the same half part of the screen (see cars numbered 0 and 3). +-- +-- => I modify the sprite data address scanner to allow 3 regions to be scanned at each line +-- (C820-C87F, C8A0-C8FF and C920-C97F). My first design was with a 12MHz master clock to +-- allow 1 read and 1 write access to sprite line buffer ram at each pixel (6Mhz). This +-- permit only one sprite data region to be scanned at each line. The master clock was +-- increased from 12Mhz to 36Mhz and desing modified to allow 3 sprite data regions to be +-- scanned at each line. +-- +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity traverse_usa is +port( + clock_36 : in std_logic; + clock_0p895 : in std_logic; + reset : in std_logic; + + shtrider : in std_logic; -- Shot Rider mode +-- tv15Khz_mode : in std_logic; + video_r : out std_logic_vector(1 downto 0); + video_g : out std_logic_vector(2 downto 0); + video_b : out std_logic_vector(2 downto 0); + video_clk : out std_logic; + video_csync : out std_logic; + video_blankn : out std_logic; + video_hs : out std_logic; + video_vs : out std_logic; + audio_out : out std_logic_vector(10 downto 0); + + dip_switch_1 : in std_logic_vector(7 downto 0); -- Coinage_B(7-4) / Cont. play(3) / Fuel consumption(2) / Fuel lost when collision (1-0) + dip_switch_2 : in std_logic_vector(7 downto 0); -- Diag(7) / Demo(6) / Zippy(5) / Freeze (4) / M-Km(3) / Coin mode (2) / Cocktail(1) / Flip(0) + + start2 : in std_logic; + start1 : in std_logic; + coin1 : in std_logic; + + right1 : in std_logic; + left1 : in std_logic; + accel1 : in std_logic; + brake1 : in std_logic; + + right2 : in std_logic; + left2 : in std_logic; + accel2 : in std_logic; + brake2 : in std_logic; + + cpu_rom_addr : out std_logic_vector(14 downto 0); + cpu_rom_do : in std_logic_vector( 7 downto 0); + cpu_rom_rd : out std_logic; + snd_rom_addr : out std_logic_vector(12 downto 0); + snd_rom_do : in std_logic_vector( 7 downto 0); + + dl_addr : in std_logic_vector(16 downto 0); + dl_data : in std_logic_vector( 7 downto 0); + dl_wr : in std_logic; + + dbg_cpu_addr : out std_logic_vector(15 downto 0) + ); +end traverse_usa; + +architecture struct of traverse_usa is + + signal reset_n: std_logic; + signal clock_36n : std_logic; + signal clock_cnt : std_logic_vector(3 downto 0) := "0000"; + + signal hcnt : std_logic_vector(8 downto 0) := '0'&x"00"; -- horizontal counter + signal vcnt : std_logic_vector(8 downto 0) := '0'&x"00"; -- vertical counter + + signal hcnt_flip : std_logic_vector(8 downto 0); + signal vcnt_flip : std_logic_vector(8 downto 0); + signal hcnt_scrolled : std_logic_vector(8 downto 0); + signal hcnt_scrolled_flip : std_logic_vector(2 downto 0); + + signal pix_ena : std_logic; + + signal csync : std_logic; + signal hsync0 : std_logic; + signal hsync1 : std_logic; + signal hsync2 : std_logic; + + signal hblank : std_logic; + signal vblank : std_logic; + + signal cpu_ena : std_logic; + + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_wr_n : std_logic; + signal cpu_mreq_n : std_logic; + signal cpu_ioreq_n : std_logic; + signal cpu_irq_n : std_logic; + signal cpu_m1_n : std_logic; + +-- signal cpu_rom_do : std_logic_vector( 7 downto 0); + + signal wram_we : std_logic; + signal wram_do : std_logic_vector( 7 downto 0); + + signal vflip : std_logic; + signal flip : std_logic; + signal flip_int : std_logic; + + signal chrram_addr: std_logic_vector(10 downto 0); + signal chrram_we : std_logic; + signal chrram_do : std_logic_vector(7 downto 0); + signal chrram_do_to_cpu : std_logic_vector( 7 downto 0); + + signal scroll_x : std_logic_vector(8 downto 0) := (others=>'0'); + signal apply_scroll : std_logic; + + signal chr_code: std_logic_vector( 7 downto 0); + signal chr_attr: std_logic_vector( 7 downto 0); + signal chr_code_line : std_logic_vector(12 downto 0); + signal chr_flip_h : std_logic; + + signal chr_graphx1_do : std_logic_vector(7 downto 0); + signal chr_graphx2_do : std_logic_vector(7 downto 0); + signal chr_graphx3_do : std_logic_vector(7 downto 0); + signal chr_color : std_logic_vector(3 downto 0); + signal chr_palette_addr : std_logic_vector(7 downto 0); + signal chr_palette_1_do : std_logic_vector(7 downto 0); + signal chr_palette_2_do : std_logic_vector(7 downto 0); + + signal sprram_addr : std_logic_vector(9 downto 0); + signal sprram_we : std_logic; + signal sprram_do : std_logic_vector(7 downto 0); + + signal cpu_has_spr_ram : std_logic; + + signal spr_pix_ena : std_logic; + signal spr_hcnt : std_logic_vector(10 downto 0); + signal spr_posv, spr_posv_r : std_logic_vector( 7 downto 0); + signal spr_attr, spr_attr_r : std_logic_vector( 7 downto 0); + signal spr_code, spr_code_r : std_logic_vector( 7 downto 0); + signal spr_posh : std_logic_vector( 7 downto 0); + + signal spr_vcnt : std_logic_vector( 7 downto 0); + signal spr_on_line : std_logic; + signal spr_on_line_r : std_logic; + signal spr_code_line : std_logic_vector(12 downto 0); + signal spr_line_cnt : std_logic_vector( 4 downto 0); + signal spr_graphx1_do : std_logic_vector( 7 downto 0); + signal spr_graphx2_do : std_logic_vector( 7 downto 0); + signal spr_graphx3_do : std_logic_vector( 7 downto 0); + signal spr_palette_addr : std_logic_vector( 7 downto 0); + signal spr_palette_do : std_logic_vector( 7 downto 0); + signal spr_pixels : std_logic_vector( 4 downto 0); + signal spr_rgb_lut_addr : std_logic_vector( 4 downto 0); + signal spr_rgb_lut_do : std_logic_vector( 7 downto 0); + + signal spr_input_line_addr : std_logic_vector(7 downto 0); + signal spr_input_line_di : std_logic_vector(3 downto 0); + signal spr_input_line_do : std_logic_vector(3 downto 0); + signal spr_input_line_we : std_logic; + + signal spr_output_line_addr : std_logic_vector(7 downto 0); + signal spr_output_line_di : std_logic_vector(3 downto 0); + signal spr_output_line_do : std_logic_vector(3 downto 0); + signal spr_output_line_we : std_logic; + signal spr_buffer_ram1_addr : std_logic_vector(7 downto 0); + signal spr_buffer_ram1_we : std_logic; + signal spr_buffer_ram1_di : std_logic_vector(3 downto 0); + signal spr_buffer_ram1_do : std_logic_vector(3 downto 0); + signal spr_buffer_ram2_addr : std_logic_vector(7 downto 0); + signal spr_buffer_ram2_we : std_logic; + signal spr_buffer_ram2_di : std_logic_vector(3 downto 0); + signal spr_buffer_ram2_do : std_logic_vector(3 downto 0); + + signal sound_cmd : std_logic_vector( 7 downto 0); + signal audio : std_logic_vector(11 downto 0); + + signal input_0 : std_logic_vector(7 downto 0); + signal input_1 : std_logic_vector(7 downto 0); + signal input_2 : std_logic_vector(7 downto 0); + + signal char_graphics_1_we : std_logic; + signal char_graphics_2_we : std_logic; + signal char_graphics_3_we : std_logic; + signal sprite_graphics_1_we : std_logic; + signal sprite_graphics_2_we : std_logic; + signal sprite_graphics_3_we : std_logic; + signal chr_palette_1_we : std_logic; + signal chr_palette_2_we : std_logic; + signal spr_palette_we : std_logic; + signal spr_lut_we : std_logic; + + signal scroll_we : std_logic; + signal scroll_addr : std_logic_vector(8 downto 0); + signal scroll_do : std_logic_vector(7 downto 0); + +begin + +clock_36n <= not clock_36; +reset_n <= not reset; + +-- debug +process (reset, clock_36, cpu_ena, cpu_mreq_n) +begin + if rising_edge(clock_36) and cpu_ena ='1' and cpu_mreq_n ='0' then + dbg_cpu_addr <= cpu_addr; + end if; +end process; + +-- make enables clock from 36MHz +process (clock_36, reset) +begin + if reset='1' then + clock_cnt <= "0000"; + else + if rising_edge(clock_36) then + if clock_cnt = "1011" then + clock_cnt <= "0000"; + else + clock_cnt <= clock_cnt + 1; + end if; + end if; + end if; +end process; + +pix_ena <= '1' when clock_cnt = "0101" or clock_cnt = "1011" else '0'; -- (6MHz) +cpu_ena <= '1' when clock_cnt = "1011" else '0'; -- (3MHz) + +------------------- +-- Video scanner -- +------------------- +-- hcnt [x080..x0FF-x100..x1FF] => 128+256 = 384 pixels, 384/6.144Mhz => 1 line is 62.5us (16.000KHz) +-- vcnt [x0E6..x0FF-x100..x1FF] => 26+256 = 282 lines, 1 frame is 260 x 62.5us = 17.625ms (56.74Hz) + +process (reset, clock_36, pix_ena) +begin + if reset='1' then + hcnt <= (others=>'0'); + vcnt <= '0'&X"FC"; + else + if rising_edge(clock_36) and pix_ena = '1'then + hcnt <= hcnt + 1; + if hcnt = '1'&x"FF" then + hcnt <= '0'&x"80"; + vcnt <= vcnt + 1; + if vcnt = '1'&x"FF" then + vcnt <= '0'&x"E6"; -- from M52 schematics + end if; + end if; + end if; + end if; +end process; + +flip <= flip_int xor dip_switch_2(0); +hcnt_flip <= '0'&hcnt(7 downto 0) when flip ='1' else '0' & not hcnt(7 downto 0); +vflip <= flip xor shtrider; +vcnt_flip <= vcnt when vflip ='1' else not vcnt; + +-------------------- +-- players inputs -- +-------------------- +input_0 <= "1111" & not coin1 & '1' & not start2 & not start1; +input_1 <= not brake1 & '1' & not accel1 & "111" & not left1 & not right1; +input_2 <= not brake2 & '1' & not accel2 & "111" & not left2 & not right2; + +------------------------------------------ +-- cpu data input with address decoding -- +------------------------------------------ +cpu_di <= cpu_rom_do when cpu_addr(15 downto 12) < X"8" else -- 0000-7FFF + chrram_do_to_cpu when cpu_addr(15 downto 12) = X"8" else -- 8000-8FFF + wram_do when cpu_addr(15 downto 12) = X"E" else -- E000-EFFF + input_0 when cpu_addr(15 downto 0) = X"D000" else -- D000 + input_1 when cpu_addr(15 downto 0) = X"D001" else -- D001 + input_2 when cpu_addr(15 downto 0) = X"D002" else -- D002 + dip_switch_1 when cpu_addr(15 downto 0) = X"D003" else -- D003 + dip_switch_2 when cpu_addr(15 downto 0) = X"D004" else -- D004 + X"FF"; + +------------------------------------------------------------------------ +-- Misc registers : interrupt, scroll, cocktail flip, sound trigger +------------------------------------------------------------------------ +process (clock_36, reset) +begin + if reset = '1' then + sound_cmd <= x"00"; + elsif rising_edge(clock_36) then + + if cpu_m1_n = '0' and cpu_ioreq_n = '0' then + cpu_irq_n <= '1'; + else -- lauch irq and end of frame + if ((vcnt = 230 and vflip = '0') or (vcnt = 448 and vflip = '1')) and (hcnt = '0'&X"80") then + cpu_irq_n <= '0'; + end if; + end if; + + if cpu_wr_n = '0' and cpu_addr(15 downto 12) = X"9" then scroll_x(7 downto 0) <= cpu_do; end if; + if cpu_wr_n = '0' and cpu_addr(15 downto 12) = X"A" then scroll_x(8) <= cpu_do(0); end if; + + if cpu_wr_n = '0' and cpu_addr(15 downto 0) = X"D000" then sound_cmd <= cpu_do; end if; + if cpu_wr_n = '0' and cpu_addr(15 downto 0) = X"D001" then flip_int <= cpu_do(0); end if; + + end if; +end process; + +------------------------------------------ +-- write enable to working ram from CPU -- +------------------------------------------ +wram_we <= '1' when cpu_wr_n = '0' and cpu_addr(15 downto 12) = X"E" else '0'; + +---------------------- +--- sprite machine --- +---------------------- +-- 3 regions sprite data scanner +-- 080-1FF => C820-C87F +-- 180-2FF => C8A0-C8FF +-- 280-3FF => C920-C97F +process (clock_36) +begin + if rising_edge(clock_36) then + spr_pix_ena <= not spr_pix_ena; -- (18MHz) + + if hcnt = '1'&x"FF" and pix_ena = '1' then -- synched with hcnt + spr_hcnt <= "000"&x"80"; + spr_pix_ena <= '0'; + else + if spr_pix_ena = '1' then + if spr_hcnt( 8 downto 0) = "1"&x"FF" then + spr_hcnt( 8 downto 0) <= '0'&x"80"; + spr_hcnt(10 downto 9) <= spr_hcnt(10 downto 9) + '1'; + else + spr_hcnt <= spr_hcnt + '1'; + end if; + end if; + end if; + end if; +end process; + +-- CPU allowed to access sprite data ram outside scrolling zone +-- from x080 to x13F when not flipped (scrolling zone from x140 to x1FF) +-- from x080 to x0FF and from x1C0 to x1FF when not flipped (scrolling zone from x100 to x1BF) +-- within scrolling zone sprite data ram is accessed by sprite data scanner (spr_hcnt) + +cpu_has_spr_ram <= '1' when ( vcnt < '1'&x"3F" and vflip = '0') or + ((vcnt > '1'&x"C0" or vcnt < '0'&x"FF") and vflip = '1') else '0'; + +sprram_we <= '1' when cpu_wr_n = '0' and cpu_addr(15 downto 11) = X"C"&"1" and cpu_has_spr_ram = '1' else '0'; + +sprram_addr <= '0' & spr_hcnt(10 downto 4) & spr_hcnt(2 downto 1) when cpu_has_spr_ram = '0' else + cpu_addr(9 downto 0); + +-- latch current sprite data with respect to pixel and hcnt in relation with sprite data ram addressing +process (clock_36) +begin + if rising_edge(clock_36) then + if spr_pix_ena = '1' then + if spr_hcnt(2 downto 0) = "001" then spr_posv <= sprram_do ;end if; + if spr_hcnt(2 downto 0) = "011" then spr_attr <= sprram_do ;end if; + if spr_hcnt(2 downto 0) = "101" then spr_code <= sprram_do ;end if; + if spr_hcnt(2 downto 0) = "111" then + spr_posh <= sprram_do ; + spr_posv_r <= spr_posv; + spr_attr_r <= spr_attr; + spr_code_r <= spr_code; + end if; + end if; + end if; +end process; + +-- compute sprite presence and graphics rom address w.r.t vertical position and v_flip (attr(7)) +-- sprite is also inhibited when outside scrolling zone (cpu_has_spr_ram) +spr_vcnt <= vcnt_flip(7 downto 0) + spr_posv_r - 1 ; +spr_on_line <= '1' when spr_vcnt(7 downto 4) = x"F" and cpu_has_spr_ram = '0' else '0'; +spr_line_cnt <= spr_vcnt(4 downto 0) xor (spr_attr_r(7) & spr_attr_r(7) & spr_attr_r(7) & spr_attr_r(7) & spr_attr_r(7)); +spr_code_line <= spr_code_r & (spr_attr_r(6) xor not spr_hcnt(3)) & spr_line_cnt(3 downto 0) when shtrider = '0' else + spr_code_r & spr_line_cnt(3) & (spr_attr_r(6) xor not spr_hcnt(3)) & spr_line_cnt(2 downto 0); + +-- get and serialise sprite graphics data and w.r.t enable (attr(5)) and h_flip (attr(6)) +-- and compute palette address from graphics bits and color set# +with spr_attr_r(6 downto 5) select +spr_palette_addr(0) <= spr_graphx1_do(to_integer(unsigned(not(spr_hcnt(2 downto 0))))) when "00", + spr_graphx1_do(to_integer(unsigned( (spr_hcnt(2 downto 0))))) when "10", + '0' when others; + +with spr_attr_r(6 downto 5) select +spr_palette_addr(1) <= spr_graphx2_do(to_integer(unsigned(not(spr_hcnt(2 downto 0))))) when "00", + spr_graphx2_do(to_integer(unsigned( (spr_hcnt(2 downto 0))))) when "10", + '0' when others; + +with spr_attr_r(6 downto 5) select +spr_palette_addr(2) <= spr_graphx3_do(to_integer(unsigned(not(spr_hcnt(2 downto 0))))) when "00", + spr_graphx3_do(to_integer(unsigned( (spr_hcnt(2 downto 0))))) when "10", + '0' when others; + +spr_palette_addr(7 downto 3) <= spr_attr_r(4 downto 0); -- color set# + +---------------------------------------------------- +-- manage read/write flip-flop sprite line buffer -- +---------------------------------------------------- + +-- input buffer work at 36Mhz (read previous data before write) +-- sprite data is written to input buffer when not already written (previous data differ from 0000) + +-- buffer data is written back to 0000 (cleared) after read from output buffer +-- output buffer work at normal pixel speed (12Mhz since read previous data before clear) + +-- input/output buffers are swapped (fkip-flop) each other line + +process (clock_36) +begin + if rising_edge(clock_36) then + if spr_pix_ena = '1' then + + spr_on_line_r <= spr_on_line; + + spr_pixels(3 downto 0) <= spr_palette_do(3 downto 0); + spr_pixels(4) <= spr_attr_r(4); -- not used ! + + -- write input buffer at the right place + if spr_hcnt(3 downto 0) = "1000" then + spr_input_line_addr <= spr_posh; + else + spr_input_line_addr <= spr_input_line_addr+1; + end if; + + end if; + + -- read output buffer w.r.t. flip screen (normal/reverse) + if pix_ena = '1' then + if hcnt < '1'&x"09" then + spr_output_line_addr <= X"00"; + else + if flip = '0' then + spr_output_line_addr <= spr_output_line_addr+1; + else + spr_output_line_addr <= spr_output_line_addr-1; + end if; + end if; + + end if; + + -- demux output buffer (flip-flop) + if pix_ena = '0' then + if vcnt(0) = '1'then + spr_output_line_do <= spr_buffer_ram1_do; + else + spr_output_line_do <= spr_buffer_ram2_do; + end if; + end if; + + end if; +end process; + +-- read previous data from input buffer w.r.t. flip-flop +spr_input_line_do <= spr_buffer_ram1_do when vcnt(0) = '0' else spr_buffer_ram2_do; + +-- feed input buffer +spr_input_line_di <= spr_pixels(3 downto 0); +-- keep write data if input buffer is clear +spr_input_line_we <= '1' when spr_on_line_r = '1' and spr_pix_ena = '1' and spr_input_line_do = "0000" else '0'; + +-- feed output buufer (clear) +spr_output_line_di <= "0000"; +-- always clear just after read +spr_output_line_we <= pix_ena; + +-- flip-flop input/output buffers +spr_buffer_ram1_addr <= not(spr_input_line_addr) when vcnt(0) = '0' else spr_output_line_addr; +spr_buffer_ram1_di <= spr_input_line_di when vcnt(0) = '0' else spr_output_line_di; +spr_buffer_ram1_we <= spr_input_line_we when vcnt(0) = '0' else spr_output_line_we; + +spr_buffer_ram2_addr <= not(spr_input_line_addr) when vcnt(0) = '1' else spr_output_line_addr; +spr_buffer_ram2_di <= spr_input_line_di when vcnt(0) = '1' else spr_output_line_di; +spr_buffer_ram2_we <= spr_input_line_we when vcnt(0) = '1' else spr_output_line_we; + +-- feed sprite color lut with sprite output buffer +spr_rgb_lut_addr <= '0' & spr_output_line_do; + +-------------------- +--- char machine --- +-------------------- +-- compute scrolling zone and apply to horizontal scanner +apply_scroll <= not(vcnt_flip(6) and vcnt_flip(7)); +hcnt_scrolled <= hcnt_flip + scroll_x when apply_scroll = '1' else hcnt_flip; +hcnt_scrolled_flip <= hcnt_scrolled(2 downto 0) when flip = '1' else not (hcnt_scrolled(2 downto 0)); + +-- compute ram tile address w.r.t horizontal scanner +-- address char attr at pixel # 0 +-- address char code at pixel # 4 +-- give access to CPU for all other pixels +with hcnt_scrolled_flip(2 downto 0) select +chrram_addr <= vcnt_flip(6 downto 3) & hcnt_scrolled(8 downto 3) & '1' when "000", + vcnt_flip(6 downto 3) & hcnt_scrolled(8 downto 3) & '0' when "100", + cpu_addr(10 downto 0) when others; + +-- write enable to char tile ram from CPU +chrram_we <= '1' when cpu_wr_n = '0' and cpu_addr(15 downto 12) = X"8" and hcnt_scrolled_flip(1 downto 0) /= "00" else '0'; + +-- read char tile ram and manage char graphics +process (clock_36) +begin + if rising_edge(clock_36) then + -- latch ram tile output w.r.t to addressing scheme (attr/code/CPU) + if hcnt_scrolled_flip(2 downto 0) = "000" then + chr_attr <= chrram_do; + end if; + if hcnt_scrolled_flip(1 downto 0) /= "00" then + chrram_do_to_cpu <= chrram_do; + end if; + if hcnt_scrolled_flip(2 downto 0) = "100" then + chr_code <= chrram_do; + end if; + + -- compute graphics rom address and delay char flip and color + if hcnt_scrolled_flip(2 downto 0) = "111" and pix_ena = '1' then + chr_code_line( 2 downto 0) <= vcnt_flip(2 downto 0) xor (chr_attr(4) & chr_attr(4) & chr_attr(4)); + chr_code_line(10 downto 3) <= chr_code; + chr_code_line(12 downto 11) <= chr_attr(7) & chr_attr(6); + chr_flip_h <= chr_attr(5); + chr_color <= chr_attr(3 downto 0); + end if; + + -- get and serialise char graphics data and w.r.t char flip + -- and compute palette address from graphics bits and color set# + if pix_ena = '1' then + chr_palette_addr(6 downto 3) <= chr_color; + chr_palette_addr(7) <= '0'; + if chr_flip_h = '0' then + chr_palette_addr(0) <= chr_graphx1_do(to_integer(unsigned(not(hcnt_scrolled(2 downto 0))))); + chr_palette_addr(1) <= chr_graphx2_do(to_integer(unsigned(not(hcnt_scrolled(2 downto 0))))); + chr_palette_addr(2) <= chr_graphx3_do(to_integer(unsigned(not(hcnt_scrolled(2 downto 0))))); + else + chr_palette_addr(0) <= chr_graphx1_do(to_integer(unsigned(hcnt_scrolled(2 downto 0)))); + chr_palette_addr(1) <= chr_graphx2_do(to_integer(unsigned(hcnt_scrolled(2 downto 0)))); + chr_palette_addr(2) <= chr_graphx3_do(to_integer(unsigned(hcnt_scrolled(2 downto 0)))); + end if; + + end if; + end if; +end process; + +--------------------------- +-- mux char/sprite video -- +--------------------------- +process (clock_36) +begin + if rising_edge(clock_36) then + + if pix_ena = '1' then + -- always give priority to sprite when not 0000 + -- except for char color #6 and #7 of color set#15 + if spr_output_line_do /= "0000" and + (chr_palette_addr(6 downto 0) < "1111110") then + video_r <= spr_rgb_lut_do(7 downto 6); + video_g <= spr_rgb_lut_do(5 downto 3); + video_b <= spr_rgb_lut_do(2 downto 0); + elsif shtrider = '0' then -- 1x8 bit in Traverse USA + video_r <= chr_palette_1_do(7 downto 6); + video_g <= chr_palette_1_do(5 downto 3); + video_b <= chr_palette_1_do(2 downto 0); + else -- 2x4 bit in Shot Rider + video_r <= chr_palette_1_do(3 downto 2); + video_g <= chr_palette_1_do(1 downto 0) & chr_palette_2_do(3); + video_b <= chr_palette_2_do(2 downto 0); + end if; + end if; + + end if; +end process; + +--------------------------------------------------------- +-- Sound board is same as Moon patrol (except CPU rom) -- +--------------------------------------------------------- +moon_patrol_sound_board : entity work.moon_patrol_sound_board +port map( + clock_E => clock_0p895, + areset => reset, + + select_sound => sound_cmd, -- not(key(1)) & sw(6 downto 0), + audio_out => audio, + + rom_addr => snd_rom_addr, + rom_do => snd_rom_do, + + dbg_cpu_addr => open --dbg_cpu_addr +); + + +audio_out <= audio(11 downto 1); + +---------------------------- +-- video syncs and blanks -- +---------------------------- + +video_csync <= csync; + +process(clock_36, pix_ena) + constant hcnt_base : integer := 180; + variable hsync_cnt : std_logic_vector(8 downto 0); + variable vsync_cnt : std_logic_vector(3 downto 0); +begin + +if rising_edge(clock_36) and pix_ena = '1' then + + if hcnt = hcnt_base then + hsync_cnt := (others=>'0'); + else + hsync_cnt := hsync_cnt + 1; + end if; + + if hsync_cnt = 0 then hsync0 <= '0'; + elsif hsync_cnt = 24 then hsync0 <= '1'; + end if; + + if hsync_cnt = 0 then hsync1 <= '0'; + elsif hsync_cnt = 0+8 then hsync1 <= '1'; + elsif hsync_cnt = 192 then hsync1 <= '0'; + elsif hsync_cnt = 192+8 then hsync1 <= '1'; + end if; + + if hsync_cnt = 0 then hsync2 <= '0'; + elsif hsync_cnt = 192-8 then hsync2 <= '1'; + elsif hsync_cnt = 192 then hsync2 <= '0'; + elsif hsync_cnt = 384-8 then hsync2 <= '1'; + end if; + + if hcnt = hcnt_base then + if vcnt = 238 then + vsync_cnt := X"0"; + else + if vsync_cnt < X"F" then vsync_cnt := vsync_cnt + 1; end if; + end if; + end if; + + if vsync_cnt = 0 then csync <= hsync1; + elsif vsync_cnt = 1 then csync <= hsync1; + elsif vsync_cnt = 2 then csync <= hsync1; + elsif vsync_cnt = 3 then csync <= hsync2; + elsif vsync_cnt = 4 then csync <= hsync2; + elsif vsync_cnt = 5 then csync <= hsync2; + elsif vsync_cnt = 6 then csync <= hsync1; + elsif vsync_cnt = 7 then csync <= hsync1; + elsif vsync_cnt = 8 then csync <= hsync1; + else csync <= hsync0; + end if; + + -- hcnt : [128-511] 384 pixels + if hcnt = 128 then hblank <= '1'; + elsif hcnt = 272 then hblank <= '0'; + end if; + + -- vcnt : [230-511] 282 lines + if vcnt = 230 then vblank <= '1'; + elsif vcnt = 256 then vblank <= '0'; + end if; + + -- external sync and blank outputs + video_blankn <= not (hblank or vblank); +-- + video_hs <= hsync0; +-- + if vsync_cnt = 0 then video_vs <= '0'; + elsif vsync_cnt = 2 then video_vs <= '1'; + end if; +-- +end if; +end process; + +------------------------------ +-- components & sound board -- +------------------------------ + +-- microprocessor Z80 +cpu : entity work.T80s +generic map(Mode => 0, T2Write => 1, IOWait => 1) +port map( + RESET_n => reset_n, + CLK => clock_36, + CEN => cpu_ena, + WAIT_n => '1', + INT_n => cpu_irq_n, + NMI_n => '1', --cpu_nmi_n, + BUSRQ_n => '1', + M1_n => cpu_m1_n, + MREQ_n => cpu_mreq_n, + IORQ_n => cpu_ioreq_n, + RD_n => open, + WR_n => cpu_wr_n, + RFSH_n => open, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_di, + DO => cpu_do +); + +-- cpu program ROM 0x0000-0x7FFF +--rom_cpu : entity work.travusa_cpu +--port map( +-- clk => clock_36n, +-- addr => cpu_addr(14 downto 0), +-- data => cpu_rom_do +--); +cpu_rom_addr <= cpu_addr(14 downto 0); +cpu_rom_rd <= '1' when cpu_mreq_n = '0' and cpu_addr(15) = '0'; + +-- working RAM 0xE000-0xEFFF +wram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 12) +port map( + clk => clock_36n, + we => wram_we, + addr => cpu_addr(11 downto 0), + d => cpu_do, + q => wram_do +); + +-- char RAM 0x8000-0x91FF +scrollram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 9) +port map( + clk => clock_36n, + we => scroll_we, + addr => scroll_addr, + d => cpu_do, + q => scroll_do +); + +-- scoll RAM 0x9000-0x87FF +chrram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 11) +port map( + clk => clock_36n, + we => chrram_we, + addr => chrram_addr, + d => cpu_do, + q => chrram_do +); + +-- sprite RAM 0xC800-0xCBFF +sprite_ram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 10) +port map( + clk => clock_36n, + we => sprram_we, + addr => sprram_addr, + d => cpu_do, + q => sprram_do +); + +-- sprite line buffer 1 +sprlinebuf1 : entity work.gen_ram +generic map( dWidth => 4, aWidth => 8) +port map( + clk => clock_36n, + we => spr_buffer_ram1_we, + addr => spr_buffer_ram1_addr, + d => spr_buffer_ram1_di, + q => spr_buffer_ram1_do +); + +-- sprite line buffer 2 +sprlinebuf2 : entity work.gen_ram +generic map( dWidth => 4, aWidth => 8) +port map( + clk => clock_36n, + we => spr_buffer_ram2_we, + addr => spr_buffer_ram2_addr, + d => spr_buffer_ram2_di, + q => spr_buffer_ram2_do +); + +-- char graphics ROM 3E +char_graphics_1 : entity work.dpram +generic map( dWidth => 8, aWidth => 13) +port map( + clk_a => clock_36n, + addr_a => chr_code_line, + q_a => chr_graphx1_do, + clk_b => clock_36, + we_b => char_graphics_1_we, + addr_b => dl_addr(12 downto 0), + d_b => dl_data +); +char_graphics_1_we <= '1' when dl_addr(16 downto 13) = "0101" and dl_wr = '1' else '0'; -- 0A000-0BFFF + +-- char graphics ROM 3E +char_graphics_2 : entity work.dpram +generic map( dWidth => 8, aWidth => 13) +port map( + clk_a => clock_36n, + addr_a => chr_code_line, + q_a => chr_graphx2_do, + clk_b => clock_36, + we_b => char_graphics_2_we, + addr_b => dl_addr(12 downto 0), + d_b => dl_data +); +char_graphics_2_we <= '1' when dl_addr(16 downto 13) = "0110" and dl_wr = '1' else '0'; -- 0C000-0DFFF + +-- char graphics ROM 3E +char_graphics_3 : entity work.dpram +generic map( dWidth => 8, aWidth => 13) +port map( + clk_a => clock_36n, + addr_a => chr_code_line, + q_a => chr_graphx3_do, + clk_b => clock_36, + we_b => char_graphics_3_we, + addr_b => dl_addr(12 downto 0), + d_b => dl_data +); +char_graphics_3_we <= '1' when dl_addr(16 downto 13) = "0111" and dl_wr = '1' else '0'; -- 0E000-0FFFF + +--char palette ROM +char_palette_1 : entity work.dpram +generic map( dWidth => 8, aWidth => 8) +port map( + clk_a => clock_36n, + addr_a => chr_palette_addr, + q_a => chr_palette_1_do, + clk_b => clock_36, + we_b => chr_palette_1_we, + addr_b => dl_addr(7 downto 0), + d_b => dl_data +); +chr_palette_1_we <= '1' when dl_addr(16 downto 8) = "101100000" and dl_wr = '1' else '0'; -- 16000-160FF + +char_palette_2 : entity work.dpram +generic map( dWidth => 8, aWidth => 8) +port map( + clk_a => clock_36n, + addr_a => chr_palette_addr, + q_a => chr_palette_2_do, + clk_b => clock_36, + we_b => chr_palette_2_we, + addr_b => dl_addr(7 downto 0), + d_b => dl_data +); +chr_palette_2_we <= '1' when dl_addr(16 downto 8) = "101100001" and dl_wr = '1' else '0'; -- 16100-161FF + +-- sprite graphics ROM 3N +sprite_graphics_1 : entity work.dpram +generic map( dWidth => 8, aWidth => 13) +port map( + clk_a => clock_36n, + addr_a => spr_code_line, + q_a => spr_graphx1_do, + clk_b => clock_36, + we_b => sprite_graphics_1_we, + addr_b => dl_addr(12 downto 0), + d_b => dl_data +); +sprite_graphics_1_we <= '1' when dl_addr(16 downto 13) = "1000" and dl_wr = '1' else '0'; -- 10000-11FFF + +-- sprite graphics ROM 3L or 3M +sprite_graphics_2 : entity work.dpram +generic map( dWidth => 8, aWidth => 13) +port map( + clk_a => clock_36n, + addr_a => spr_code_line, + q_a => spr_graphx2_do, + clk_b => clock_36, + we_b => sprite_graphics_2_we, + addr_b => dl_addr(12 downto 0), + d_b => dl_data +); +sprite_graphics_2_we <= '1' when dl_addr(16 downto 13) = "1001" and dl_wr = '1' else '0'; -- 12000-13FFF + +-- sprite graphics ROM 3K +sprite_graphics_3 : entity work.dpram +generic map( dWidth => 8, aWidth => 13) +port map( + clk_a => clock_36n, + addr_a => spr_code_line, + q_a => spr_graphx3_do, + clk_b => clock_36, + we_b => sprite_graphics_3_we, + addr_b => dl_addr(12 downto 0), + d_b => dl_data +); +sprite_graphics_3_we <= '1' when dl_addr(16 downto 13) = "1010" and dl_wr = '1' else '0'; -- 14000-15FFF + +-- sprite palette ROM 2H +spr_palette : entity work.dpram +generic map( dWidth => 8, aWidth => 8) +port map( + clk_a => clock_36n, + addr_a => spr_palette_addr, + q_a => spr_palette_do, + clk_b => clock_36, + we_b => spr_palette_we, + addr_b => dl_addr(7 downto 0), + d_b => dl_data +); +spr_palette_we <= '1' when dl_addr(16 downto 8) = "101100010" and dl_wr = '1' else '0'; -- 16200-162FF + +-- sprite rgb lut ROM 1F +spr_rgb_lut : entity work.dpram +generic map( dWidth => 8, aWidth => 8) +port map( + clk_a => clock_36n, + addr_a => "000"&spr_rgb_lut_addr, -- extended to 8 bit, prevents segfault of Quartus + q_a => spr_rgb_lut_do, + clk_b => clock_36, + we_b => spr_lut_we, + addr_b => "000"&dl_addr(4 downto 0), + d_b => dl_data, + q_b => open +); +spr_lut_we <= '1' when dl_addr(16 downto 5) = "101100011000" and dl_wr = '1' else '0'; -- 16300-1631F + +end struct; \ No newline at end of file diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/README.txt b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/README.txt index c2d8a065..e7005d27 100644 --- a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/README.txt +++ b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/README.txt @@ -1,3 +1,26 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Spy Hunter port to MiST by Gehstock +-- 16 November 2019 +-- + +SHUNTER.ROM is required at the root of the SD-Card. + +Controls +Joy Keyboard +up up : Accelerate +down down : Decelerate +left left : Left +right right : Right + ESC : Coin +start TAB : VAN +Y Z : Shift +X shift left : Oil +C ctrl left : Smoke +B alt left : Missle +A Space : Gun + + --------------------------------------------------------------------------------- -- DE10_lite Top level for Spy hunter (Midway MCR) by Dar (darfpga@aol.fr) (06/12/2019) -- http://darfpga.blogspot.fr diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/Release/SHUNTER.ROM b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/Release/SHUNTER.ROM new file mode 100644 index 00000000..48a0e6b8 Binary files /dev/null and b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/Release/SHUNTER.ROM differ diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/Release/SpyHunter.rbf b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/Release/SpyHunter.rbf new file mode 100644 index 00000000..a11fcca0 Binary files /dev/null and b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/Release/SpyHunter.rbf differ diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/Release/TURBOTAG.ROM b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/Release/TURBOTAG.ROM deleted file mode 100644 index 4bb2c4c5..00000000 Binary files a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/Release/TURBOTAG.ROM and /dev/null differ diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/TurboTag.qsf b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/TurboTag.qsf index 08c4d8e2..8fd2eabc 100644 --- a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/TurboTag.qsf +++ b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/TurboTag.qsf @@ -214,7 +214,7 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name ENABLE_SIGNALTAP OFF -set_global_assignment -name USE_SIGNALTAP_FILE output_files/reset.stp +set_global_assignment -name USE_SIGNALTAP_FILE output_files/csd.stp set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" @@ -222,22 +222,25 @@ set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON set_global_assignment -name FITTER_EFFORT "STANDARD FIT" set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE ON -set_global_assignment -name SYSTEMVERILOG_FILE rtl/SpyHunter_MiST.sv -set_global_assignment -name VHDL_FILE rtl/spy_hunter.vhd +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF +set_global_assignment -name SYSTEMVERILOG_FILE rtl/TurboTag_MiST.sv +set_global_assignment -name VHDL_FILE rtl/turbo_tag.vhd +set_global_assignment -name VHDL_FILE rtl/turbo_tag_sound_board.vhd +set_global_assignment -name VHDL_FILE rtl/cheap_squeak_deluxe.vhd +set_global_assignment -name VHDL_FILE rtl/turbo_tag_control.vhd set_global_assignment -name VHDL_FILE rtl/ctc_counter.vhd set_global_assignment -name VHDL_FILE rtl/ctc_controler.vhd -set_global_assignment -name VHDL_FILE rtl/spy_hunter_sound_board.vhd -set_global_assignment -name VHDL_FILE rtl/spy_hunter_control.vhd -set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd -set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd -set_global_assignment -name VHDL_FILE rtl/cmos_ram.vhd set_global_assignment -name VHDL_FILE rtl/rom/ttag_ch_bits.vhd set_global_assignment -name VHDL_FILE rtl/rom/ttag_bg_bits_2.vhd set_global_assignment -name VHDL_FILE rtl/rom/ttag_bg_bits_1.vhd set_global_assignment -name VHDL_FILE rtl/rom/midssio_82s123.vhd +set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd +set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd +set_global_assignment -name VHDL_FILE rtl/cmos_ram.vhd set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd +set_global_assignment -name VHDL_FILE ../../../common/IO/pia6821.vhd +set_global_assignment -name QIP_FILE ../../../common/CPU/68000/FX68k/fx68k.qip set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/SpyHunter_MiST.sv b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/TurboTag_MiST.sv similarity index 78% rename from Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/SpyHunter_MiST.sv rename to Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/TurboTag_MiST.sv index 696e991a..7ea851a3 100644 --- a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/SpyHunter_MiST.sv +++ b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/TurboTag_MiST.sv @@ -50,12 +50,10 @@ module SpyHunter_MiST( localparam CONF_STR = { "TURBOTAG;ROM;", "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", "O5,Blend,Off,On;", "O6,Service,Off,On;", - "O7,Swap Joystick,Off,On;", "T0,Reset;", - "V,v1.1.",`BUILD_DATE + "V,v1.0.",`BUILD_DATE }; assign LED = ~ioctl_downl; @@ -75,18 +73,19 @@ pll_mist pll( wire [31:0] status; wire [1:0] buttons; wire [1:0] switches; -wire [7:0] joy_0; -wire [7:0] joy_1; +wire [15:0] joystick_0; +wire [15:0] joystick_1; wire scandoublerD; wire ypbpr; wire [15:0] audio_l, audio_r; +wire [9:0] csd_audio; wire hs, vs, cs; wire blankn; wire [2:0] g, r, b; wire [15:0] rom_addr; wire [15:0] rom_do; -wire [14:0] snd_addr; -wire [15:0] snd_do; +wire [14:1] csd_addr; +wire [15:0] csd_do; wire [14:0] sp_addr; wire [31:0] sp_do; wire ioctl_downl; @@ -109,7 +108,40 @@ data_io data_io( .ioctl_dout ( ioctl_dout ) ); -wire [24:0] sp_ioctl_addr = ioctl_addr - 17'h16000;//e000 +// ROM structure: + +// 0000 - DFFF - Main ROM (8 bit) +// E000 - FFFF - Super Sound board ROM (8 bit) +// 10000 - 17FFF - CSD ROM (16 bit) +// 18000 - Sprite ROMs (32 bit) + +// spy-hunter_cpu_pg0_2-9-84.6d +// spy-hunter_cpu_pg1_2-9-84.7d +// spy-hunter_cpu_pg2_2-9-84.8d +// spy-hunter_cpu_pg3_2-9-84.9d +// spy-hunter_cpu_pg4_2-9-84.10d +// spy-hunter_cpu_pg5_2-9-84.11d + +// spy-hunter_snd_0_sd_11-18-83.a7 +// spy-hunter_snd_1_sd_11-18-83.a8 + +// spy-hunter_cs_deluxe_u17_b_11-18-83.u17 +// spy-hunter_cs_deluxe_u18_d_11-18-83.u18 +// spy-hunter_cs_deluxe_u7_a_11-18-83.u7 +// spy-hunter_cs_deluxe_u8_c_11-18-83.u8 + +// spy-hunter_video_1fg_11-18-83.a7 +// spy-hunter_video_0fg_11-18-83.a8 +// spy-hunter_video_3fg_11-18-83.a5 +// spy-hunter_video_2fg_11-18-83.a6 +// spy-hunter_video_5fg_11-18-83.a3 +// spy-hunter_video_4fg_11-18-83.a4 +// spy-hunter_video_7fg_11-18-83.a1 +// spy-hunter_video_6fg_11-18-83.a2 + +wire [24:0] rom_ioctl_addr = ~ioctl_addr[16] ? ioctl_addr : // 8 bit ROMs + {ioctl_addr[24:16], ioctl_addr[15], ioctl_addr[13:0], ioctl_addr[14]}; // 16 bit ROM +wire [24:0] sp_ioctl_addr = ioctl_addr - 17'h16000; reg port1_req, port2_req; sdram sdram( @@ -117,19 +149,22 @@ sdram sdram( .init_n ( pll_locked ), .clk ( clk_mem ), - // port1 used for main + sound CPU + // port1 used for main + sound CPUs .port1_req ( port1_req ), .port1_ack ( ), - .port1_a ( ioctl_addr[23:1] ), - .port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ), + .port1_a ( rom_ioctl_addr[23:1] ), + .port1_ds ( {rom_ioctl_addr[0], ~rom_ioctl_addr[0]} ), .port1_we ( ioctl_downl ), .port1_d ( {ioctl_dout, ioctl_dout} ), .port1_q ( ), - .cpu1_addr ( ioctl_downl ? 16'hffff : {rom_addr[15:1]} ), + .cpu1_addr ( ioctl_downl ? 16'hffff : {1'b0, rom_addr[15:1]} ), .cpu1_q ( rom_do ), - .cpu2_addr ( 16'hffff),//ioctl_downl ? 16'hffff : (16'h7000 + snd_addr[14:1]) ),// CSD - .cpu2_q ( ),//snd_do ), + // need higher priority for CSD + .cpu2_addr ( ioctl_downl ? 16'hffff : (16'h7000 + csd_addr[14:1]) ), + .cpu2_q ( csd_do ), + .cpu3_addr ( 16'hffff ), + .cpu3_q ( ), // port2 for sprite graphics .port2_req ( port2_req ), @@ -174,7 +209,7 @@ always @(posedge clk_sys) begin end -spy_hunter_control spy_hunter_control( +turbo_tag_control turbo_tagcontrol( .clock_40(clk_sys), .reset(reset), .vsync(vs), @@ -186,7 +221,7 @@ spy_hunter_control spy_hunter_control( .gas(gas) ); -spy_hunter spy_hunter( +turbo_tag turbo_tag( .clock_40(clk_sys), .reset(reset), .video_r(r), @@ -200,24 +235,22 @@ spy_hunter spy_hunter( .separate_audio(1'b0), .audio_out_l(audio_l), .audio_out_r(audio_r), + .csd_audio_out(csd_audio), .coin1(btn_coin), .coin2(1'b0), - - .shift(), - .oil(m_fire4), - .missile(), - .van(m_fire2), - .smoke(m_fire3), - .gun(m_fire1), - - .steering(steering), .gas(gas), - + .steering(steering), + .start1(btn_one_player), + .start2(btn_two_players), + .shift(m_fire1), + .left(m_left), + .center(btn_fire2), + .right(m_right), .service(status[6]), .cpu_rom_addr ( rom_addr ), .cpu_rom_do ( rom_addr[0] ? rom_do[15:8] : rom_do[7:0] ), - .snd_rom_addr ( snd_addr ), - .snd_rom_do ( snd_addr[0] ? snd_do[15:8] : snd_do[7:0] ), + .csd_rom_addr ( csd_addr ), + .csd_rom_do ( csd_do ), .sp_addr ( sp_addr ), .sp_graphx32_do ( sp_do ) ); @@ -247,7 +280,6 @@ mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video( .blend ( status[5] ), .scandoubler_disable(1),//scandoublerD ), .no_csync ( 1'b1 ), - .scanlines ( status[4:3] ), .ypbpr ( ypbpr ) ); @@ -267,33 +299,29 @@ user_io( .key_strobe (key_strobe ), .key_pressed (key_pressed ), .key_code (key_code ), - .joystick_0 (joy_0 ), - .joystick_1 (joy_1 ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), .status (status ) ); dac #( - .C_bits(16)) + .C_bits(10)) dac_l( .clk_i(clk_sys), .res_n_i(1), - .dac_i(audio_l), + .dac_i(csd_audio), .dac_o(AUDIO_L) ); - + dac #( - .C_bits(16)) + .C_bits(10)) dac_r( .clk_i(clk_sys), .res_n_i(1), - .dac_i(audio_r), + .dac_i(csd_audio), .dac_o(AUDIO_R) ); -wire [7:0] joystick_0 = status[7] ? joy_1 : joy_0; -wire [7:0] joystick_1 = status[7] ? joy_0 : joy_1; - -// Rotated Normal wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3]; wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2]; wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1]; @@ -312,6 +340,8 @@ reg btn_fire2 = 0; reg btn_fire3 = 0; reg btn_fire4 = 0; reg btn_coin = 0; +reg btn_one_player = 0; +reg btn_two_players = 0; wire key_pressed; wire [7:0] key_code; wire key_strobe; @@ -324,8 +354,8 @@ always @(posedge clk_sys) begin 'h6B: btn_left <= key_pressed; // left 'h74: btn_right <= key_pressed; // right 'h76: btn_coin <= key_pressed; // ESC -// 'h05: btn_one_player <= key_pressed; // F1 -// 'h06: btn_two_players <= key_pressed; // F2 + 'h05: btn_one_player <= key_pressed; // F1 + 'h06: btn_two_players <= key_pressed; // F2 'h12: btn_fire4 <= key_pressed; // shift left 'h14: btn_fire3 <= key_pressed; // ctrl left 'h11: btn_fire2 <= key_pressed; // alt left @@ -334,4 +364,4 @@ always @(posedge clk_sys) begin end end -endmodule +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/cheap_squeak_deluxe.vhd b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/cheap_squeak_deluxe.vhd new file mode 100644 index 00000000..6e9dc8f1 --- /dev/null +++ b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/cheap_squeak_deluxe.vhd @@ -0,0 +1,219 @@ +-- Midway Cheap Squeak Deluxe sound board + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; +use work.fx68k.all; + +entity cheap_squeak_deluxe is +port( + clock_40 : in std_logic; + reset : in std_logic; + input : in std_logic_vector(7 downto 0); + rom_addr : out std_logic_vector(14 downto 1); + rom_do : in std_logic_vector(15 downto 0); + audio_out : out std_logic_vector(9 downto 0) +); +end cheap_squeak_deluxe; + +architecture rtl of cheap_squeak_deluxe is + +signal cpu_ce1 : std_logic; +signal cpu_ce2 : std_logic; +signal cpu_ce_count : std_logic_vector( 4 downto 0); +signal cpu_addr : std_logic_vector(23 downto 1); +signal cpu_rw : std_logic; +signal cpu_irq : std_logic; +signal cpu_data_in : std_logic_vector(15 downto 0); +signal cpu_data_out : std_logic_vector(15 downto 0); +signal cpu_as_n : std_logic; +signal cpu_lds_n : std_logic; +signal cpu_uds_n : std_logic; +signal cpu_dtack_n : std_logic; +signal cpu_vpa_n : std_logic; +signal cpu_fc : std_logic_vector( 2 downto 0); +signal cpu_ipl2_N : std_logic; +signal cpu_sel : std_logic; + +signal pia_data_out : std_logic_vector( 7 downto 0); +signal pia_pa_in : std_logic_vector( 7 downto 0); +signal pia_pa_out : std_logic_vector( 7 downto 0); +signal pia_pa_oe : std_logic_vector( 7 downto 0); +signal pia_pb_in : std_logic_vector( 7 downto 0); +signal pia_pb_out : std_logic_vector( 7 downto 0); +signal pia_pb_oe : std_logic_vector( 7 downto 0); +signal pia_ca1_in : std_logic; +signal pia_ca2_out : std_logic; +signal pia_cb1_in : std_logic; +signal pia_cb2_out : std_logic; +signal pia_irqa : std_logic; +signal pia_irqb : std_logic; + +signal cs_rom : std_logic; +signal cs_ram : std_logic; +signal cs_pia : std_logic; + +signal ram_we : std_logic; +signal ram_data_out : std_logic_vector(15 downto 0); + +signal romd1 : std_logic; +signal romd : std_logic; +signal rom_addr_out : std_logic_vector(14 downto 1); +signal rom_addr_old : std_logic_vector(14 downto 1); + +begin + +fx68k_inst: fx68k +port map ( + clk => clock_40, + extReset => reset, + pwrUp => reset, + enPhi1 => cpu_ce1, + enPhi2 => cpu_ce2, + + eRWn => cpu_rw, + ASn => cpu_as_n, + LDSn => cpu_lds_n, + UDSn => cpu_uds_n, + E => open, + VMAn => open, + FC0 => cpu_fc(0), + FC1 => cpu_fc(1), + FC2 => cpu_fc(2), + BGn => open, + oRESETn => open, + oHALTEDn => open, + DTACKn => cpu_dtack_n, + VPAn => cpu_vpa_n, + BERRn => '1', + BRn => '1', + BGACKn => '1', + IPL0n => '1', + IPL1n => '1', + IPL2n => cpu_ipl2_n, + iEdb => cpu_data_in, + oEdb => cpu_data_out, + eab => cpu_addr +); + +-- U6 +u_wram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 11) +port map( + clk => clock_40, + we => ram_we and not cpu_uds_n, + addr => cpu_addr(11 downto 1), + d => cpu_data_out(15 downto 8), + q => ram_data_out(15 downto 8) +); + +-- U16 +l_wram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 11) +port map( + clk => clock_40, + we => ram_we and not cpu_lds_n, + addr => cpu_addr(11 downto 1), + d => cpu_data_out(7 downto 0), + q => ram_data_out(7 downto 0) +); + +-- U9 +pia6821 : entity work.pia6821 +port map ( + clk => clock_40, + rst => reset, + cs => cs_pia, + rw => cpu_rw, + addr => cpu_addr(1)&cpu_addr(2), -- wired in reverse order + data_in => cpu_data_out(15 downto 8), + data_out => pia_data_out, + irqa => pia_irqa, + irqb => pia_irqb, + pa_i => pia_pa_in, + pa_o => pia_pa_out, + pa_oe => open, + ca1 => pia_ca1_in, + ca2_i => '0', + ca2_o => open, + ca2_oe => open, + pb_i => pia_pb_in, + pb_o => pia_pb_out, + pb_oe => open, + cb1 => pia_cb1_in, + cb2_i => '0', + cb2_o => open, + cb2_oe => open +); + +-- clock enable generation: 40/5 = 8 MHz effective clock (original: 7.5 MHz) +process (clock_40, reset) +begin + if reset = '1' then + cpu_ce1 <= '0'; + cpu_ce2 <= '0'; + cpu_ce_count <= (others => '0'); + elsif rising_edge(clock_40) then + cpu_ce1 <= '0'; + cpu_ce2 <= '0'; + cpu_ce_count <= cpu_ce_count + 1; + if cpu_ce_count = 2 then + cpu_ce1 <= '1'; + end if; + if cpu_ce_count = 4 then + cpu_ce2 <= '1'; + cpu_ce_count <= (others => '0'); + end if; + end if; +end process; + +process (clock_40, reset) +begin + if reset = '1' then + rom_addr_old <= (others => '1'); + elsif rising_edge(clock_40) then + + rom_addr_old <= rom_addr_out; + + -- ROMD signal - DTACK_N delay for ROM access + if cpu_as_n = '1' then + romd1 <= '0'; + romd <= '0'; + elsif cpu_ce1 = '1' then + romd1 <= '1'; + romd <= romd1; + end if; + end if; +end process; + +cpu_sel <= '1' when cpu_as_n = '0' and (cpu_uds_n = '0' or cpu_lds_n = '0') else '0'; +cpu_dtack_n <= not ((cs_rom and romd) or cs_ram or cs_pia); + +-- auto-vectored interrupt handling +cpu_vpa_n <= '0' when cpu_fc = "111" else '1'; +cpu_ipl2_n <= not (pia_irqa or pia_irqb); + +cs_rom <= '1' when cpu_sel = '1' and cpu_addr(16 downto 15) = "00" else '0'; +cs_ram <= '1' when cpu_sel = '1' and cpu_addr(16 downto 14) = "111" else '0'; +-- PIA uses 6800 bus cycle originally with VMA, VPA and E clock +cs_pia <= '1' when cpu_sel = '1' and cpu_addr(16 downto 14) = "110" else '0'; + +ram_we <= '1' when cs_ram = '1' and cpu_rw = '0' else '0'; + +cpu_data_in <= rom_do when cs_rom = '1' else + ram_data_out when cs_ram = '1' else + pia_data_out&x"FF" when cs_pia = '1' else + (others => '1'); + +rom_addr_out <= cpu_addr(14 downto 1) when cs_rom = '1' else rom_addr_old; +rom_addr <= rom_addr_out; + +audio_out <= pia_pa_out(7 downto 0)&pia_pb_out(7 downto 6); +pia_pb_in(5 downto 0) <= "00"&input(3 downto 0); -- stat1-stat0, sr3-sr0 +pia_ca1_in <= not input(4); -- sirq +pia_pa_in <= (others => '0'); +pia_cb1_in <= '0'; -- spare + + +end rtl; diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/0304-00803-0052.u15 b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/0304-00803-0052.u15 deleted file mode 100644 index c624a667..00000000 Binary files a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/0304-00803-0052.u15 and /dev/null differ diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/82s123.12d b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/82s123.12d deleted file mode 100644 index 74f83b11..00000000 --- a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/82s123.12d +++ /dev/null @@ -1 +0,0 @@ -ÿÿÿÿÿÿÿþÿÿýÿþÿ÷ûïmÿÿÿÿÿÿÿÿÿÿÿÿ \ No newline at end of file diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/make_spy_hunter_proms.bat b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/make_spy_hunter_proms.bat deleted file mode 100644 index 6d04e643..00000000 --- a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/make_spy_hunter_proms.bat +++ /dev/null @@ -1,24 +0,0 @@ -copy /B ttprog0.bin + ttprog1.bin + ttprog2.bin + ttprog3.bin + ttprog4.bin + ttprog5.bin + ttprog5.bin ttag_cpu.bin -copy /B ttu7.bin + ttu17.bin + ttu8.bin + ttu18.bin ttag_sound_cpu.bin - -make_vhdl_prom ttan.bin ttag_ch_bits.vhd - -copy /B ttbg0.bin + ttbg1.bin ttag_bg_bits_1.bin -copy /B ttbg2.bin + ttbg3.bin ttag_bg_bits_2.bin -make_vhdl_prom ttag_bg_bits_1.bin ttag_bg_bits_1.vhd -make_vhdl_prom ttag_bg_bits_2.bin ttag_bg_bits_2.vhd - - - -make_vhdl_prom 82s123.12d midssio_82s123.vhd - -copy /B ttfg1.bin + ttfg0.bin ttag_sp_bits_1.bin -copy /B ttfg3.bin + ttfg2.bin ttag_sp_bits_2.bin -copy /B ttfg5.bin + ttfg4.bin ttag_sp_bits_3.bin -copy /B ttfg7.bin + ttfg6.bin ttag_sp_bits_4.bin - - -copy /b ttag_cpu.bin + ttag_sound_cpu.bin + ttag_sp_bits_1.bin + ttag_sp_bits_2.bin + ttag_sp_bits_3.bin + ttag_sp_bits_4.bin TURBOTAG.ROM - -pause - diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/make_vhdl_prom.exe b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/make_vhdl_prom.exe deleted file mode 100644 index 1e5618bf..00000000 Binary files a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/make_vhdl_prom.exe and /dev/null differ diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_bg_bits_1.bin b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_bg_bits_1.bin deleted file mode 100644 index 5d790649..00000000 Binary files a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_bg_bits_1.bin and /dev/null differ diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_bg_bits_1.vhd b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_bg_bits_1.vhd deleted file mode 100644 index 29c9f883..00000000 --- a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_bg_bits_1.vhd +++ /dev/null @@ -1,1046 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity ttag_bg_bits_1 is -port ( - clk : in std_logic; - addr : in std_logic_vector(13 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of ttag_bg_bits_1 is - type rom is array(0 to 16383) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55", - X"50",X"15",X"01",X"50",X"15",X"01",X"50",X"15",X"50",X"54",X"05",X"40",X"54",X"05",X"40",X"54", - X"51",X"50",X"15",X"01",X"50",X"15",X"01",X"50",X"55",X"40",X"54",X"05",X"40",X"54",X"05",X"40", - X"55",X"01",X"50",X"15",X"01",X"50",X"15",X"00",X"54",X"05",X"40",X"54",X"05",X"40",X"54",X"00", - X"50",X"15",X"01",X"50",X"15",X"01",X"50",X"00",X"50",X"54",X"05",X"40",X"54",X"05",X"40",X"00", - X"51",X"50",X"15",X"01",X"50",X"15",X"00",X"00",X"55",X"40",X"54",X"05",X"40",X"54",X"00",X"00", - X"55",X"01",X"50",X"15",X"01",X"50",X"00",X"00",X"54",X"05",X"40",X"54",X"05",X"40",X"00",X"00", - X"50",X"15",X"01",X"50",X"15",X"00",X"00",X"00",X"50",X"54",X"05",X"40",X"54",X"00",X"00",X"00", - X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55", - X"01",X"55",X"01",X"50",X"15",X"01",X"50",X"15",X"01",X"54",X"05",X"40",X"54",X"05",X"40",X"54", - X"00",X"54",X"15",X"01",X"50",X"15",X"01",X"50",X"00",X"14",X"54",X"05",X"40",X"54",X"05",X"40", - X"00",X"15",X"50",X"15",X"01",X"50",X"15",X"00",X"00",X"05",X"40",X"54",X"05",X"40",X"54",X"00", - X"00",X"01",X"41",X"50",X"15",X"01",X"50",X"00",X"00",X"01",X"55",X"40",X"54",X"05",X"40",X"00", - X"00",X"00",X"55",X"01",X"50",X"15",X"00",X"00",X"00",X"00",X"14",X"05",X"40",X"54",X"00",X"00", - X"00",X"00",X"15",X"15",X"01",X"50",X"00",X"00",X"00",X"00",X"05",X"54",X"05",X"40",X"00",X"00", - X"00",X"00",X"01",X"50",X"15",X"00",X"00",X"00",X"00",X"00",X"01",X"50",X"54",X"00",X"00",X"00", - X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55", - X"00",X"55",X"40",X"54",X"05",X"40",X"54",X"05",X"00",X"55",X"01",X"50",X"15",X"01",X"50",X"15", - X"00",X"15",X"05",X"40",X"54",X"05",X"40",X"55",X"00",X"05",X"15",X"01",X"50",X"15",X"01",X"55", - X"00",X"05",X"54",X"05",X"40",X"54",X"05",X"45",X"00",X"01",X"50",X"15",X"01",X"50",X"15",X"05", - X"00",X"00",X"50",X"54",X"05",X"40",X"54",X"05",X"00",X"00",X"55",X"50",X"15",X"01",X"50",X"15", - X"00",X"00",X"15",X"40",X"54",X"05",X"40",X"55",X"00",X"00",X"05",X"01",X"50",X"15",X"01",X"55", - X"00",X"00",X"05",X"45",X"40",X"54",X"05",X"45",X"00",X"00",X"01",X"55",X"01",X"50",X"15",X"05", - X"00",X"00",X"00",X"54",X"05",X"40",X"54",X"05",X"00",X"00",X"00",X"54",X"15",X"01",X"50",X"15", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"01",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"41",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"14",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"50",X"10",X"00",X"00",X"00", - X"00",X"00",X"00",X"10",X"14",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"40",X"00",X"00",X"00", - X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"15",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - 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Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_bg_bits_2.bin b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_bg_bits_2.bin deleted file mode 100644 index ec0ab70b..00000000 Binary files a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_bg_bits_2.bin and /dev/null differ diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_bg_bits_2.vhd b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_bg_bits_2.vhd deleted file mode 100644 index 0c1c65df..00000000 --- a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_bg_bits_2.vhd +++ /dev/null @@ -1,1046 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity ttag_bg_bits_2 is -port ( - clk : in std_logic; - addr : in std_logic_vector(13 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of ttag_bg_bits_2 is - type rom is array(0 to 16383) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - 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in std_logic_vector(11 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of ttag_ch_bits is - type rom is array(0 to 4095) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"AB",X"AA",X"AA",X"EA",X"AB",X"AA",X"AF",X"FE",X"AA",X"AA",X"AE",X"EE",X"AE",X"EE",X"AF",X"FE", - X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA", - X"3F",X"FC",X"C0",X"03",X"CC",X"33",X"CC",X"33",X"CC",X"33",X"CF",X"F3",X"C0",X"03",X"3F",X"FC", - X"AA",X"AA",X"AA",X"AE",X"AA",X"AE",X"AF",X"FE",X"AA",X"AA",X"AF",X"EA",X"AE",X"EA",X"AF",X"FE", - X"AA",X"AA",X"AF",X"EA",X"AA",X"FE",X"AF",X"EA",X"AA",X"AA",X"AB",X"FE",X"AF",X"BA",X"AB",X"FE", - X"AA",X"AA",X"AF",X"BE",X"AE",X"EA",X"AF",X"FE",X"AA",X"AA",X"AE",X"EE",X"AE",X"EE",X"AF",X"FE", - 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if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_cpu.bin b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_cpu.bin deleted file mode 100644 index f005a261..00000000 Binary files a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_cpu.bin and /dev/null differ diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_sound_cpu.bin b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_sound_cpu.bin deleted file mode 100644 index 629b4916..00000000 Binary files a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_sound_cpu.bin and /dev/null differ diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_sp_bits_1.bin b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_sp_bits_1.bin deleted file mode 100644 index ab42f44f..00000000 Binary files a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_sp_bits_1.bin and /dev/null differ diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_sp_bits_2.bin b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_sp_bits_2.bin deleted file mode 100644 index a1b7a32c..00000000 Binary files a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_sp_bits_2.bin and /dev/null differ diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_sp_bits_3.bin b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_sp_bits_3.bin deleted file mode 100644 index ea7b1745..00000000 Binary files a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_sp_bits_3.bin and /dev/null differ diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_sp_bits_4.bin b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_sp_bits_4.bin deleted file mode 100644 index 1f98b849..00000000 Binary files a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_sp_bits_4.bin and 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Scroll/TurboTag_MiST/rtl/rom/unzip/ttu7.bin deleted file mode 100644 index 94a5f2d0..00000000 Binary files a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttu7.bin and /dev/null differ diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttu8.bin b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttu8.bin deleted file mode 100644 index 4eee2b77..00000000 Binary files a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttu8.bin and /dev/null differ diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/sdram.sv b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/sdram.sv index 41f5b7a8..9f78c393 100644 --- a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/sdram.sv +++ b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/sdram.sv @@ -50,6 +50,8 @@ module sdram ( output reg [15:0] cpu1_q, input [16:1] cpu2_addr, output reg [15:0] cpu2_q, + input [16:1] cpu3_addr, + output reg [15:0] cpu3_q, input port2_req, output reg port2_ack, @@ -150,9 +152,9 @@ assign SDRAM_nRAS = sd_cmd[2]; assign SDRAM_nCAS = sd_cmd[1]; assign SDRAM_nWE = sd_cmd[0]; -reg [24:1] addr_latch[2]; +reg [24:1] addr_latch[3]; reg [24:1] addr_latch_next[2]; -reg [16:1] addr_last[2]; +reg [16:1] addr_last[4]; reg [16:2] addr_last2[2]; reg [15:0] din_latch[2]; reg [1:0] oe_latch; @@ -162,14 +164,15 @@ reg [1:0] ds[2]; reg port1_state; reg port2_state; -localparam PORT_NONE = 2'd0; -localparam PORT_CPU1 = 2'd1; -localparam PORT_CPU2 = 2'd2; -localparam PORT_SP = 2'd1; -localparam PORT_REQ = 2'd3; +localparam PORT_NONE = 3'd0; +localparam PORT_CPU1 = 3'd1; +localparam PORT_CPU2 = 3'd2; +localparam PORT_CPU3 = 3'd3; +localparam PORT_SP = 3'd1; +localparam PORT_REQ = 3'd4; -reg [1:0] next_port[2]; -reg [1:0] port[2]; +reg [2:0] next_port[2]; +reg [2:0] port[2]; reg refresh; reg [10:0] refresh_cnt; @@ -189,6 +192,9 @@ always @(*) begin end else if (cpu2_addr != addr_last[PORT_CPU2]) begin next_port[0] = PORT_CPU2; addr_latch_next[0] = { 8'd0, cpu2_addr }; + end else if (cpu3_addr != addr_last[PORT_CPU3]) begin + next_port[0] = PORT_CPU3; + addr_latch_next[0] = { 8'd0, cpu3_addr }; end else begin next_port[0] = PORT_NONE; addr_latch_next[0] = addr_latch[0]; @@ -321,6 +327,7 @@ always @(posedge clk) begin PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end PORT_CPU1: begin cpu1_q <= sd_din; end PORT_CPU2: begin cpu2_q <= sd_din; end + PORT_CPU3: begin cpu3_q <= sd_din; end default: ; endcase; end diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/spy_hunter.vhd b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/turbo_tag.vhd similarity index 92% rename from Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/spy_hunter.vhd rename to Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/turbo_tag.vhd index 559d2604..6e2b1650 100644 --- a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/spy_hunter.vhd +++ b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/turbo_tag.vhd @@ -1,5 +1,5 @@ --------------------------------------------------------------------------------- --- Spy hunter by Dar (darfpga@aol.fr) (06/12/2019) +-- Turbo Tag by Dar (darfpga@aol.fr) (06/12/2019) -- http://darfpga.blogspot.fr --------------------------------------------------------------------------------- -- @@ -134,68 +134,46 @@ use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -entity spy_hunter is +entity turbo_tag is port( - clock_40 : in std_logic; - reset : in std_logic; - tv15Khz_mode : in std_logic; - video_r : out std_logic_vector(2 downto 0); - video_g : out std_logic_vector(2 downto 0); - video_b : out std_logic_vector(2 downto 0); - video_clk : out std_logic; - video_csync : out std_logic; - video_blankn : out std_logic; - video_hs : out std_logic; - video_vs : out std_logic; - - separate_audio : in std_logic; - audio_out_l : out std_logic_vector(15 downto 0); - audio_out_r : out std_logic_vector(15 downto 0); - - coin1 : in std_logic; - coin2 : in std_logic; - - shift : in std_logic; - oil : in std_logic; - missile : in std_logic; - van : in std_logic; - smoke : in std_logic; - gun : in std_logic; - --- lamp_oil : out std_logic; --- lamp_missile : out std_logic; --- lamp_van : out std_logic; --- lamp_smoke : out std_logic; --- lamp_gun : out std_logic; - - - steering : in std_logic_vector(7 downto 0); - gas : in std_logic_vector(7 downto 0); - - service : in std_logic; --- sp_rom_addr : out std_logic_vector(17 downto 0); -- shall contains 1-2-3-4 rom order and 4-3-2-1 rom order --- sp_rom_rd : out std_logic; - --- sp_graphx0 : in std_logic_vector(31 downto 0); --- sp_graphx1 : in std_logic_vector(31 downto 0); --- sp_graphx2 : in std_logic_vector(31 downto 0); --- sp_graphx3 : in std_logic_vector(31 downto 0); - - cpu_rom_addr : out std_logic_vector(15 downto 0); - cpu_rom_do : in std_logic_vector(7 downto 0); - snd_rom_addr : out std_logic_vector(12 downto 0); - snd_rom_do : in std_logic_vector(7 downto 0); - - sp_addr : out std_logic_vector(14 downto 0); --- sp_graphx_do : in std_logic_vector(7 downto 0); - sp_graphx32_do : in std_logic_vector(31 downto 0); - + clock_40 : in std_logic; + reset : in std_logic; + tv15Khz_mode : in std_logic; + video_r : out std_logic_vector(2 downto 0); + video_g : out std_logic_vector(2 downto 0); + video_b : out std_logic_vector(2 downto 0); + video_clk : out std_logic; + video_csync : out std_logic; + video_blankn : out std_logic; + video_hs : out std_logic; + video_vs : out std_logic; + separate_audio : in std_logic; + audio_out_l : out std_logic_vector(15 downto 0); + audio_out_r : out std_logic_vector(15 downto 0); + csd_audio_out : out std_logic_vector( 9 downto 0); + start1 : in std_logic; + start2 : in std_logic; + coin1 : in std_logic; + coin2 : in std_logic; + shift : in std_logic; + left : in std_logic; + center : in std_logic; + right : in std_logic; + gas : in std_logic_vector(7 downto 0); + steering : in std_logic_vector(7 downto 0); + service : in std_logic; + cpu_rom_addr : out std_logic_vector(15 downto 0); + cpu_rom_do : in std_logic_vector(7 downto 0); + csd_rom_addr : out std_logic_vector(14 downto 1); + csd_rom_do : in std_logic_vector(15 downto 0); + sp_addr : out std_logic_vector(14 downto 0); + sp_graphx32_do : in std_logic_vector(31 downto 0); dbg_cpu_addr : out std_logic_vector(15 downto 0) ); -end spy_hunter; +end turbo_tag; -architecture struct of spy_hunter is +architecture struct of turbo_tag is signal reset_n : std_logic; signal clock_vid : std_logic; @@ -363,17 +341,6 @@ clock_vid <= clock_40; clock_vidn <= not clock_40; reset_n <= not reset; --- debug -process (reset, clock_vid) -begin - if rising_edge(clock_vid) then -- and cpu_ena ='1' and cpu_mreq_n ='0' then - --dbg_cpu_addr<= cpu_addr; - --dbg_cpu_addr<= "000000000000000" & service; --cpu_addr; - --dbg_cpu_addr<= max_sprite_rr & "0000000" & service; --cpu_addr; - dbg_cpu_addr <= steering & gas; - end if; -end process; - -- make enables clock from clock_vid process (clock_vid, reset) begin @@ -512,11 +479,12 @@ end process; -------------------- -- "11" for test & tilt & unused input_0 <= not service & "11" & not shift & "11" & not coin2 & not coin1; -input_1 <= "111" & not gun & not smoke & not van & not missile & not oil; +input_1 <= not service & "11" & not right & not start2 & not center & not left & not start1; input_2 <= steering when output_4(7) = '1' else gas; input_3 <= x"FF"; input_4 <= x"FF"; + -- ssio ouput_4 : -- OP4 bit 0/3 J5-10/13 md0/3 (to cheap squeak deluxe and lamps) -- OP4 bit 4 J5-14 st0 (to cheap squeak deluxe) @@ -524,8 +492,6 @@ input_4 <= x"FF"; -- OP4 bit 6 J5-16 ard (to absolute position) -- OP4 bit 7 J5-17 sel (to absolute position) - - ------------------------------------------ -- cpu data input with address decoding -- ------------------------------------------ @@ -543,7 +509,7 @@ cpu_di <= cpu_rom_do when cpu_mreq_n = '0' and cpu_addr(15 downto 12) < X"E ctc_counter_0_do when cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F0" else X"FF"; -cpu_rom_addr <= cpu_addr;-- when cpu_addr < x"A000" else cpu_addr xor x"6000"; -- last rom has upper/lower part swapped - not needed here +cpu_rom_addr <= cpu_addr when cpu_addr < x"A000" else cpu_addr xor x"6000"; -- last rom has upper/lower part swapped ------------------------------------------ -- write enable / ram access from CPU -- @@ -727,7 +693,7 @@ begin if pix_ena = '1' then if hcnt(0) = '1' then - if hcnt(3 downto 1) = "111" then -- normal text + if hcnt(3 downto 1) = "111" then ch_code <= ch_ram_do; end if; @@ -810,9 +776,7 @@ begin if rising_edge(clock_vid) then video_g <= palette_do(2 downto 0); video_b <= palette_do(5 downto 3); - video_r <= palette_do(8 downto 6); - - + video_r <= palette_do(8 downto 6); case ch_color is when "01" => video_g <= "111"; @@ -948,6 +912,14 @@ port map( ); +-- cpu program ROM 0x0000-0xDFFF +--rom_cpu : entity work.spy_hunter_cpu +--port map( +-- clk => clock_vidn, +-- addr => cpu_rom_addr, +-- data => cpu_rom_do +--); + -- working RAM F000-F7FF 2Ko wram : entity work.cmos_ram generic map( dWidth => 8, aWidth => 11) @@ -1060,7 +1032,7 @@ bg_graphics_1 : entity work.ttag_bg_bits_1 port map( clk => clock_vidn, addr => bg_code_line, - data => bg_graphx2_do + data => bg_graphx1_do ); -- background graphics ROM 5A/6A @@ -1068,11 +1040,22 @@ bg_graphics_2 : entity work.ttag_bg_bits_2 port map( clk => clock_vidn, addr => bg_code_line, - data => bg_graphx1_do + data => bg_graphx2_do +); + +-- background & sprite palette +palette : entity work.gen_ram +generic map( dWidth => 9, aWidth => 6) +port map( + clk => clock_vidn, + we => palette_we, + addr => palette_addr, + d => cpu_addr(0) & cpu_do, + q => palette_do ); -- Spy hunter sound board -sound_board : entity work.spy_hunter_sound_board +sound_board : entity work.turbo_tag_sound_board port map( clock_40 => clock_40, reset => reset, @@ -1090,25 +1073,21 @@ port map( input_4 => input_4, output_4 => output_4, - cpu_rom_addr => snd_rom_addr, - cpu_rom_do => snd_rom_do, separate_audio => separate_audio, audio_out_l => audio_out_l, - audio_out_r => audio_out_r, - - dbg_cpu_addr => open --dbg_cpu_addr + audio_out_r => audio_out_r ); - --- background & sprite palette -palette : entity work.gen_ram -generic map( dWidth => 9, aWidth => 6) -port map( - clk => clock_vidn, - we => palette_we, - addr => palette_addr, - d => cpu_addr(0) & cpu_do, - q => palette_do + +-- Cheap Squeak Deluxe +csd: entity work.cheap_squeak_deluxe +port map ( + clock_40 => clock_40, + reset => reset, + input => output_4, + rom_addr => csd_rom_addr, + rom_do => csd_rom_do, + audio_out => csd_audio_out ); end struct; \ No newline at end of file diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/spy_hunter_control.vhd b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/turbo_tag_control.vhd similarity index 90% rename from Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/spy_hunter_control.vhd rename to Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/turbo_tag_control.vhd index 2b30a78d..84970891 100644 --- a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/spy_hunter_control.vhd +++ b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/turbo_tag_control.vhd @@ -3,7 +3,7 @@ use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -entity spy_hunter_control is +entity turbo_tag_control is port( clock_40 : in std_logic; reset : in std_logic; @@ -16,10 +16,10 @@ port( steering : out std_logic_vector(7 downto 0); gas : out std_logic_vector(7 downto 0) ); -end spy_hunter_control; +end turbo_tag_control; -architecture struct of spy_hunter_control is +architecture struct of turbo_tag_control is signal steering_r : std_logic_vector(7 downto 0); --signal steering_plus : std_logic; signal steering_plus_r : std_logic; @@ -35,6 +35,14 @@ architecture struct of spy_hunter_control is signal gas_timer : std_logic_vector(5 downto 0); signal vsync_r : std_logic; begin-- absolute position decoder simulation + +--spy PORT_BIT( 0xff, 0x30, IPT_PEDAL ) PORT_MINMAX(0x30,0xff) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) + +--tag PORT_BIT( 0xff, 0x3c, IPT_PEDAL ) PORT_MINMAX(60,180) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) 0x3c,0xb4 + +--spy PORT_BIT( 0xff, 0x74, IPT_PADDLE ) PORT_MINMAX(0x34,0xb4) PORT_SENSITIVITY(40) PORT_KEYDELTA(10) + +--tag PORT_BIT( 0xff, 0x60, IPT_PADDLE ) PORT_SENSITIVITY(40) PORT_KEYDELTA(10) -- -- steering : -- thresholds median diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/spy_hunter_sound_board.vhd b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/turbo_tag_sound_board.vhd similarity index 98% rename from Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/spy_hunter_sound_board.vhd rename to Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/turbo_tag_sound_board.vhd index 1b47507f..18ef13c2 100644 --- a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/spy_hunter_sound_board.vhd +++ b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/turbo_tag_sound_board.vhd @@ -1,5 +1,5 @@ --------------------------------------------------------------------------------- --- Timber sound board by Dar (darfpga@aol.fr) (19/10/2019) +-- turbo_tag sound board by Dar (darfpga@aol.fr) (19/10/2019) -- http://darfpga.blogspot.fr --------------------------------------------------------------------------------- -- gen_ram.vhd & io_ps2_keyboard @@ -52,7 +52,7 @@ use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -entity spy_hunter_sound_board is +entity turbo_tag_sound_board is port( clock_40 : in std_logic; reset : in std_logic; @@ -70,18 +70,16 @@ port( input_4 : in std_logic_vector(7 downto 0); output_4 : out std_logic_vector(7 downto 0); - cpu_rom_addr : out std_logic_vector(12 downto 0); - cpu_rom_do : in std_logic_vector(7 downto 0); separate_audio : in std_logic; audio_out_l : out std_logic_vector(15 downto 0); audio_out_r : out std_logic_vector(15 downto 0); - + dbg_cpu_addr : out std_logic_vector(15 downto 0) ); -end spy_hunter_sound_board; +end turbo_tag_sound_board; -architecture struct of spy_hunter_sound_board is +architecture struct of turbo_tag_sound_board is signal reset_n : std_logic; signal clock_snd : std_logic; @@ -216,7 +214,7 @@ ena_4Mhz <= '1' when clock_cnt1 = "00000" or ------------------------------------------ -- cpu data input with address decoding -- ------------------------------------------ -cpu_di <= cpu_rom_do when cpu_mreq_n = '0' and cpu_addr(15 downto 14) = "00" else -- 0x0000-0x3FFF +cpu_di <= --cpu_rom_do when cpu_mreq_n = '0' and cpu_addr(15 downto 14) = "00" else -- 0x0000-0x3FFF wram_do when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"8" else -- 0x8000-0x83FF iram_0_do when cpu_mreq_n = '0' and cpu_addr(15 downto 0)= X"9000" else iram_1_do when cpu_mreq_n = '0' and cpu_addr(15 downto 0)= X"9001" else @@ -444,8 +442,8 @@ port map( -- addr => cpu_addr(12 downto 0), -- data => cpu_rom_do --); ---cpu_rom_addr <= cpu_addr(12 downto 0); +--cpu_rom_addr <= cpu_addr(12 downto 0); -- working RAM 0x8000-0x83FF wram : entity work.gen_ram diff --git a/Arcade_MiST/Nintendo Popeye Hardware/Popeye_MiST/Release/Popeye.rbf b/Arcade_MiST/Nintendo Popeye Hardware/Popeye_MiST/Release/Popeye.rbf index 81754db3..c72028ac 100644 Binary files a/Arcade_MiST/Nintendo Popeye Hardware/Popeye_MiST/Release/Popeye.rbf and b/Arcade_MiST/Nintendo Popeye Hardware/Popeye_MiST/Release/Popeye.rbf differ diff --git a/Arcade_MiST/Nintendo Popeye Hardware/Popeye_MiST/rtl/popeye.vhd b/Arcade_MiST/Nintendo Popeye Hardware/Popeye_MiST/rtl/popeye.vhd index 5ca9ae21..3a20a5be 100644 --- a/Arcade_MiST/Nintendo Popeye Hardware/Popeye_MiST/rtl/popeye.vhd +++ b/Arcade_MiST/Nintendo Popeye Hardware/Popeye_MiST/rtl/popeye.vhd @@ -120,6 +120,7 @@ architecture struct of popeye is signal cpu_di : std_logic_vector( 7 downto 0); signal cpu_do : std_logic_vector( 7 downto 0); signal cpu_wr_n : std_logic; + signal cpu_wr_n_r : std_logic; signal cpu_rd_n : std_logic; signal cpu_mreq_n : std_logic; signal cpu_ioreq_n : std_logic; @@ -234,6 +235,12 @@ architecture struct of popeye is signal ay_iob_do : std_logic_vector(7 downto 0); signal ay_ioa_di : std_logic_vector(7 downto 0); + + signal protection_data0 : std_logic_vector(7 downto 0); + signal protection_data1 : std_logic_vector(7 downto 0); + signal protection_do : std_logic_vector(7 downto 0); + signal protection_shift : std_logic_vector(2 downto 0); + begin @@ -415,8 +422,19 @@ cpu_rom_do_swp <= cpu_rom_do(3) & cpu_rom_do(4) & cpu_rom_do(2) & cpu_rom_do(5) & cpu_rom_do(1) & cpu_rom_do(6) & cpu_rom_do(0) & cpu_rom_do(7); +protection_do <= + (protection_data1(7 downto 0) ) or ( "00000000" ) when protection_shift = "000" else + (protection_data1(6 downto 0) & '0' ) or ( "0000000" & protection_data0(7 downto 7)) when protection_shift = "001" else + (protection_data1(5 downto 0) & "00" ) or ( "000000" & protection_data0(7 downto 6)) when protection_shift = "010" else + (protection_data1(4 downto 0) & "000" ) or ( "00000" & protection_data0(7 downto 5)) when protection_shift = "011" else + (protection_data1(3 downto 0) & "0000" ) or ( "0000" & protection_data0(7 downto 4)) when protection_shift = "100" else + (protection_data1(2 downto 0) & "00000" ) or ( "000" & protection_data0(7 downto 3)) when protection_shift = "101" else + (protection_data1(1 downto 0) & "000000" ) or ( "00" & protection_data0(7 downto 2)) when protection_shift = "110" else + (protection_data1(0 downto 0) & "0000000" ) or ( '0' & protection_data0(7 downto 1)); -- protection_shift = "111" + cpu_di <= cpu_rom_do_swp when cpu_mreq_n = '0' and cpu_addr(15 downto 12) < X"8" else -- program rom 0000-7FFF 32Ko wram_do_r when cpu_mreq_n = '0' and (cpu_addr and X"E000") = x"8000" else -- work ram 8000-87FF 2Ko + mirroring 1800 + protection_do when cpu_mreq_n = '0' and (cpu_addr and X"FFFF") = x"E000" else -- protection E000 input_0 when cpu_ioreq_n = '0' and (cpu_addr(1 downto 0) = "00") else input_1 when cpu_ioreq_n = '0' and (cpu_addr(1 downto 0) = "01") else input_2 when cpu_ioreq_n = '0' and (cpu_addr(1 downto 0) = "10") else @@ -487,7 +505,7 @@ end process; process (clock_vid) begin if rising_edge(clock_vid) then - + cpu_wr_n_r <= cpu_wr_n; if cpu_mreq_n = '0' and cpu_wr_n = '0' then if (cpu_addr = x"8C00") then hoffset <= cpu_do; end if; if (cpu_addr = x"8C01") then voffset <= cpu_do; end if; @@ -497,10 +515,15 @@ begin bg_palette_addr(4) <= cpu_do(3); end if; end if; - + if (cpu_addr = x"E000") then protection_shift <= cpu_do(2 downto 0); end if; + if (cpu_addr = x"E001") and cpu_wr_n_r = '1' then + protection_data0 <= protection_data1; + protection_data1 <= cpu_do; + end if; end if; end process; + cpu_nmi_n <= video_vs; audio_out <= ay_audio & X"00"; diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/SkySkipper.qsf b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/SkySkipper.qsf index f4ebf1e0..f58ba2f0 100644 --- a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/SkySkipper.qsf +++ b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/SkySkipper.qsf @@ -239,5 +239,4 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO -set_global_assignment -name VERILOG_FILE rtl/jtpopeye_security.v set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/SkySkipper.vhd b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/SkySkipper.vhd index 07d8315b..6f2c2996 100644 --- a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/SkySkipper.vhd +++ b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/SkySkipper.vhd @@ -121,6 +121,7 @@ architecture struct of SkySkipper is signal cpu_di : std_logic_vector( 7 downto 0); signal cpu_do : std_logic_vector( 7 downto 0); signal cpu_wr_n : std_logic; + signal cpu_wr_n_r : std_logic; signal cpu_rd_n : std_logic; signal cpu_mreq_n : std_logic; signal cpu_ioreq_n : std_logic; @@ -235,23 +236,11 @@ architecture struct of SkySkipper is signal ay_iob_do : std_logic_vector(7 downto 0); signal ay_ioa_di : std_logic_vector(7 downto 0); - signal sec_cs : std_logic; - signal sec_we : std_logic; - signal sec_data : std_logic_vector(7 downto 0); - COMPONENT jtpopeye_security - PORT - ( - clk : IN STD_LOGIC; - cen : IN STD_LOGIC; - din : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - cs : IN STD_LOGIC; - A0 : IN STD_LOGIC; - rd_n : IN STD_LOGIC; - wr_n : IN STD_LOGIC - ); -END COMPONENT; + signal protection_data0 : std_logic_vector(7 downto 0); + signal protection_data1 : std_logic_vector(7 downto 0); + signal protection_do : std_logic_vector(7 downto 0); + signal protection_shift : std_logic_vector(2 downto 0); begin @@ -430,10 +419,19 @@ cpu_rom_addr <= (cpu_addr(14 downto 10) & cpu_addr(8 downto 7) & cpu_addr(0) & c cpu_rom_do(3) & cpu_rom_do(4) & cpu_rom_do(2) & cpu_rom_do(5) & cpu_rom_do(1) & cpu_rom_do(6) & cpu_rom_do(0) & cpu_rom_do(7); + protection_do <= + (protection_data1(7 downto 0) ) or ( "00000000" ) when protection_shift = "000" else + (protection_data1(6 downto 0) & '0' ) or ( "0000000" & protection_data0(7 downto 7)) when protection_shift = "001" else + (protection_data1(5 downto 0) & "00" ) or ( "000000" & protection_data0(7 downto 6)) when protection_shift = "010" else + (protection_data1(4 downto 0) & "000" ) or ( "00000" & protection_data0(7 downto 5)) when protection_shift = "011" else + (protection_data1(3 downto 0) & "0000" ) or ( "0000" & protection_data0(7 downto 4)) when protection_shift = "100" else + (protection_data1(2 downto 0) & "00000" ) or ( "000" & protection_data0(7 downto 3)) when protection_shift = "101" else + (protection_data1(1 downto 0) & "000000" ) or ( "00" & protection_data0(7 downto 2)) when protection_shift = "110" else + (protection_data1(0 downto 0) & "0000000" ) or ( '0' & protection_data0(7 downto 1)); -- protection_shift = "111" + cpu_di <= cpu_rom_do_swp when cpu_mreq_n = '0' and cpu_addr(15 downto 12) < X"8" else -- program rom 0000-7FFF 32Ko wram_do_r when cpu_mreq_n = '0' and (cpu_addr and X"E000") = x"8000" else -- work ram 8000-87FF 2Ko + mirroring 1800 --- sec_data when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = x"E" else - sec_data when cpu_mreq_n = '0' and cpu_addr(15 downto 0) = "1110000000000001" else + protection_do when cpu_mreq_n = '0' and (cpu_addr and X"FFFF") = x"E000" else -- protection E000 input_0 when cpu_ioreq_n = '0' and (cpu_addr(1 downto 0) = "00") else input_1 when cpu_ioreq_n = '0' and (cpu_addr(1 downto 0) = "01") else input_2 when cpu_ioreq_n = '0' and (cpu_addr(1 downto 0) = "10") else @@ -450,8 +448,6 @@ ch_ram_txt_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr an ch_ram_color_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"EC00") = x"A400" and hcnt(0) = '0' else '0'; bg_ram_lnib_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"F000") = x"C000" and hcnt(0) = '0' else '0'; bg_ram_hnib_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"F000") = x"D000" and hcnt(0) = '0' else '0';--not needed ---sec_cs <= '1' when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = x"E" else '0'; -sec_cs <= '1' when cpu_addr(15 downto 0) = "1110000000000001" else '0'; ----------------------------------------------------- -- Transfer sprite data from wram to sprite ram -- once per frame. Read sprite ram on every scanline. @@ -505,7 +501,7 @@ end process; process (clock_vid) begin if rising_edge(clock_vid) then - + cpu_wr_n_r <= cpu_wr_n; if cpu_mreq_n = '0' and cpu_wr_n = '0' then if (cpu_addr = x"8C00") then hoffset <= cpu_do; end if; if (cpu_addr = x"8C01") then voffset <= cpu_do; end if; @@ -515,7 +511,11 @@ begin bg_palette_addr(4) <= cpu_do(3); end if; end if; - + if (cpu_addr = x"E000") then protection_shift <= cpu_do(2 downto 0); end if; + if (cpu_addr = x"E001") and cpu_wr_n_r = '1' then + protection_data0 <= protection_data1; + protection_data1 <= cpu_do; + end if; end if; end process; @@ -977,16 +977,4 @@ port map ( CLK => clock_vid --: in std_logic -- note 6 Mhz! ); -sec : jtpopeye_security -port map ( - clk => clock_vid, - cen => cpu_ena, - din => cpu_do, - dout => sec_data, - rd_n => cpu_rd_n, - wr_n => cpu_wr_n, - cs => sec_cs, - A0 => cpu_addr(0) -); - end; diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/jtpopeye_security.v b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/jtpopeye_security.v deleted file mode 100644 index 736475d2..00000000 --- a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/jtpopeye_security.v +++ /dev/null @@ -1,96 +0,0 @@ -/* This file is part of JTPOPEYE. - JTPOPEYE program is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - JTPOPEYE program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR AD PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with JTPOPEYE. If not, see . - - Author: Jose Tejada Gomez. Twitter: @topapate - Version: 1.0 - Date: 12-3-2019 */ - -`timescale 1ns/1ps - -// 7J: '139 decoder -// /MemWR and /MemRD serve as enable signals. If H all outputs will be H -// -// /OE is the same as addr1 -// Mode is the same addr0. Mode pin is not used in this model. -// -// CPU || /MemWR || /MemRD -// /sec_cs addr0 || A[1:0] || /OE || Mode -// =========================================== -// 0 0 || 10 || 1 || 0 -// 0 1 || 01 || 0 || 1 -// 1 x || 11 || 1 || 1 - -// based on code provided by www.JAMMARCADE.net - -module jtpopeye_security( - input clk, - input cen, - input [7:0] din, - output reg [7:0] dout, - input cs, - input A0, - input rd_n, - input wr_n -); - -reg [7:0] fifo [1:0]; -reg [2:0] shift; - -reg last_addr0, last_addr1; -reg addr0, addr1, oen; -wire csn = ~cs; -reg [7:0] result; - -always @(*) begin - addr0 = 1'b1; - addr1 = 1'b1; - oen = 1'b1; - // mode = 1'b1; - if( csn ) begin - if(!wr_n) begin - addr0 = A0; - addr1 = ~A0; - end - if(!rd_n) begin - oen = A0; - //mode = ~A0; - end - end - // dout = result; - // dout = A0 ? 8'd0 : result; -end - - -always @(posedge clk) if(cen) begin - // if( !addr0 ) - // shift <= din[2:0]; - // if( !addr1 ) begin - // fifo[0] <= fifo[1]; - // fifo[1] <= din; - // end - if( cs && !wr_n ) begin - if( A0 ) begin - fifo[0] <= fifo[1]; - fifo[1] <= din; - end else begin - shift <= din[2:0]; - end - end - result <= (fifo[1] << shift) | (fifo[0] >> (4'd8-{1'b0,shift})); - // dout <= { result[7:3], A0 ? 3'd0 : result[2:0] }; - if( cs && !rd_n) dout <= A0 ? 8'd0 : result; -end - - -endmodule \ No newline at end of file