diff --git a/Arcade_MiST/IremM72 Hardware/IremM72.qsf b/Arcade_MiST/IremM72 Hardware/IremM72.qsf index 152eb751..2ff1dbe2 100644 --- a/Arcade_MiST/IremM72 Hardware/IremM72.qsf +++ b/Arcade_MiST/IremM72 Hardware/IremM72.qsf @@ -1,3 +1,4 @@ +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 # -------------------------------------------------------------------------- # # # Copyright (C) 1991-2013 Altera Corporation @@ -164,7 +165,7 @@ set_global_assignment -name USE_CONFIGURATION_DEVICE OFF # SignalTap II Assignments # ======================== set_global_assignment -name ENABLE_SIGNALTAP OFF -set_global_assignment -name USE_SIGNALTAP_FILE output_files/cpu3.stp +set_global_assignment -name USE_SIGNALTAP_FILE output_files/cpu2.stp # Power Estimation Assignments # ============================ @@ -233,11 +234,20 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top # end ENTITY(IremM72_MiST) # --------------------------- set_location_assignment PLL_1 -to pll|altpll_component|auto_generated|pll1 +set_global_assignment -name DSP_BLOCK_BALANCING "DSP BLOCKS" +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA +set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF set_global_assignment -name SYSTEMVERILOG_FILE rtl/IremM72_MiST.sv +set_global_assignment -name VERILOG_FILE rtl/build_id.v set_global_assignment -name QIP_FILE rtl/pll_mist.qip +set_global_assignment -name SYSTEMVERILOG_FILE rtl/ddr_debug.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/m72.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/pal.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/mcu.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sample_rom.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/m72_pkg.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/m72_pic.sv set_global_assignment -name VERILOG_FILE rtl/iir_filter.v @@ -247,8 +257,6 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/kna70h015.sv set_global_assignment -name VERILOG_FILE rtl/jtframe_frac_cen.v set_global_assignment -name SYSTEMVERILOG_FILE rtl/dualport_mailbox.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/dpramv.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/ddr_debug.sv -set_global_assignment -name VERILOG_FILE rtl/build_id.v set_global_assignment -name SYSTEMVERILOG_FILE rtl/board_b_d_layer.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/board_b_d.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/sprite.sv @@ -263,9 +271,4 @@ set_global_assignment -name QIP_FILE ../../common/Sound/jt51/jt51.qip set_global_assignment -name SIGNALTAP_FILE output_files/cpu.stp set_global_assignment -name SIGNALTAP_FILE output_files/cpu2.stp set_global_assignment -name SIGNALTAP_FILE output_files/cpu3.stp -set_global_assignment -name DSP_BLOCK_BALANCING "DSP BLOCKS" -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/IremM72 Hardware/Readme.md b/Arcade_MiST/IremM72 Hardware/Readme.md index 26187246..6eab9a76 100644 --- a/Arcade_MiST/IremM72 Hardware/Readme.md +++ b/Arcade_MiST/IremM72 Hardware/Readme.md @@ -2,7 +2,7 @@ ![](docs/header_small.png) -Implemention of the Irem M72 arcade hardware (https://www.system16.com/hardware.php?id=738) for the MiSTer FPGA platform. +Implemention of the Irem M72 & M84 arcade hardware (https://www.system16.com/hardware.php?id=738) for the MiSTer FPGA platform. [Original core](https://github.com/MiSTer-devel/Arcade-IremM72_MiSTer) by Martin Donlon. @@ -22,6 +22,9 @@ Implemention of the Irem M72 arcade hardware (https://www.system16.com/hardware. |[Dragon Breed](https://en.wikipedia.org/wiki/Dragon_Breed)|Japan|Conversion from M81 hardware.| |[X-Multiply](https://en.wikipedia.org/wiki/X_Multiply)|Japan|Conversion from M81 hardware.| |[Daiku no Gensan](https://en.wikipedia.org/wiki/Hammerin%27_Harry)|Japan|Conversion from M81 hardware. Emulated MCU| +|[R-Type II](https://en.wikipedia.org/wiki/R-Type_II)|Japan,World|M84 hardware.| +|[Hammerin' Harry](https://en.wikipedia.org/wiki/Hammerin%27_Harry)|US|M84 hardware.| + **Note:** Emulated MCU is not implemented on MiST (FPGA is full). diff --git a/Arcade_MiST/IremM72 Hardware/meta/Air Duel (Japan, M72 hardware).mra b/Arcade_MiST/IremM72 Hardware/meta/Air Duel (Japan, M72 hardware).mra index 94eb7326..336054f0 100644 --- a/Arcade_MiST/IremM72 Hardware/meta/Air Duel (Japan, M72 hardware).mra +++ b/Arcade_MiST/IremM72 Hardware/meta/Air Duel (Japan, M72 hardware).mra @@ -37,7 +37,7 @@ - 00 08 00 00 + 01 08 00 00 @@ -46,7 +46,7 @@ - 00 08 00 00 + 02 08 00 00 @@ -55,7 +55,7 @@ - 00 08 00 00 + 03 08 00 00 @@ -64,11 +64,11 @@ - 00 00 10 00 + 04 00 10 00 - 00 02 00 00 + 05 02 00 00 diff --git a/Arcade_MiST/IremM72 Hardware/meta/Dragon Breed (Japan, M72 hardware).mra b/Arcade_MiST/IremM72 Hardware/meta/Dragon Breed (Japan, M72 hardware).mra index c80e6eaf..9527d893 100644 --- a/Arcade_MiST/IremM72 Hardware/meta/Dragon Breed (Japan, M72 hardware).mra +++ b/Arcade_MiST/IremM72 Hardware/meta/Dragon Breed (Japan, M72 hardware).mra @@ -43,7 +43,7 @@ - 00 08 00 00 + 01 08 00 00 @@ -52,7 +52,7 @@ - 00 08 00 00 + 02 08 00 00 @@ -61,7 +61,7 @@ - 00 08 00 00 + 03 08 00 00 @@ -70,11 +70,11 @@ - 00 00 10 00 + 04 00 10 00 - 00 02 00 00 + 05 02 00 00 diff --git a/Arcade_MiST/IremM72 Hardware/meta/Gallop - Armed Police Unit (Japan, M72 hardware).mra b/Arcade_MiST/IremM72 Hardware/meta/Gallop - Armed Police Unit (Japan, M72 hardware).mra index 9768589e..fe6de640 100644 --- a/Arcade_MiST/IremM72 Hardware/meta/Gallop - Armed Police Unit (Japan, M72 hardware).mra +++ b/Arcade_MiST/IremM72 Hardware/meta/Gallop - Armed Police Unit (Japan, M72 hardware).mra @@ -39,7 +39,7 @@ - 00 08 00 00 + 01 08 00 00 @@ -48,7 +48,7 @@ - 00 04 00 00 + 02 04 00 00 @@ -57,12 +57,13 @@ - 00 04 00 00 + 03 04 00 00 + diff --git a/Arcade_MiST/IremM72 Hardware/meta/Hammerin' Harry (US, M84 hardware).mra b/Arcade_MiST/IremM72 Hardware/meta/Hammerin' Harry (US, M84 hardware).mra new file mode 100644 index 00000000..4ac6b62c --- /dev/null +++ b/Arcade_MiST/IremM72 Hardware/meta/Hammerin' Harry (US, M84 hardware).mra @@ -0,0 +1,75 @@ + + Hammerin' Harry (US, M84 hardware) + 0247 + hharryu + 1989 + Irem + Platformer + IremM72 + horizontal + + 8-way + 2 + + + + + + + + + + + + + + + + + + + 14 + + 00 08 00 00 + + + + + + + + + + + + + + + + 01 08 00 00 + + + + + + + + + 02 08 00 00 + + + + + + + + + 05 02 00 00 + + + + 08 01 00 00 + + + + \ No newline at end of file diff --git a/Arcade_MiST/IremM72 Hardware/meta/Image Fight (Japan).mra b/Arcade_MiST/IremM72 Hardware/meta/Image Fight (Japan).mra index c1fef8e0..57eeaca1 100644 --- a/Arcade_MiST/IremM72 Hardware/meta/Image Fight (Japan).mra +++ b/Arcade_MiST/IremM72 Hardware/meta/Image Fight (Japan).mra @@ -45,7 +45,7 @@ - 00 08 00 00 + 01 08 00 00 @@ -54,7 +54,7 @@ - 00 04 00 00 + 02 04 00 00 @@ -63,7 +63,7 @@ - 00 04 00 00 + 03 04 00 00 @@ -72,11 +72,11 @@ - 00 00 10 00 + 04 00 10 00 - 00 02 00 00 + 05 02 00 00 diff --git a/Arcade_MiST/IremM72 Hardware/meta/Image Fight (World).mra b/Arcade_MiST/IremM72 Hardware/meta/Image Fight (World).mra index db56e424..83e681b1 100644 --- a/Arcade_MiST/IremM72 Hardware/meta/Image Fight (World).mra +++ b/Arcade_MiST/IremM72 Hardware/meta/Image Fight (World).mra @@ -44,7 +44,7 @@ - 00 08 00 00 + 01 08 00 00 @@ -53,7 +53,7 @@ - 00 04 00 00 + 02 04 00 00 @@ -62,7 +62,7 @@ - 00 04 00 00 + 03 04 00 00 @@ -71,11 +71,11 @@ - 00 00 10 00 + 04 00 10 00 - 00 02 00 00 + 05 02 00 00 diff --git a/Arcade_MiST/IremM72 Hardware/meta/Legend of Hero Tonma (Japan).mra b/Arcade_MiST/IremM72 Hardware/meta/Legend of Hero Tonma (Japan).mra index 1723f33f..d46dbf26 100644 --- a/Arcade_MiST/IremM72 Hardware/meta/Legend of Hero Tonma (Japan).mra +++ b/Arcade_MiST/IremM72 Hardware/meta/Legend of Hero Tonma (Japan).mra @@ -39,7 +39,7 @@ - 00 08 00 00 + 01 08 00 00 @@ -48,7 +48,7 @@ - 00 04 00 00 + 02 04 00 00 @@ -57,7 +57,7 @@ - 00 04 00 00 + 03 04 00 00 @@ -66,11 +66,11 @@ - 00 00 10 00 + 04 00 10 00 - 00 01 00 00 + 05 01 00 00 diff --git a/Arcade_MiST/IremM72 Hardware/meta/Mr. HELI no Daibouken (Japan).mra b/Arcade_MiST/IremM72 Hardware/meta/Mr. HELI no Daibouken (Japan).mra index 751944b3..c95959de 100644 --- a/Arcade_MiST/IremM72 Hardware/meta/Mr. HELI no Daibouken (Japan).mra +++ b/Arcade_MiST/IremM72 Hardware/meta/Mr. HELI no Daibouken (Japan).mra @@ -50,7 +50,7 @@ - 00 08 00 00 + 01 08 00 00 @@ -59,7 +59,7 @@ - 00 04 00 00 + 02 04 00 00 @@ -68,7 +68,7 @@ - 00 04 00 00 + 03 04 00 00 @@ -77,11 +77,11 @@ - 00 00 10 00 + 04 00 10 00 - 00 01 00 00 + 05 01 00 00 diff --git a/Arcade_MiST/IremM72 Hardware/meta/Ninja Spirit (Japan).mra b/Arcade_MiST/IremM72 Hardware/meta/Ninja Spirit (Japan).mra index ecd626f4..e0d72b74 100644 --- a/Arcade_MiST/IremM72 Hardware/meta/Ninja Spirit (Japan).mra +++ b/Arcade_MiST/IremM72 Hardware/meta/Ninja Spirit (Japan).mra @@ -48,7 +48,7 @@ - 00 08 00 00 + 01 08 00 00 @@ -57,7 +57,7 @@ - 00 04 00 00 + 02 04 00 00 @@ -66,7 +66,7 @@ - 00 04 00 00 + 03 04 00 00 @@ -75,11 +75,11 @@ - 00 00 10 00 + 04 00 10 00 - 00 01 00 00 + 05 01 00 00 diff --git a/Arcade_MiST/IremM72 Hardware/meta/R-Type (Japan).mra b/Arcade_MiST/IremM72 Hardware/meta/R-Type (Japan).mra index 02e1ee91..3eb004e5 100644 --- a/Arcade_MiST/IremM72 Hardware/meta/R-Type (Japan).mra +++ b/Arcade_MiST/IremM72 Hardware/meta/R-Type (Japan).mra @@ -42,7 +42,7 @@ - 00 06 00 00 + 01 06 00 00 @@ -58,7 +58,7 @@ - 00 02 00 00 + 02 02 00 00 @@ -67,7 +67,7 @@ - 00 02 00 00 + 03 02 00 00 diff --git a/Arcade_MiST/IremM72 Hardware/meta/R-Type (World).mra b/Arcade_MiST/IremM72 Hardware/meta/R-Type (World).mra index d4ab0a84..ea9c53c3 100644 --- a/Arcade_MiST/IremM72 Hardware/meta/R-Type (World).mra +++ b/Arcade_MiST/IremM72 Hardware/meta/R-Type (World).mra @@ -40,7 +40,7 @@ - 00 06 00 00 + 01 06 00 00 @@ -56,7 +56,7 @@ - 00 02 00 00 + 02 02 00 00 @@ -65,7 +65,7 @@ - 00 02 00 00 + 03 02 00 00 diff --git a/Arcade_MiST/IremM72 Hardware/meta/R-Type II (Japan).mra b/Arcade_MiST/IremM72 Hardware/meta/R-Type II (Japan).mra new file mode 100644 index 00000000..15597ef5 --- /dev/null +++ b/Arcade_MiST/IremM72 Hardware/meta/R-Type II (Japan).mra @@ -0,0 +1,73 @@ + + R-Type II (Japan) + 0245 + rtype2j + rtype2 + 1989 + Irem + Shooter + IremM72 + horizontal + + 8-way + 2 + + + + + + + + + + + + + + + 13 + + 00 08 00 00 + + + + + + + + + + + 01 08 00 00 + + + + + + + + + 02 10 00 00 + + + + + + + + + + + + + + + 05 02 00 00 + + + + 08 01 00 00 + + + + diff --git a/Arcade_MiST/IremM72 Hardware/meta/R-Type II (World).mra b/Arcade_MiST/IremM72 Hardware/meta/R-Type II (World).mra new file mode 100644 index 00000000..b2c9da0b --- /dev/null +++ b/Arcade_MiST/IremM72 Hardware/meta/R-Type II (World).mra @@ -0,0 +1,72 @@ + + R-Type II (World) + 0245 + rtype2 + 1989 + Irem + Shooter + IremM72 + horizontal + + 8-way + 2 + + + + + + + + + + + + + + + 13 + + 00 08 00 00 + + + + + + + + + + + 01 08 00 00 + + + + + + + + + 02 10 00 00 + + + + + + + + + + + + + + + 05 02 00 00 + + + + 08 01 00 00 + + + + \ No newline at end of file diff --git a/Arcade_MiST/IremM72 Hardware/meta/X Multiply (Japan, M72 hardware).mra b/Arcade_MiST/IremM72 Hardware/meta/X Multiply (Japan, M72 hardware).mra index 2b05fa69..68533798 100644 --- a/Arcade_MiST/IremM72 Hardware/meta/X Multiply (Japan, M72 hardware).mra +++ b/Arcade_MiST/IremM72 Hardware/meta/X Multiply (Japan, M72 hardware).mra @@ -12,7 +12,7 @@ 8-way 1 - + @@ -43,7 +43,7 @@ - 00 10 00 00 + 01 10 00 00 @@ -58,7 +58,7 @@ - 00 08 00 00 + 02 08 00 00 @@ -67,7 +67,7 @@ - 00 08 00 00 + 03 08 00 00 @@ -76,11 +76,11 @@ - 00 00 10 00 + 04 00 10 00 - 00 02 00 00 + 05 02 00 00 diff --git a/Arcade_MiST/IremM72 Hardware/rtl/Arcade-IremM72.sv b/Arcade_MiST/IremM72 Hardware/rtl/Arcade-IremM72.sv deleted file mode 100644 index 479b3ade..00000000 --- a/Arcade_MiST/IremM72 Hardware/rtl/Arcade-IremM72.sv +++ /dev/null @@ -1,675 +0,0 @@ -//============================================================================ -// Irem M72 for MiSTer FPGA -// -// Copyright (C) 2022 Martin Donlon -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -//============================================================================ - - -import m72_pkg::*; - -module emu -( - //Master input clock - input CLK_50M, - - //Async reset from top-level module. - //Can be used as initial reset. - input RESET, - - //Must be passed to hps_io module - inout [48:0] HPS_BUS, - - //Base video clock. Usually equals to CLK_SYS. - output CLK_VIDEO, - - //Multiple resolutions are supported using different CE_PIXEL rates. - //Must be based on CLK_VIDEO - output CE_PIXEL, - - //Video aspect ratio for HDMI. Most retro systems have ratio 4:3. - //if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio. - output [12:0] VIDEO_ARX, - output [12:0] VIDEO_ARY, - - output [7:0] VGA_R, - output [7:0] VGA_G, - output [7:0] VGA_B, - output VGA_HS, - output VGA_VS, - output VGA_DE, // = ~(VBlank | HBlank) - output VGA_F1, - output [1:0] VGA_SL, - output VGA_SCALER, // Force VGA scaler - - input [11:0] HDMI_WIDTH, - input [11:0] HDMI_HEIGHT, - output HDMI_FREEZE, - -`ifdef MISTER_FB - // Use framebuffer in DDRAM (USE_FB=1 in qsf) - // FB_FORMAT: - // [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp - // [3] : 0=16bits 565 1=16bits 1555 - // [4] : 0=RGB 1=BGR (for 16/24/32 modes) - // - // FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes) - output FB_EN, - output [4:0] FB_FORMAT, - output [11:0] FB_WIDTH, - output [11:0] FB_HEIGHT, - output [31:0] FB_BASE, - output [13:0] FB_STRIDE, - input FB_VBL, - input FB_LL, - output FB_FORCE_BLANK, - -`ifdef MISTER_FB_PALETTE - // Palette control for 8bit modes. - // Ignored for other video modes. - output FB_PAL_CLK, - output [7:0] FB_PAL_ADDR, - output [23:0] FB_PAL_DOUT, - input [23:0] FB_PAL_DIN, - output FB_PAL_WR, -`endif -`endif - - output LED_USER, // 1 - ON, 0 - OFF. - - // b[1]: 0 - LED status is system status OR'd with b[0] - // 1 - LED status is controled solely by b[0] - // hint: supply 2'b00 to let the system control the LED. - output [1:0] LED_POWER, - output [1:0] LED_DISK, - - // I/O board button press simulation (active high) - // b[1]: user button - // b[0]: osd button - output [1:0] BUTTONS, - - input CLK_AUDIO, // 24.576 MHz - output [15:0] AUDIO_L, - output [15:0] AUDIO_R, - output AUDIO_S, // 1 - signed audio samples, 0 - unsigned - output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono) - - //ADC - inout [3:0] ADC_BUS, - - //SD-SPI - output SD_SCK, - output SD_MOSI, - input SD_MISO, - output SD_CS, - input SD_CD, - - //High latency DDR3 RAM interface - //Use for non-critical time purposes - output DDRAM_CLK, - input DDRAM_BUSY, - output [7:0] DDRAM_BURSTCNT, - output [28:0] DDRAM_ADDR, - input [63:0] DDRAM_DOUT, - input DDRAM_DOUT_READY, - output DDRAM_RD, - output [63:0] DDRAM_DIN, - output [7:0] DDRAM_BE, - output DDRAM_WE, - - //SDRAM interface with lower latency - output SDRAM_CLK, - output SDRAM_CKE, - output [12:0] SDRAM_A, - output [1:0] SDRAM_BA, - inout [15:0] SDRAM_DQ, - output SDRAM_DQML, - output SDRAM_DQMH, - output SDRAM_nCS, - output SDRAM_nCAS, - output SDRAM_nRAS, - output SDRAM_nWE, - -`ifdef MISTER_DUAL_SDRAM - //Secondary SDRAM - //Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0 - input SDRAM2_EN, - output SDRAM2_CLK, - output [12:0] SDRAM2_A, - output [1:0] SDRAM2_BA, - inout [15:0] SDRAM2_DQ, - output SDRAM2_nCS, - output SDRAM2_nCAS, - output SDRAM2_nRAS, - output SDRAM2_nWE, -`endif - - input UART_CTS, - output UART_RTS, - input UART_RXD, - output UART_TXD, - output UART_DTR, - input UART_DSR, - - // Open-drain User port. - // 0 - D+/RX - // 1 - D-/TX - // 2..6 - USR2..USR6 - // Set USER_OUT to 1 to read from USER_IN. - input [6:0] USER_IN, - output [6:0] USER_OUT, - - input OSD_STATUS -); - -///////// Default values for ports not used in this core ///////// - -assign ADC_BUS = 'Z; -assign USER_OUT = '1; -assign {UART_RTS, UART_TXD, UART_DTR} = 0; -assign {SD_SCK, SD_MOSI, SD_CS} = 'Z; -assign CLK_VIDEO = CLK_32M; - -assign VGA_F1 = 0; -assign VGA_SCALER = 0; - -assign AUDIO_S = 1; -assign AUDIO_MIX = 0; - -assign LED_DISK = 0; -assign LED_POWER = 0; -assign BUTTONS = 0; - -////////////////////////////////////////////////////////////////// - -wire [1:0] ar = status[2:1]; -wire [1:0] scandoubler_fx = status[4:3]; -wire [1:0] scale = status[6:5]; -wire pause_in_osd = status[7]; -wire system_pause; - -assign VGA_SL = scandoubler_fx; -assign HDMI_FREEZE = 0; //system_pause; - -wire en_layer_a = ~status[64]; -wire en_layer_b = ~status[65]; -wire en_sprites = ~status[66]; -wire en_layer_palette = ~status[67]; -wire en_sprite_palette = ~status[68]; -wire dbg_sprite_freeze = status[69]; -wire en_audio_filters = ~status[70]; - -wire video_60hz = status[9:8] == 2'd3; -wire video_57hz = status[9:8] == 2'd2; -wire video_50hz = status[9:8] == 2'd1; - -// If video timing changes, force mode update -reg [1:0] video_status; -reg new_vmode = 0; -always @(posedge clk_sys) begin - if (video_status != status[9:8]) begin - video_status <= status[9:8]; - new_vmode <= ~new_vmode; - end -end - -`include "build_id.v" -localparam CONF_STR = { - "M72;;", - "-;", - "O[2:1],Aspect ratio,Original,Full Screen,[ARC1],[ARC2];", - "O[4:3],Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;", - "O[6:5],Scale,Normal,V-Integer,Narrower HV-Integer,Wider HV-Integer;", - "O[7],OSD Pause,Off,On;", - "O[9:8],Video Timing,Normal,50Hz,57Hz,60Hz;", - "O[10],Orientation,Horz,Vert;", - "-;", - "DIP;", - "-;", - "P1,Debug;", - "P1-;", - "P1O[64],Layer A,On,Off;", - "P1O[65],Layer B,On,Off;", - "P1O[66],Sprites,On,Off;", - "P1O[67],Layer Palette,On,Off;", - "P1O[68],Sprite Palette,On,Off;", - "P1O[69],Sprite Freeze,Off,On;", - "P1O[70],Audio Filtering,On,Off;", - "-;", - "T[0],Reset;", - "DEFMRA,/_Arcade/m72.mra;", - "V,v",`BUILD_DATE -}; - -wire forced_scandoubler; -wire [1:0] buttons; -wire [128:0] status; -wire [10:0] ps2_key; - -wire ioctl_download; -wire ioctl_upload; -wire ioctl_upload_req = 0; -wire [7:0] ioctl_index; -wire ioctl_wr; -wire [24:0] ioctl_addr; -wire [7:0] ioctl_dout; -wire [7:0] ioctl_din = 0; -wire ioctl_wait; - -wire [15:0] joystick_0, joystick_1; -wire [15:0] joy = joystick_0 | joystick_1; - -wire [21:0] gamma_bus; -wire direct_video; -wire video_rotated; -wire no_rotate = ~status[10]; -wire flip = 0; -wire rotate_ccw = 1; - -wire clk_sys = CLK_32M; - -hps_io #(.CONF_STR(CONF_STR)) hps_io -( - .clk_sys(clk_sys), - .HPS_BUS(HPS_BUS), - .EXT_BUS(), - .gamma_bus(gamma_bus), - .direct_video(direct_video), - - .forced_scandoubler(forced_scandoubler), - .new_vmode(new_vmode), - .video_rotated(video_rotated), - - .buttons(buttons), - .status(status), - .status_menumask({direct_video}), - - .ioctl_download(ioctl_download), - .ioctl_upload(ioctl_upload), - .ioctl_upload_req(ioctl_upload_req), - .ioctl_wr(ioctl_wr), - .ioctl_addr(ioctl_addr), - .ioctl_dout(ioctl_dout), - .ioctl_din(ioctl_din), - .ioctl_index(ioctl_index), - .ioctl_wait(ioctl_wait), - - .joystick_0(joystick_0), - .joystick_1(joystick_1), - .ps2_key(ps2_key) -); - -/////////////////////// CLOCKS /////////////////////////////// - -wire CLK_32M; -wire CLK_96M; -wire pll_locked; -pll pll -( - .refclk(CLK_50M), - .rst(0), - .outclk_0(CLK_96M), - .outclk_1(CLK_32M), - .locked(pll_locked) -); - -wire reset = RESET | status[0] | buttons[1]; - -/////////////////////////////////////////////////////////////////////// -// SDRAM -/////////////////////////////////////////////////////////////////////// -wire [63:0] sdr_sprite_dout; -wire [24:1] sdr_sprite_addr; -wire sdr_sprite_req, sdr_sprite_rdy; - -wire [31:0] sdr_bg_dout; -wire [24:1] sdr_bg_addr; -wire sdr_bg_req, sdr_bg_rdy; - -wire [15:0] sdr_cpu_dout, sdr_cpu_din; -wire [24:1] sdr_cpu_addr; -wire sdr_cpu_req; -wire [1:0] sdr_cpu_wr_sel; - -reg [24:1] sdr_rom_addr; -reg [15:0] sdr_rom_data; -reg [1:0] sdr_rom_be; -reg sdr_rom_req; - -wire sdr_rom_write = ioctl_download && (ioctl_index == 0); -wire [24:1] sdr_ch3_addr = sdr_rom_write ? sdr_rom_addr : sdr_cpu_addr; -wire [15:0] sdr_ch3_din = sdr_rom_write ? sdr_rom_data : sdr_cpu_din; -wire [1:0] sdr_ch3_be = sdr_rom_write ? sdr_rom_be : sdr_cpu_wr_sel; -wire sdr_ch3_rnw = sdr_rom_write ? 1'b0 : ~{|sdr_cpu_wr_sel}; -wire sdr_ch3_req = sdr_rom_write ? sdr_rom_req : sdr_cpu_req; -wire sdr_ch3_rdy; -wire sdr_cpu_rdy = sdr_ch3_rdy; -wire sdr_rom_rdy = sdr_ch3_rdy; - -wire [19:0] bram_addr; -wire [7:0] bram_data; -wire [1:0] bram_cs; -wire bram_wr; - -board_cfg_t board_cfg; - -sdram sdram -( - .*, - .doRefresh(0), - .init(~pll_locked), - .clk(CLK_96M), - - .ch1_addr(sdr_bg_addr), - .ch1_dout(sdr_bg_dout), - .ch1_req(sdr_bg_req), - .ch1_ready(sdr_bg_rdy), - - .ch2_addr(sdr_sprite_addr), - .ch2_dout(sdr_sprite_dout), - .ch2_req(sdr_sprite_req), - .ch2_ready(sdr_sprite_rdy), - - // multiplexed with rom download and cpu read/writes - .ch3_addr(sdr_ch3_addr), - .ch3_din(sdr_ch3_din), - .ch3_dout(sdr_cpu_dout), - .ch3_be(sdr_ch3_be), - .ch3_rnw(sdr_ch3_rnw), - .ch3_req(sdr_ch3_req), - .ch3_ready(sdr_ch3_rdy) -); - -rom_loader rom_loader( - .sys_clk(clk_sys), - .ram_clk(CLK_96M), - - .ioctl_wr(ioctl_wr && !ioctl_index), - .ioctl_data(ioctl_dout[7:0]), - - .ioctl_wait(ioctl_wait), - - .sdr_addr(sdr_rom_addr), - .sdr_data(sdr_rom_data), - .sdr_be(sdr_rom_be), - .sdr_req(sdr_rom_req), - .sdr_rdy(sdr_rom_rdy), - - .bram_addr(bram_addr), - .bram_data(bram_data), - .bram_cs(bram_cs), - .bram_wr(bram_wr), - - .board_cfg(board_cfg) -); - -/////////////////// Keyboard ////////////////// -reg btn_up = 0; -reg btn_down = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_a = 0; -reg btn_b = 0; -reg btn_x = 0; -reg btn_y = 0; -reg btn_coin1 = 0; -reg btn_coin2 = 0; -reg btn_1p_start = 0; -reg btn_2p_start = 0; -reg btn_pause = 0; - -wire pressed = ps2_key[9]; -wire [7:0] code = ps2_key[7:0]; -always @(posedge CLK_32M) begin - reg old_state; - old_state <= ps2_key[10]; - if(old_state != ps2_key[10]) begin - case(code) - 'h16: btn_1p_start <= pressed; // 1 - 'h1E: btn_2p_start <= pressed; // 2 - 'h2E: btn_coin1 <= pressed; // 5 - 'h36: btn_coin2 <= pressed; // 6 - 'h4D: btn_pause <= pressed; // P - - 'h75: btn_up <= pressed; // up - 'h72: btn_down <= pressed; // down - 'h6B: btn_left <= pressed; // left - 'h74: btn_right <= pressed; // right - 'h14: btn_a <= pressed; // ctrl - 'h11: btn_b <= pressed; // alt - 'h29: btn_x <= pressed; // space - 'h12: btn_y <= pressed; // shift - endcase - end -end - -// DIP SWITCHES -reg [7:0] dip_sw[8]; // Active-LOW -always @(posedge CLK_32M) begin - if(ioctl_wr && (ioctl_index==254) && !ioctl_addr[24:3]) - dip_sw[ioctl_addr[2:0]] <= ioctl_dout; -end - - -////////////////// Arcade Buttons/Interfaces /////////////////////////// - -//Player 1 -wire m_up1 = btn_up | joystick_0[3]; -wire m_down1 = btn_down | joystick_0[2]; -wire m_left1 = btn_left | joystick_0[1]; -wire m_right1 = btn_right | joystick_0[0]; -wire m_btna1 = btn_a | joystick_0[4]; -wire m_btnb1 = btn_b | joystick_0[5]; -wire m_btnx1 = btn_x | joystick_0[6]; -wire m_btny1 = btn_y | joystick_0[7]; - -//Player 2 -wire m_up2 = btn_up | joystick_1[3]; -wire m_down2 = btn_down | joystick_1[2]; -wire m_left2 = btn_left | joystick_1[1]; -wire m_right2 = btn_right | joystick_1[0]; -wire m_btna2 = btn_a | joystick_1[4]; -wire m_btnb2 = btn_b | joystick_1[5]; -wire m_btnx2 = btn_x | joystick_1[6]; -wire m_btny2 = btn_y | joystick_1[7]; - -//Start/coin -wire m_start1 = btn_1p_start | joy[8]; -wire m_start2 = btn_2p_start | joy[10]; -wire m_coin1 = btn_coin1 | joy[9]; -wire m_coin2 = btn_coin2; -wire m_pause = btn_pause | joy[11]; - -////////////////////////////////////////////////////////////////// - -wire [7:0] R, G, B; -wire HBlank, VBlank, HSync, VSync; -wire ce_pix; - -m72 m72( - .CLK_32M(CLK_32M), - .CLK_96M(CLK_96M), - .ce_pix(ce_pix), - .reset_n(~reset), - .HBlank(HBlank), - .VBlank(VBlank), - .HSync(HSync), - .VSync(VSync), - .R(R), - .G(G), - .B(B), - .AUDIO_L(AUDIO_L), - .AUDIO_R(AUDIO_R), - - .board_cfg(board_cfg), - - .coin({~m_coin2, ~m_coin1}), - - .start_buttons({~m_start2, ~m_start1}), - - .p1_joystick({~m_up1, ~m_down1, ~m_left1, ~m_right1}), - .p2_joystick({~m_up2, ~m_down2, ~m_left2, ~m_right2}), - .p1_buttons({~m_btna1, ~m_btnb1, ~m_btnx1, ~m_btny1}), - .p2_buttons({~m_btna2, ~m_btnb2, ~m_btnx2, ~m_btny2}), - - .dip_sw({~dip_sw[1], ~dip_sw[0]}), - - .sdr_sprite_addr(sdr_sprite_addr), - .sdr_sprite_dout(sdr_sprite_dout), - .sdr_sprite_req(sdr_sprite_req), - .sdr_sprite_rdy(sdr_sprite_rdy), - - .sdr_bg_addr(sdr_bg_addr), - .sdr_bg_dout(sdr_bg_dout), - .sdr_bg_req(sdr_bg_req), - .sdr_bg_rdy(sdr_bg_rdy), - - .sdr_cpu_dout(sdr_cpu_dout), - .sdr_cpu_din(sdr_cpu_din), - .sdr_cpu_addr(sdr_cpu_addr), - .sdr_cpu_req(sdr_cpu_req), - .sdr_cpu_rdy(sdr_cpu_rdy), - .sdr_cpu_wr_sel(sdr_cpu_wr_sel), - - .clk_bram(clk_sys), - .bram_addr(bram_addr), - .bram_data(bram_data), - .bram_cs(bram_cs), - .bram_wr(bram_wr), - -`ifdef M72_DEBUG - .pause_rq(system_pause | debug_stall), -`else - .pause_rq(system_pause), -`endif - .ddr_debug_data(ddr_debug_data), - - .en_layer_a(en_layer_a), - .en_layer_b(en_layer_b), - .en_sprites(en_sprites), - .en_layer_palette(en_layer_palette), - .en_sprite_palette(en_sprite_palette), - .en_audio_filters(en_audio_filters), - - .sprite_freeze(dbg_sprite_freeze), - - .video_50hz(video_50hz), - .video_57hz(video_57hz), - .video_60hz(video_60hz) -); - - -wire gamma_hsync, gamma_vsync, gamma_hblank, gamma_vblank; -wire [7:0] gamma_r, gamma_g, gamma_b; -gamma_fast video_gamma -( - .clk_vid(CLK_VIDEO), - .ce_pix(ce_pix), - .gamma_bus(gamma_bus), - .HSync(HSync), - .VSync(VSync), - .HBlank(HBlank), - .VBlank(VBlank), - .DE(), - .RGB_in({R, G, B}), - .HSync_out(gamma_hsync), - .VSync_out(gamma_vsync), - .HBlank_out(gamma_hblank), - .VBlank_out(gamma_vblank), - .DE_out(), - .RGB_out({gamma_r, gamma_g, gamma_b}) -); - -wire VGA_DE_MIXER; -video_mixer #(386, 0, 0) video_mixer( - .CLK_VIDEO(CLK_VIDEO), - .CE_PIXEL(CE_PIXEL), - .ce_pix(ce_pix), - - .scandoubler(forced_scandoubler || scandoubler_fx != 2'b00), - .hq2x(0), - - .gamma_bus(), - - .R(gamma_r), - .G(gamma_g), - .B(gamma_b), - - .HBlank(gamma_hblank), - .VBlank(gamma_vblank), - .HSync(gamma_hsync), - .VSync(gamma_vsync), - - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .VGA_DE(VGA_DE_MIXER), - - .HDMI_FREEZE(HDMI_FREEZE) -); - - -video_freak video_freak( - .CLK_VIDEO(CLK_VIDEO), - .CE_PIXEL(CE_PIXEL), - .VGA_VS(VGA_VS), - .HDMI_WIDTH(HDMI_WIDTH), - .HDMI_HEIGHT(HDMI_HEIGHT), - .VGA_DE(VGA_DE), - .VIDEO_ARX(VIDEO_ARX), - .VIDEO_ARY(VIDEO_ARY), - - .VGA_DE_IN(VGA_DE_MIXER), - .ARX((!ar) ? ( no_rotate ? 12'd4 : 12'd3 ) : (ar - 1'd1)), - .ARY((!ar) ? ( no_rotate ? 12'd3 : 12'd4 ) : 12'd0), - .CROP_SIZE(0), - .CROP_OFF(0), - .SCALE(scale) -); - - -pause pause( - .clk_sys(clk_sys), - .reset(reset), - .user_button(m_pause), - .pause_request(0), - .options({1'b0, pause_in_osd}), - .pause_cpu(system_pause), - .OSD_STATUS(OSD_STATUS) -); - -`ifndef M72_DEBUG // debug uses DDR -screen_rotate screen_rotate(.*); -`endif - - - -ddr_debug_data_t ddr_debug_data; - -`ifdef M72_DEBUG -wire debug_stall; -ddr_debug ddr_debug( - .*, - .data(ddr_debug_data), - .clk(CLK_96M), - .reset(reset | ~pll_locked), - .stall(debug_stall) -); -`endif - -endmodule diff --git a/Arcade_MiST/IremM72 Hardware/rtl/IremM72_MiST.sv b/Arcade_MiST/IremM72 Hardware/rtl/IremM72_MiST.sv index dd351ab4..f2bb6e53 100644 --- a/Arcade_MiST/IremM72 Hardware/rtl/IremM72_MiST.sv +++ b/Arcade_MiST/IremM72 Hardware/rtl/IremM72_MiST.sv @@ -33,7 +33,10 @@ module IremM72_MiST( `include "rtl/build_id.v" -`define CORE_NAME "LOHTJ" +`define CORE_NAME "RTYPE2" +//`define CORE_NAME "HHARRYU" +//`define CORE_NAME "GALLOP" +//`define CORE_NAME "LOHTJ" //`define CORE_NAME "MRHELI" //`define CORE_NAME "AIRDUM72" //`define CORE_NAME "RTYPE" @@ -166,19 +169,19 @@ wire [24:1] sdr_sprite_addr; wire sdr_sprite_req, sdr_sprite_ack; wire [31:0] sdr_bg_data_a; -wire [24:1] sdr_bg_addr_a; +wire [24:0] sdr_bg_addr_a; wire sdr_bg_req_a, sdr_bg_ack_a; wire [31:0] sdr_bg_data_b; -wire [24:1] sdr_bg_addr_b; +wire [24:0] sdr_bg_addr_b; wire sdr_bg_req_b, sdr_bg_ack_b; wire [15:0] sdr_cpu_dout, sdr_cpu_din; -wire [24:1] sdr_cpu_addr; +wire [24:0] sdr_cpu_addr; wire sdr_cpu_req, sdr_cpu_ack; wire [1:0] sdr_cpu_wr_sel; -wire [24:1] sdr_rom_addr; +wire [24:0] sdr_rom_addr; wire [15:0] sdr_rom_data; wire [1:0] sdr_rom_be; wire sdr_rom_req; @@ -193,7 +196,7 @@ wire sdr_z80_ram_cs; wire sdr_z80_ram_valid; wire [24:0] sample_rom_addr; -wire [63:0] sample_rom_data; +wire [63:0] sample_rom_dout; wire sample_rom_req; wire sample_rom_ack; @@ -201,7 +204,7 @@ wire sdr_rom_write = ioctl_downl && (ioctl_index == 0); wire [19:0] bram_addr; wire [7:0] bram_data; -wire [1:0] bram_cs; +wire [3:0] bram_cs; wire bram_wr; board_cfg_t board_cfg; @@ -212,7 +215,7 @@ sdram_4w #(96) sdram .clk ( CLK_96M ), // Bank 0-1 ops - .port1_a ( sdr_rom_addr ), + .port1_a ( sdr_rom_addr[24:1] ), .port1_req ( sdr_rom_req ), .port1_ack ( sdr_rom_ack ), .port1_we ( sdr_rom_write ), @@ -228,7 +231,7 @@ sdram_4w #(96) sdram .cpu1_ram_req ( sdr_cpu_req ), .cpu1_ram_ack ( sdr_cpu_ack ), - .cpu1_ram_addr ( sdr_cpu_addr ), + .cpu1_ram_addr ( sdr_cpu_addr[24:1] ), .cpu1_ram_we ( |sdr_cpu_wr_sel ), .cpu1_ram_d ( sdr_cpu_din ), .cpu1_ram_q ( sdr_cpu_dout ), @@ -250,7 +253,7 @@ sdram_4w #(96) sdram .cpu3_ack ( ), // Bank 2-3 ops - .port2_a ( sdr_rom_addr ), + .port2_a ( sdr_rom_addr[24:1] ), .port2_req ( sdr_rom_req ), .port2_ack ( sdr_rom_ack ), .port2_we ( sdr_rom_write ), @@ -260,16 +263,16 @@ sdram_4w #(96) sdram .gfx1_req ( sdr_bg_req_a ), .gfx1_ack ( sdr_bg_ack_a ), - .gfx1_addr ( sdr_bg_addr_a ), + .gfx1_addr ( sdr_bg_addr_a[24:1] ), .gfx1_q ( sdr_bg_data_a ), .gfx2_req ( sdr_bg_req_b ), .gfx2_ack ( sdr_bg_ack_b ), - .gfx2_addr ( sdr_bg_addr_b ), + .gfx2_addr ( sdr_bg_addr_b[24:1] ), .gfx2_q ( sdr_bg_data_b ), .sample_addr ( {sample_rom_addr[22:3], 2'b00} ), - .sample_data ( sample_rom_data ), + .sample_q ( sample_rom_dout ), .sample_req ( sample_rom_req ), .sample_ack ( sample_rom_ack ), @@ -368,7 +371,7 @@ m72 m72( .sdr_z80_ram_valid(sdr_z80_ram_valid), .sample_rom_addr(sample_rom_addr), - .sample_rom_data(sample_rom_data), + .sample_rom_dout(sample_rom_dout), .sample_rom_req(sample_rom_req), .sample_rom_ack(sample_rom_ack), diff --git a/Arcade_MiST/IremM72 Hardware/rtl/board_b_d.sv b/Arcade_MiST/IremM72 Hardware/rtl/board_b_d.sv index c9ae1d69..c9a82629 100644 --- a/Arcade_MiST/IremM72 Hardware/rtl/board_b_d.sv +++ b/Arcade_MiST/IremM72 Hardware/rtl/board_b_d.sv @@ -37,8 +37,9 @@ module board_b_d ( input MWR, input IORD, input IOWR, - input CHARA, - input CHARA_P, + input a_memrq, + input b_memrq, + input palette_memrq, input NL, input [8:0] VE, @@ -50,12 +51,12 @@ module board_b_d ( output P1L, input [31:0] sdr_data_a, - output [24:1] sdr_addr_a, + output [24:0] sdr_addr_a, output sdr_req_a, input sdr_ack_a, input [31:0] sdr_data_b, - output [24:1] sdr_addr_b, + output [24:0] sdr_addr_b, output sdr_req_b, input sdr_ack_b, @@ -63,15 +64,17 @@ module board_b_d ( input en_layer_a, input en_layer_b, - input en_palette + input en_palette, + + input m84 ); // M72-B-D 1/8 // Didn't implement WAIT signal -wire WRA = MWR & CHARA & ~A[15]; -wire WRB = MWR & CHARA & A[15]; -wire RDA = MRD & CHARA & ~A[15]; -wire RDB = MRD & CHARA & A[15]; +wire WRA = MWR & a_memrq; +wire WRB = MWR & b_memrq; +wire RDA = MRD & a_memrq; +wire RDB = MRD & b_memrq; wire VSCKA = IOWR & (IO_A[7:6] == 2'b10) & (IO_A[3:1] == 3'b000); wire HSCKA = IOWR & (IO_A[7:6] == 2'b10) & (IO_A[3:1] == 3'b001); @@ -89,9 +92,9 @@ wire [15:0] DOUT_A, DOUT_B; assign DOUT = pal_dout_valid ? pal_dout : RDA ? DOUT_A : DOUT_B; assign DOUT_VALID = RDA | RDB | pal_dout_valid; -wire [17:0] addr_a, addr_b; -assign sdr_addr_a = { REGION_BG_A.base_addr[24:19], addr_a }; -assign sdr_addr_b = { REGION_BG_B.base_addr[24:19], addr_b }; +wire [20:0] addr_a, addr_b; +assign sdr_addr_a = { REGION_BG_A.base_addr[24:21], addr_a }; +assign sdr_addr_b = { m84 ? REGION_BG_A.base_addr[24:21] : REGION_BG_B.base_addr[24:21], addr_b }; board_b_d_layer layer_a( .CLK_32M(CLK_32M), @@ -125,7 +128,9 @@ board_b_d_layer layer_a( .sdr_ack(sdr_ack_a), .enabled(en_layer_a), - .paused(paused) + .paused(paused), + + .m84(m84) ); board_b_d_layer layer_b( @@ -160,7 +165,9 @@ board_b_d_layer layer_b( .sdr_ack(sdr_ack_b), .enabled(en_layer_b), - .paused(paused) + .paused(paused), + + .m84(m84) ); wire [4:0] r_out, g_out, b_out; @@ -176,8 +183,9 @@ assign P1L = ~(CP15A & a_opaque) & ~(CP15B & b_opaque) & ~(CP8A & BITA[3]) & ~(C kna91h014 kna91h014( .CLK_32M(CLK_32M), + .CE_PIX(CE_PIX), - .G(CHARA_P), + .G(palette_memrq), .SELECT(S), .CA({COLA, BITA}), .CB({COLB, BITB}), diff --git a/Arcade_MiST/IremM72 Hardware/rtl/board_b_d_layer.sv b/Arcade_MiST/IremM72 Hardware/rtl/board_b_d_layer.sv index 7f59dac3..b2e287bf 100644 --- a/Arcade_MiST/IremM72 Hardware/rtl/board_b_d_layer.sv +++ b/Arcade_MiST/IremM72 Hardware/rtl/board_b_d_layer.sv @@ -40,51 +40,83 @@ module board_b_d_layer( input [8:0] HE, output [3:0] BIT, - output [3:0] COL, - output CP15, - output CP8, + output reg [3:0] COL, + output reg CP15, + output reg CP8, input [31:0] sdr_data, - output [17:0] sdr_addr, - output sdr_req, + output [20:0] sdr_addr, + output reg sdr_req, input sdr_ack, input enabled, - input paused + input paused, + + input m84 ); -assign DOUT = { dout_h, dout_l }; +assign DOUT = A[1] ? { dout_11, dout_10 } : { dout_01 , dout_00 }; -wire [7:0] dout_h, dout_l; +wire [7:0] dout_00, dout_01, dout_10, dout_11; -dpramv #(.widthad_a(13)) ram_l +dpramv #(.widthad_a(12)) ram_00 ( .clock_a(CLK_32M), - .address_a(A[13:1]), - .q_a(dout_l), - .wren_a(WR & BYTE_SEL[0]), + .address_a(A[13:2]), + .q_a(dout_00), + .wren_a(WR & ~A[1] & BYTE_SEL[0]), .data_a(DIN[7:0]), .clock_b(CLK_32M), - .address_b({SV[8:3], SH[8:2]}), + .address_b({SV[8:3], SH[8:3]}), .data_b(), .wren_b(1'd0), - .q_b(ram_l_dout) + .q_b(ram_00_dout) ); -dpramv #(.widthad_a(13)) ram_h +dpramv #(.widthad_a(12)) ram_01 ( .clock_a(CLK_32M), - .address_a(A[13:1]), - .q_a(dout_h), - .wren_a(WR & BYTE_SEL[1]), + .address_a(A[13:2]), + .q_a(dout_01), + .wren_a(WR & ~A[1] & BYTE_SEL[1]), .data_a(DIN[15:8]), .clock_b(CLK_32M), - .address_b({SV[8:3], SH[8:2]}), + .address_b({SV[8:3], SH[8:3]}), .data_b(), .wren_b(1'd0), - .q_b(ram_h_dout) + .q_b(ram_01_dout) +); + +dpramv #(.widthad_a(12)) ram_10 +( + .clock_a(CLK_32M), + .address_a(A[13:2]), + .q_a(dout_10), + .wren_a(WR & A[1] & BYTE_SEL[0]), + .data_a(DIN[7:0]), + + .clock_b(CLK_32M), + .address_b({SV[8:3], SH[8:3]}), + .data_b(), + .wren_b(1'd0), + .q_b(ram_10_dout) +); + +dpramv #(.widthad_a(12)) ram_11 +( + .clock_a(CLK_32M), + .address_a(A[13:2]), + .q_a(dout_11), + .wren_a(WR & A[1] & BYTE_SEL[1]), + .data_a(DIN[15:8]), + + .clock_b(CLK_32M), + .address_b({SV[8:3], SH[8:3]}), + .data_b(), + .wren_b(1'd0), + .q_b(ram_11_dout) ); reg [31:0] rom_data; @@ -109,39 +141,37 @@ kna6034201 kna6034201( ); wire [8:0] SV = VE + adj_v; -wire [8:0] SH = ( HE + adj_h ) ^ { 6'b0, {3{NL}} }; +wire [8:0] SH = ( ( m84 ? HE - 9'd4 : HE ) + adj_h ) ^ { 6'b0, {3{NL}} }; reg [8:0] adj_v; reg [8:0] adj_h; reg HREV1, VREV, HREV2; -reg [13:0] COD; -reg [7:0] row_data1, row_data; +reg [15:0] COD; wire [2:0] RV = SV[2:0] ^ {3{VREV}}; -wire [7:0] ram_h_dout, ram_l_dout; +wire [7:0] ram_00_dout, ram_01_dout, ram_10_dout, ram_11_dout; +wire [15:0] attrib_0 = { ram_01_dout, ram_00_dout }; +wire [15:0] attrib_1 = { ram_11_dout, ram_10_dout }; -assign COL = row_data[3:0]; -assign CP15 = row_data[7]; -assign CP8 = row_data[6]; assign BIT = (HREV2 ^ NL) ? BITR : BITF; //reg [17:0] paused_offsets[512]; -//reg [8:0] ve_latch; +reg [8:0] ve_latch; always @(posedge CLK_32M) begin - //ve_latch <= VE; - //if (paused) begin - //{adj_v, adj_h} <= paused_offsets[ve_latch]; - //end else begin +// ve_latch <= VE; +// if (paused) begin +// {adj_v, adj_h} <= paused_offsets[ve_latch]; +// end else begin if (VSCK & ~IO_A[0]) adj_v[7:0] <= IO_DIN[7:0]; if (HSCK & ~IO_A[0]) adj_h[7:0] <= IO_DIN[7:0]; if (VSCK & IO_A[0]) adj_v[8] <= IO_DIN[0]; if (HSCK & IO_A[0]) adj_h[8] <= IO_DIN[0]; - //paused_offsets[ve_latch] <= {adj_v, adj_h}; - //end +// paused_offsets[ve_latch] <= {adj_v, adj_h}; +// end end always @(posedge CLK_32M) begin @@ -150,7 +180,7 @@ always @(posedge CLK_32M) begin do_rom <= 0; if (do_rom) begin - sdr_addr <= {COD[13:0], RV[2:0], 1'b0}; + sdr_addr <= {COD[15:0], RV[2:0], 2'b00}; sdr_req <= ~sdr_req; end else if (sdr_req == sdr_ack) begin rom_data <= sdr_data; @@ -158,13 +188,24 @@ always @(posedge CLK_32M) begin if (CE_PIX) begin if (SH[2:0] == 2'b001) begin - { VREV, HREV1, COD } <= { ram_h_dout, ram_l_dout }; + if (m84) begin + COD <= attrib_0; + {VREV, HREV1} <= attrib_1[6:5]; + end else begin + COD <= { 2'b00, attrib_0[13:0]}; + { VREV, HREV1 } <= attrib_0[15:14]; + end do_rom <= 1; end - - if (SH[2:0] == 3'b101) row_data1 <= ram_l_dout; if (SH[2:0] == 3'b111) begin - row_data <= row_data1; + COL <= attrib_1[3:0]; + if (m84) begin + CP15 <= attrib_1[8]; + CP8 <= attrib_1[7]; + end else begin + CP15 <= attrib_1[7]; + CP8 <= attrib_1[6]; + end HREV2 <= HREV1; end end diff --git a/Arcade_MiST/IremM72 Hardware/rtl/kna70h015.sv b/Arcade_MiST/IremM72 Hardware/rtl/kna70h015.sv index e863726b..9d3dc1a4 100644 --- a/Arcade_MiST/IremM72 Hardware/rtl/kna70h015.sv +++ b/Arcade_MiST/IremM72 Hardware/rtl/kna70h015.sv @@ -23,9 +23,8 @@ module kna70h015 ( input CE_PIX, - input [15:0] D, - input A0, - input ISET, + input [1:0] iset, + input [15:0] iset_data, input NL, input S24H, @@ -88,12 +87,8 @@ V.Sync Pulse = 384us (6) */ always @(posedge CLK_32M) begin - if (ISET) begin - if (A0) - h_int_line[8] <= D[0]; - else - h_int_line[7:0] <= D[7:0]; - end + if (iset[1]) h_int_line[8] <= iset_data[8]; + if (iset[0]) h_int_line[7:0] <= iset_data[7:0]; if (CE_PIX) begin h_count <= h_count + 10'd1; diff --git a/Arcade_MiST/IremM72 Hardware/rtl/kna91h014.v b/Arcade_MiST/IremM72 Hardware/rtl/kna91h014.v index e009c9cc..fe42751e 100644 --- a/Arcade_MiST/IremM72 Hardware/rtl/kna91h014.v +++ b/Arcade_MiST/IremM72 Hardware/rtl/kna91h014.v @@ -20,6 +20,7 @@ module kna91h014 ( input CLK_32M, + input CE_PIX, input [7:0] CB, // Pins 3-10. input [7:0] CA, // Pins 11-18. @@ -35,7 +36,7 @@ module kna91h014 ( input MRD, // Pin 28. input [15:0] DIN, // Pins 25, 22-19 (split to input for Verilog). - output [15:0] DOUT, // Pins 25, 22-19 (split to output for Verilog). + output reg [15:0] DOUT, // Pins 25, 22-19 (split to output for Verilog). output DOUT_VALID, input [19:0] A, // Pins 53-60 @@ -48,16 +49,7 @@ module kna91h014 ( wire [7:0] A_IN = A[8:1]; wire [2:0] A_S = { A[11], A[10], A[0] }; -reg [7:0] color_addr; - -always @(posedge CLK_32M) begin - color_addr <= SELECT ? CA : CB; -end - -// Palette RAMs... -reg [4:0] ram_a [256]; -reg [4:0] ram_b [256]; -reg [4:0] ram_c [256]; +wire [7:0] color_addr = SELECT ? CA : CB; // RAM Addr decoding... wire ram_a_cs = A_S==3'b000 | A_S==3'b110; @@ -68,39 +60,32 @@ wire ram_c_cs = A_S==3'b100; wire wr_ena = G & MWR; wire rd_ena = G & MRD; -wire ram_wr_a = ram_a_cs & wr_ena; -wire ram_wr_b = ram_b_cs & wr_ena; -wire ram_wr_c = ram_c_cs & wr_ena; - -reg [4:0] red_lat; -reg [4:0] grn_lat; -reg [4:0] blu_lat; - -// DOUT read driver... -assign DOUT = { 11'd0, - (ram_a_cs) ? red_lat : - (ram_b_cs) ? grn_lat : - (ram_c_cs) ? blu_lat : 5'h00 }; assign DOUT_VALID = rd_ena; +// Palette RAM(s) +reg [4:0] ram[1024]; +reg [1:0] cnt; +reg [4:0] color_out; + +always @(negedge CLK_32M) +begin + cnt <= cnt + 1'd1; + if (CE_PIX) cnt <= 0; + color_out <= ram[{cnt, color_addr}]; + case(cnt) + 2'b01: RED <= color_out; + 2'b10: GRN <= color_out; + 2'b11: BLU <= color_out; + default: ; + endcase +end + +wire [9:0] ram_a = {ram_a_cs ? 2'b00 : ram_b_cs ? 2'b01 : ram_c_cs ? 2'b10 : 2'b11, A_IN}; + always @(posedge CLK_32M) begin - red_lat <= ram_a[A_IN]; - if (ram_wr_a) - ram_a[A_IN] <= DIN[4:0]; - - grn_lat <= ram_b[A_IN]; - if (ram_wr_b) - ram_b[A_IN] <= DIN[4:0]; - - blu_lat <= ram_c[A_IN]; - if (ram_wr_c) - ram_c[A_IN] <= DIN[4:0]; - - - RED <= ram_a[color_addr]; - GRN <= ram_b[color_addr]; - BLU <= ram_c[color_addr]; + DOUT <= {11'd0, ram[ram_a]}; + if (wr_ena) ram[ram_a] <= DIN[4:0]; end endmodule diff --git a/Arcade_MiST/IremM72 Hardware/rtl/m72.sv b/Arcade_MiST/IremM72 Hardware/rtl/m72.sv index 6fa6d038..85eb0fe7 100644 --- a/Arcade_MiST/IremM72 Hardware/rtl/m72.sv +++ b/Arcade_MiST/IremM72 Hardware/rtl/m72.sv @@ -58,16 +58,16 @@ module m72 ( input sdr_sprite_ack, input [31:0] sdr_bg_data_a, - output [24:1] sdr_bg_addr_a, + output [24:0] sdr_bg_addr_a, output sdr_bg_req_a, input sdr_bg_ack_a, input [31:0] sdr_bg_data_b, - output [24:1] sdr_bg_addr_b, + output [24:0] sdr_bg_addr_b, output sdr_bg_req_b, input sdr_bg_ack_b, - output [24:1] sdr_cpu_addr, + output [24:0] sdr_cpu_addr, input [15:0] sdr_cpu_dout, output [15:0] sdr_cpu_din, output reg sdr_cpu_req, @@ -82,7 +82,7 @@ module m72 ( input sdr_z80_ram_valid, output [24:0] sample_rom_addr, - input [63:0] sample_rom_data, + input [63:0] sample_rom_dout, output sample_rom_req, input sample_rom_ack, @@ -119,6 +119,8 @@ always @(posedge CLK_32M) begin end end +wire SDBEN = sound_memrq & BRQ; + reg [1:0] ce_counter_cpu; reg [1:0] ce_counter_mcu; reg ce_cpu, ce_4x_cpu, ce_mcu; @@ -165,6 +167,8 @@ wire DBEN = cpu_io_write | cpu_io_read | cpu_mem_read | cpu_mem_write; wire TNSL; +wire m84 = board_cfg.m84; + wire [15:0] cpu_mem_out; wire [19:0] cpu_mem_addr; wire [1:0] cpu_mem_sel; @@ -185,9 +189,16 @@ wire [15:0] cpu_word_out = cpu_mem_addr[0] ? { cpu_mem_out[7:0], cpu_mem_out[15: wire [19:0] cpu_word_addr = { cpu_mem_addr[19:1], 1'b0 }; wire [1:0] cpu_word_byte_sel = cpu_mem_addr[0] ? { cpu_mem_sel[0], cpu_mem_sel[1] } : cpu_mem_sel; reg [15:0] cpu_ram_rom_data; -wire [24:1] cpu_region_addr; +wire [24:0] cpu_region_addr; wire cpu_region_writable; +wire bg_a_memrq; +wire bg_b_memrq; +wire bg_palette_memrq; +wire sprite_memrq; +wire sprite_palette_memrq; +wire sound_memrq; + function [15:0] word_shuffle(input [19:0] addr, input [15:0] data); begin word_shuffle = addr[0] ? { 8'h00, data[15:8] } : data; @@ -217,7 +228,7 @@ always_ff @(posedge CLK_32M) begin if (!mem_rq_active) begin if ((ls245_en | SDBEN) && ((cpu_mem_read_w & ~cpu_mem_read_lat) || (cpu_mem_write_w & ~cpu_mem_write_lat))) begin // sdram request sdr_cpu_wr_sel <= 2'b00; - sdr_cpu_addr <= SDBEN ? {REGION_CPU2_RAM.base_addr[24:16], cpu_word_addr[15:1]} : cpu_region_addr; + sdr_cpu_addr <= SDBEN ? {REGION_SOUND.base_addr[24:16], cpu_word_addr[15:0]} : cpu_region_addr; if (cpu_mem_write & (cpu_region_writable | SDBEN)) begin sdr_cpu_wr_sel <= cpu_word_byte_sel; sdr_cpu_din <= cpu_word_out; @@ -242,13 +253,13 @@ wire COIN0 = sys_flags[0]; wire COIN1 = sys_flags[1]; wire SOFT_NL = ~sys_flags[2]; wire CBLK = sys_flags[3]; -wire BRQ = ~sys_flags[4]; +wire BRQ = ~m84 & ~sys_flags[4]; wire BANK = sys_flags[5]; wire NL = SOFT_NL ^ dip_sw[8]; // TODO BANK, CBLK, NL always @(posedge CLK_32M) begin - if (FSET & ~cpu_io_addr[0]) sys_flags <= cpu_io_out[7:0]; + if (IOWR && cpu_io_addr == 8'h02) sys_flags <= cpu_io_out[7:0]; end // mux io and memory reads @@ -263,10 +274,12 @@ always_comb begin else d16 = cpu_ram_rom_data; cpu_mem_in = word_shuffle(cpu_mem_addr, d16); - if (SW) io16 = switches; - else if (FLAG) io16 = flags; - else if (DSW) io16 = dip_sw; - else io16 = 16'hffff; + case ({cpu_io_addr[7:1], 1'b0}) + 8'h00: io16 = switches; + 8'h02: io16 = flags; + 8'h04: io16 = dip_sw; + default: io16 = 16'hffff; + endcase cpu_io_in = cpu_io_addr[0] ? io16[15:8] : io16[7:0]; end @@ -313,52 +326,37 @@ cpu v30( .sleep_savestate(paused) ); -pal_3a pal_3a( - .A(cpu_mem_addr), - .BANK(), +wire m_io = MRD | MWR; +wire sprite_dma; +wire [1:0] iset; +wire [15:0] iset_data; +wire snd_latch1_wr, snd_latch2_wr; + +address_translator address_translator( + .A(m_io ? cpu_mem_addr : {8'h00, cpu_io_addr}), + .data(m_io ? cpu_mem_out : {8'h00, cpu_io_out}), + .bytesel(m_io ? cpu_mem_sel : 2'b01), + .rd(m_io ? MRD : IORD), + .wr(m_io ? MWR : IOWR), + .M_IO(m_io), .DBEN(DBEN), - .M_IO(MRD | MWR), - .COD(), .board_cfg(board_cfg), .ls245_en(ls245_en), .sdr_addr(cpu_region_addr), .writable(cpu_region_writable), - .S() -); + .bg_a_memrq(bg_a_memrq), + .bg_b_memrq(bg_b_memrq), + .bg_palette_memrq(bg_palette_memrq), + .sprite_memrq(sprite_memrq), + .sprite_palette_memrq(sprite_palette_memrq), + .sound_memrq(sound_memrq), -wire SW, FLAG, DSW, SND, SND2, FSET, DMA_ON, ISET, INTCS; + .sprite_dma(sprite_dma), + .iset(iset), + .iset_data(iset_data), -pal_4d pal_4d( - .IOWR(IOWR), - .IORD(IORD), - .A(cpu_io_addr), - .SW(SW), - .FLAG(FLAG), - .DSW(DSW), - .SND(SND), - .SND2(SND2), - .FSET(FSET), - .DMA_ON(DMA_ON), - .ISET(ISET), - .INTCS(INTCS) -); - -wire BUFDBEN, BUFCS, OBJ_P, CHARA_P, CHARA, SOUND, SDBEN; - -pal_3d pal_3d( - .A(cpu_mem_addr), - .M_IO(MRD | MWR), - .DBEN(~DBEN), - .TNSL(1), // TODO - .BRQ(BRQ), // TODO - - .BUFDBEN(BUFDBEN), - .BUFCS(BUFCS), - .OBJ_P(OBJ_P), - .CHARA_P(CHARA_P), - .CHARA(CHARA), - .SOUND(SOUND), - .SDBEN(SDBEN) + .snd_latch1_wr(snd_latch1_wr), + .snd_latch2_wr(snd_latch2_wr) ); wire int_req, int_ack; @@ -369,7 +367,7 @@ m72_pic m72_pic( .ce(ce_cpu), .reset(~reset_n), - .cs(INTCS), + .cs((IORD | IOWR) & ~cpu_io_addr[7] & cpu_io_addr[6]), // 0x40-0x43 .wr(IOWR), .rd(0), .a0(cpu_io_addr[1]), @@ -392,9 +390,8 @@ kna70h015 kna70h015( .CLK_32M(CLK_32M), .CE_PIX(ce_pix), - .D(cpu_io_out), - .A0(cpu_io_addr[0]), - .ISET(ISET), + .iset(iset), + .iset_data(iset_data), .NL(NL), .S24H(0), @@ -441,8 +438,11 @@ board_b_d board_b_d( .MWR(MWR), .IORD(IORD), .IOWR(IOWR), - .CHARA(CHARA), - .CHARA_P(CHARA_P), + + .a_memrq(bg_a_memrq), + .b_memrq(bg_b_memrq), + .palette_memrq(bg_palette_memrq), + .NL(NL), .VE(VE), @@ -467,7 +467,9 @@ board_b_d board_b_d( .en_layer_a(en_layer_a), .en_layer_b(en_layer_b), - .en_palette(en_layer_palette) + .en_palette(en_layer_palette), + + .m84(m84) ); @@ -484,10 +486,16 @@ sound sound( .IO_A(cpu_io_addr), .IO_DIN(cpu_io_out), - .SOUND(SOUND), - .SND(SND), + .SND(snd_latch1_wr), .BRQ(BRQ), - .SND2(SND2), + .SND2(snd_latch2_wr), + + .sample_inc(z80_sample_inc), + .sample_addr(z80_sample_addr), + .sample_addr_wr(z80_sample_addr_wr), + .sample_out(z80_sample_out), + .sample_in(sample_rom_data), + .sample_ready(sample_rom_req == sample_rom_ack), .ym_audio_l(), .ym_audio_r(ym_audio), @@ -498,6 +506,8 @@ sound sound( .pause(paused), + .m84(m84), + .ram_addr(sdr_z80_ram_addr), .ram_data(sdr_z80_ram_data), .ram_dout(sdr_z80_ram_dout), @@ -514,8 +524,9 @@ wire obj_pal_dout_valid; wire [4:0] obj_pal_r, obj_pal_g, obj_pal_b; kna91h014 obj_pal( .CLK_32M(CLK_32M), + .CE_PIX(ce_pix), - .G(OBJ_P), + .G(sprite_palette_memrq), .SELECT(0), .CA(obj_pix), .CB(obj_pix), @@ -570,7 +581,7 @@ sprite sprite( .A(cpu_word_addr), .BYTE_SEL(cpu_word_byte_sel), - .BUFDBEN(BUFDBEN), + .BUFDBEN(sprite_memrq), .MRD(MRD), .MWR(MWR), @@ -580,7 +591,7 @@ sprite sprite( .pix_test(obj_pix), .TNSL(TNSL), - .DMA_ON(DMA_ON & ~sprite_freeze), + .DMA_ON(sprite_dma & ~sprite_freeze), .sdr_data(sdr_sprite_dout), .sdr_addr(sdr_sprite_addr), @@ -596,7 +607,7 @@ wire [7:0] mcu_ram_dout; wire mcu_ram_we; wire mcu_ram_int; wire mcu_ram_cs; -wire [7:0] mcu_sample_data; +wire [7:0] mcu_sample_out; dualport_mailbox_2kx16 mcu_shared_ram( .reset(~reset_n), @@ -635,12 +646,13 @@ mcu mcu( .z80_din(mculatch_data), .z80_latch_en(mculatch_en), - .sample_data(mcu_sample_data), + .sample_out(mcu_sample_out), - .sample_rom_addr(sample_rom_addr), + .sample_addr_wr(mcu_sample_addr_wr), + .sample_addr(mcu_sample_addr), + .sample_inc(mcu_sample_inc), .sample_rom_data(sample_rom_data), - .sample_rom_req(sample_rom_req), - .sample_rom_ack(sample_rom_ack), + .sample_ready(sample_rom_req == sample_rom_ack), .clk_bram(clk_bram), .bram_wr(bram_wr), @@ -652,7 +664,28 @@ mcu mcu( .dbg_rom_addr(mcu_dbg_rom_addr) ); -wire [7:0] signed_mcu_sample = mcu_sample_data - 8'h80; +wire [1:0] z80_sample_addr_wr, mcu_sample_addr_wr; +wire [7:0] z80_sample_addr, mcu_sample_addr; +wire [7:0] sample_rom_data; +wire [7:0] z80_sample_out; +wire z80_sample_inc, mcu_sample_inc; + +sample_rom sample_rom( + .clk(CLK_32M), + .reset(~reset_n), + .sample_addr_in(m84 ? z80_sample_addr : mcu_sample_addr), + .sample_addr_wr(m84 ? z80_sample_addr_wr : mcu_sample_addr_wr), + + .sample_data(sample_rom_data), + .sample_inc(m84 ? z80_sample_inc : mcu_sample_inc), + + .sample_rom_addr(sample_rom_addr), + .sample_rom_dout(sample_rom_dout), + .sample_rom_req(sample_rom_req), + .sample_rom_ack(sample_rom_ack) +); + +wire [7:0] signed_mcu_sample = ( m84 ? z80_sample_out : mcu_sample_out ) - 8'h80; reg [2:0] ce_filter_counter = 0; wire ce_filter = &ce_filter_counter; reg [15:0] filtered_mcu_sample; diff --git a/Arcade_MiST/IremM72 Hardware/rtl/m72.v b/Arcade_MiST/IremM72 Hardware/rtl/m72.v deleted file mode 100644 index d4772ad9..00000000 --- a/Arcade_MiST/IremM72 Hardware/rtl/m72.v +++ /dev/null @@ -1,813 +0,0 @@ -//============================================================================ -// Irem M72 for MiSTer FPGA - Main module -// -// Copyright (C) 2022 Martin Donlon -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -//============================================================================ - -import m72_pkg::*; - -module m72 ( - input CLK_32M, - input CLK_96M, - - input reset_n, - output reg ce_pix, - - input board_cfg_t board_cfg, - - input z80_reset_n, - - output [7:0] R, - output [7:0] G, - output [7:0] B, - - output HSync, - output VSync, - output HBlank, - output VBlank, - - output [15:0] AUDIO_L, - output [15:0] AUDIO_R, - - input [1:0] coin, - input [1:0] start_buttons, - input [3:0] p1_joystick, - input [3:0] p2_joystick, - input [3:0] p1_buttons, - input [3:0] p2_buttons, - input service_button, - input [15:0] dip_sw, - - input pause_rq, - - output [24:1] sdr_sprite_addr, - input [63:0] sdr_sprite_dout, - output sdr_sprite_req, - input sdr_sprite_rdy, - - output [24:1] sdr_bg_addr, - input [31:0] sdr_bg_dout, - output sdr_bg_req, - input sdr_bg_rdy, - - output [24:1] sdr_cpu_addr, - input [15:0] sdr_cpu_dout, - output [15:0] sdr_cpu_din, - output sdr_cpu_req, - input sdr_cpu_rdy, - output [1:0] sdr_cpu_wr_sel, - - input clk_bram, - input bram_wr, - input [7:0] bram_data, - input [19:0] bram_addr, - input [1:0] bram_cs, - - input en_layer_a, - input en_layer_b, - input en_sprites, - input en_layer_palette, - input en_sprite_palette, - input en_audio_filters, - - input sprite_freeze, - - input video_60hz, - input video_57hz, - input video_50hz, - - output ddr_debug_data_t ddr_debug_data -); - -// Divide 32Mhz clock by 4 for pixel clock -reg paused = 0; -reg [8:0] paused_v; -reg [9:0] paused_h; - -always @(posedge CLK_32M) begin - if (pause_rq & ~paused) begin - if (~ls245_en & ~DBEN & ~mem_rq_active) begin - paused <= 1; - paused_v <= V; - paused_h <= H; - end - end else if (~pause_rq & paused) begin - paused <= ~(V == paused_v && H == paused_h); - end -end - -reg [1:0] ce_counter_cpu, ce_counter_mcu; -reg ce_cpu, ce_4x_cpu, ce_mcu; - -always @(posedge CLK_32M) begin - if (!reset_n) begin - ce_cpu <= 0; - ce_4x_cpu <= 0; - ce_counter_cpu <= 0; - ce_counter_mcu <= 0; - end else begin - ce_cpu <= 0; - ce_4x_cpu <= 0; - ce_mcu <= 0; - - if (~paused) begin - if (~ls245_en && ~mem_rq_active) begin // stall main cpu while fetching from sdram - ce_counter_cpu <= ce_counter_cpu + 2'd1; - ce_4x_cpu <= 1; - ce_cpu <= &ce_counter_cpu; - end - ce_counter_mcu <= ce_counter_mcu + 2'd1; - ce_mcu <= &ce_counter_mcu; - end - end -end - -wire ce_pix_half; -jtframe_frac_cen #(2) pixel_cen -( - .clk(CLK_32M), - .n(video_57hz ? 10'd115 : video_60hz ? 10'd207 : 10'd1), - .m(video_57hz ? 10'd444 : video_60hz ? 10'd760 : 10'd4), - .cen({ce_pix_half, ce_pix}) -); - -wire clock = CLK_32M; - -/* Global signals from schematics */ -wire IOWR = cpu_io_write; // IO Write -wire IORD = cpu_io_read; // IO Read -wire MWR = cpu_mem_write; // Mem Write -wire MRD = cpu_mem_read; // Mem Read -wire DBEN = cpu_io_write | cpu_io_read | cpu_mem_read | cpu_mem_write; - -wire TNSL; - -wire [15:0] cpu_mem_out; -wire [19:0] cpu_mem_addr; -wire [1:0] cpu_mem_sel; -reg cpu_mem_read_lat, cpu_mem_write_lat; -wire cpu_mem_read_w, cpu_mem_write_w; -wire cpu_mem_read = cpu_mem_read_w | cpu_mem_read_lat; -wire cpu_mem_write = cpu_mem_write_w | cpu_mem_write_lat; - -wire cpu_io_read, cpu_io_write; -wire [7:0] cpu_io_in; -wire [7:0] cpu_io_out; -wire [7:0] cpu_io_addr; - -wire [15:0] cpu_mem_in; - - -wire [15:0] cpu_word_out = cpu_mem_addr[0] ? { cpu_mem_out[7:0], 8'h00 } : cpu_mem_out; -wire [19:0] cpu_word_addr = { cpu_mem_addr[19:1], 1'b0 }; -wire [1:0] cpu_word_byte_sel = cpu_mem_addr[0] ? { cpu_mem_sel[0], 1'b0 } : cpu_mem_sel; -reg [15:0] cpu_ram_rom_data; -wire [24:1] cpu_region_addr; -wire cpu_region_writable; - -function [15:0] word_shuffle(input [19:0] addr, input [15:0] data); - begin - word_shuffle = addr[0] ? { 8'h00, data[15:8] } : data; - end -endfunction - -reg mem_rq_active = 0; -reg b_d_dout_valid_lat, obj_pal_dout_valid_lat, sound_dout_valid_lat, sprite_dout_valid_lat; - -always @(posedge CLK_32M or negedge reset_n) -begin - if (!reset_n) begin - b_d_dout_valid_lat <= 0; - obj_pal_dout_valid_lat <= 0; - sound_dout_valid_lat <= 0; - sprite_dout_valid_lat <= 0; - end else begin - cpu_mem_read_lat <= cpu_mem_read_w; - cpu_mem_write_lat <= cpu_mem_write_w; - - b_d_dout_valid_lat <= b_d_dout_valid; - obj_pal_dout_valid_lat <= obj_pal_dout_valid; - sound_dout_valid_lat <= sound_dout_valid; - sprite_dout_valid_lat <= sprite_dout_valid; - end -end - -reg sdr_cpu_rq, sdr_cpu_ack, sdr_cpu_rq2; - -always_ff @(posedge CLK_96M) begin - sdr_cpu_req <= 0; - if (sdr_cpu_rdy) sdr_cpu_ack <= sdr_cpu_rq; - if (sdr_cpu_rq != sdr_cpu_rq2) begin - sdr_cpu_req <= 1; - sdr_cpu_rq2 <= sdr_cpu_rq; - end -end - - -always_ff @(posedge CLK_32M or negedge reset_n) begin - if (!reset_n) begin - mem_rq_active <= 0; - end else begin - if (!mem_rq_active) begin - if (ls245_en && ((cpu_mem_read_w & ~cpu_mem_read_lat) || (cpu_mem_write_w & ~cpu_mem_write_lat))) begin // sdram request - sdr_cpu_wr_sel <= 2'b00; - sdr_cpu_addr <= cpu_region_addr; - if (cpu_mem_write & cpu_region_writable ) begin - sdr_cpu_wr_sel <= cpu_word_byte_sel; - sdr_cpu_din <= cpu_word_out; - end - sdr_cpu_rq <= ~sdr_cpu_rq; - mem_rq_active <= 1; - end - end else if (sdr_cpu_rq == sdr_cpu_ack) begin - cpu_ram_rom_data <= sdr_cpu_dout; - mem_rq_active <= 0; - end - end -end - -wire ls245_en, rom0_ce, rom1_ce, ram_cs2; - - -wire [15:0] switches = { p2_buttons, p2_joystick, p1_buttons, p1_joystick }; -wire [15:0] flags = { 8'hff, TNSL, 1'b1, 1'b1 /*TEST*/, 1'b1 /*R*/, coin, start_buttons }; - -reg [7:0] sys_flags = 0; -wire COIN0 = sys_flags[0]; -wire COIN1 = sys_flags[1]; -wire SOFT_NL = ~sys_flags[2]; -wire CBLK = sys_flags[3]; -wire BRQ = ~sys_flags[4]; -wire BANK = sys_flags[5]; -wire NL = SOFT_NL ^ dip_sw[8]; - -// TODO BANK, CBLK, NL -always @(posedge CLK_32M) begin - if (FSET & ~cpu_io_addr[0]) sys_flags <= cpu_io_out[7:0]; -end - -// mux io and memory reads -always_comb begin - bit [15:0] d16; - bit [15:0] io16; - - if (b_d_dout_valid_lat) d16 = b_d_dout; - else if (obj_pal_dout_valid_lat) d16 = obj_pal_dout; - else if (sound_dout_valid_lat) d16 = sound_dout; - else if (sprite_dout_valid_lat) d16 = sprite_dout; - else if (cpu_mem_addr[19:16] == 4'hb) d16 = cpu_shared_ram_dout; - else d16 = cpu_ram_rom_data; - cpu_mem_in = word_shuffle(cpu_mem_addr, d16); - - if (SW) io16 = switches; - else if (FLAG) io16 = flags; - else if (DSW) io16 = dip_sw; - else io16 = 16'hffff; - - cpu_io_in = cpu_io_addr[0] ? io16[15:8] : io16[7:0]; -end - -cpu v30( - .clk(CLK_32M), - .ce(ce_cpu), // TODO - .ce_4x(ce_4x_cpu), // TODO - .reset(~reset_n), - .turbo(0), - .SLOWTIMING(0), - - .cpu_idle(), - .cpu_halt(), - .cpu_irqrequest(), - .cpu_prefix(), - - .dma_active(0), - .sdma_request(0), - .canSpeedup(), - - .bus_read(cpu_mem_read_w), - .bus_write(cpu_mem_write_w), - .bus_be(cpu_mem_sel), - .bus_addr(cpu_mem_addr), - .bus_datawrite(cpu_mem_out), - .bus_dataread(cpu_mem_in), - - .irqrequest_in(int_req), - .irqvector_in(int_vector), - .irqrequest_ack(int_ack), - - .load_savestate(0), - - // TODO - .cpu_done(), - .cpu_export_opcode(cpu_export_opcode), - .cpu_export_reg_cs(cpu_export_reg_cs), - .cpu_export_reg_ip(cpu_export_reg_ip), - - .RegBus_Din(cpu_io_out), - .RegBus_Adr(cpu_io_addr), - .RegBus_wren(cpu_io_write), - .RegBus_rden(cpu_io_read), - .RegBus_Dout(cpu_io_in), - - .sleep_savestate(paused) -); - -wire [15:0] cpu_export_reg_cs; -wire [15:0] cpu_export_reg_ip; -wire [7:0] cpu_export_opcode; - -assign ddr_debug_data.cpu_cs = cpu_export_reg_cs; -assign ddr_debug_data.cpu_ip = cpu_export_reg_ip; -assign ddr_debug_data.cpu_opcode = cpu_export_opcode; - -pal_3a pal_3a( - .A(cpu_mem_addr), - .BANK(), - .DBEN(DBEN), - .M_IO(MRD | MWR), - .COD(), - .board_cfg(board_cfg), - .ls245_en(ls245_en), - .sdr_addr(cpu_region_addr), - .writable(cpu_region_writable), - .S() -); - -wire SW, FLAG, DSW, SND, SND2, FSET, DMA_ON, ISET, INTCS; - -pal_4d pal_4d( - .IOWR(IOWR), - .IORD(IORD), - .A(cpu_io_addr), - .SW(SW), - .FLAG(FLAG), - .DSW(DSW), - .SND(SND), - .SND2(SND2), - .FSET(FSET), - .DMA_ON(DMA_ON), - .ISET(ISET), - .INTCS(INTCS) -); - -wire BUFDBEN, BUFCS, OBJ_P, CHARA_P, CHARA, SOUND, SDBEN; - -pal_3d pal_3d( - .A(cpu_mem_addr), - .M_IO(MRD | MWR), - .DBEN(~DBEN), - .TNSL(1), // TODO - .BRQ(BRQ), // TODO - - .BUFDBEN(BUFDBEN), - .BUFCS(BUFCS), - .OBJ_P(OBJ_P), - .CHARA_P(CHARA_P), - .CHARA(CHARA), - .SOUND(SOUND), - .SDBEN(SDBEN) -); - -wire int_req, int_ack; -wire [8:0] int_vector; - -m72_pic m72_pic( - .clk(CLK_32M), - .ce(ce_cpu), - .reset(~reset_n), - - .cs(INTCS), - .wr(IOWR), - .rd(0), - .a0(cpu_io_addr[1]), - - .din(cpu_io_out), - - .int_req(int_req), - .int_vector(int_vector), - .int_ack(int_ack), - - .intp({5'd0, HINT, 1'b0, VBLK}) -); - -wire [8:0] VE, V; -wire [9:0] HE, H; -wire HBLK, VBLK, HS, VS; -wire HINT; - -assign HSync = HS; -assign HBlank = HBLK; -assign VSync = VS; -assign VBlank = VBLK; - -kna70h015 kna70h015( - .CLK_32M(CLK_32M), - - .CE_PIX(ce_pix), - .D(cpu_io_out), - .A0(cpu_io_addr[0]), - .ISET(ISET), - .NL(NL), - .S24H(0), - - .CLD(), - .CPBLK(), - - .VE(VE), - .V(V), - .HE(HE), - .H(H), - - .HBLK(HBLK), - .VBLK(VBLK), - .HINT(HINT), - - .HS(HS), - .VS(VS), - - .video_50hz(video_50hz) -); - -wire [15:0] b_d_dout; -wire b_d_dout_valid; - -wire [4:0] char_r, char_g, char_b; -wire P1L; - -board_b_d board_b_d( - .CLK_32M(CLK_32M), - .CLK_96M(CLK_96M), - - .CE_PIX(ce_pix), - - .DOUT(b_d_dout), - .DOUT_VALID(b_d_dout_valid), - - .DIN(cpu_word_out), - .A(cpu_word_addr), - .BYTE_SEL(cpu_word_byte_sel), - - .IO_DIN(cpu_io_out), - .IO_A(cpu_io_addr), - - .MRD(MRD), - .MWR(MWR), - .IORD(IORD), - .IOWR(IOWR), - .CHARA(CHARA), - .CHARA_P(CHARA_P), - .NL(NL), - - .VE(VE), - .HE({HE[9], HE[7:0]}), - - - .RED(char_r), - .GREEN(char_g), - .BLUE(char_b), - .P1L(P1L), - - .sdr_data(sdr_bg_dout), - .sdr_addr(sdr_bg_addr), - .sdr_req(sdr_bg_req), - .sdr_rdy(sdr_bg_rdy), - - .paused(paused), - - .en_layer_a(en_layer_a), - .en_layer_b(en_layer_b), - .en_palette(en_layer_palette) -); - - -wire [15:0] sound_dout; -wire sound_dout_valid; - -wire [7:0] snd_io_addr; -wire [7:0] snd_io_data; -wire snd_io_req; - -wire [15:0] ym_audio; - -sound sound( - .CLK_32M(CLK_32M), - .DIN(cpu_mem_out), - .DOUT(sound_dout), - .DOUT_VALID(sound_dout_valid), - - .A(cpu_mem_addr), - .BYTE_SEL(cpu_mem_sel), - - .IO_A(cpu_io_addr), - .IO_DIN(cpu_io_out), - - .SDBEN(SDBEN), - .SOUND(SOUND), - .SND(SND), - .BRQ(BRQ), - .MRD(MRD), - .MWR(MWR), - .SND2(SND2), - - .ym_audio_l(), - .ym_audio_r(ym_audio), - - .snd_io_addr(snd_io_addr), - .snd_io_data(snd_io_data), - .snd_io_req(snd_io_req), - - .pause(paused) -); - -// Temp A-C board palette -wire [15:0] obj_pal_dout; -wire obj_pal_dout_valid; - - -wire [4:0] obj_pal_r, obj_pal_g, obj_pal_b; -kna91h014 obj_pal( - .CLK_32M(CLK_32M), - - .G(OBJ_P), - .SELECT(0), - .CA(obj_pix), - .CB(obj_pix), - - .E1_N(), // TODO - .E2_N(), // TODO - - .MWR(MWR & cpu_word_byte_sel[0]), - .MRD(MRD), - - .DIN(cpu_word_out), - .DOUT(obj_pal_dout), - .DOUT_VALID(obj_pal_dout_valid), - .A(cpu_word_addr), - - .RED(obj_pal_r), - .GRN(obj_pal_g), - .BLU(obj_pal_b) -); - -wire [4:0] obj_r = en_sprite_palette ? obj_pal_r : { obj_pix[3:0], 1'b0 }; -wire [4:0] obj_g = en_sprite_palette ? obj_pal_g : { obj_pix[3:0], 1'b0 }; -wire [4:0] obj_b = en_sprite_palette ? obj_pal_b : { obj_pix[3:0], 1'b0 }; - -wire P0L = (|obj_pix[3:0]) && en_sprites; - -assign R = ~CBLK ? ( (P0L & P1L) ? {obj_r[4:0], obj_r[4:2]} : {char_r[4:0], char_r[4:2]} ) : 8'h00; -assign G = ~CBLK ? ( (P0L & P1L) ? {obj_g[4:0], obj_g[4:2]} : {char_g[4:0], char_g[4:2]} ) : 8'h00; -assign B = ~CBLK ? ( (P0L & P1L) ? {obj_b[4:0], obj_b[4:2]} : {char_b[4:0], char_b[4:2]} ) : 8'h00; - -wire [15:0] sprite_dout; -wire sprite_dout_valid; - -wire [7:0] obj_pix; - -sprite sprite( - .CLK_32M(CLK_32M), - .CLK_96M(CLK_96M), - .CE_PIX(ce_pix), - - .DIN(cpu_word_out), - .DOUT(sprite_dout), - .DOUT_VALID(sprite_dout_valid), - - .A(cpu_word_addr), - .BYTE_SEL(cpu_word_byte_sel), - - .BUFDBEN(BUFDBEN), - .MRD(MRD), - .MWR(MWR), - - .VE(VE), - .NL(NL), - .HBLK(HBLK), - .pix_test(obj_pix), - - .TNSL(TNSL), - .DMA_ON(DMA_ON & ~sprite_freeze), - - .sdr_data(sdr_sprite_dout), - .sdr_addr(sdr_sprite_addr), - .sdr_req(sdr_sprite_req), - .sdr_rdy(sdr_sprite_rdy) -); - - -wire [15:0] cpu_shared_ram_dout; -wire [11:0] mcu_ram_addr; -wire [7:0] mcu_ram_din; -wire [7:0] mcu_ram_dout; -wire mcu_ram_we; -wire mcu_ram_int; -wire mcu_ram_cs; -wire [7:0] mcu_sample_data; - -dualport_mailbox_2kx16 mcu_shared_ram( - .reset(~reset_n), - .clk_l(CLK_32M), - .addr_l(cpu_word_addr[11:1]), - .cs_l(1'b1), - .din_l(cpu_word_out), - .dout_l(cpu_shared_ram_dout), - .we_l((cpu_word_addr[19:16] == 4'hb && MWR) ? cpu_word_byte_sel : 2'b00), - .int_l(), - - .clk_r(CLK_32M), - .cs_r(mcu_ram_cs), - .addr_r(mcu_ram_addr[11:0]), - .din_r(mcu_ram_dout), - .dout_r(mcu_ram_din), - .we_r(mcu_ram_we), - .int_r(mcu_ram_int) -); - -wire [7:0] mculatch_data = board_cfg.main_mculatch ? cpu_io_out : snd_io_data; -wire mculatch_en = board_cfg.main_mculatch ? ( IOWR && cpu_io_addr == 8'hc0 ) : ( snd_io_req && snd_io_addr == 8'h82 ); - -mcu mcu( - .CLK_32M(CLK_32M), - .ce_8m(ce_mcu), - .reset(~reset_n), - - .ext_ram_addr(mcu_ram_addr), - .ext_ram_din(mcu_ram_din), - .ext_ram_dout(mcu_ram_dout), - .ext_ram_cs(mcu_ram_cs), - .ext_ram_we(mcu_ram_we), - .ext_ram_int(mcu_ram_int), - - .z80_din(mculatch_data), - .z80_latch_en(mculatch_en), - - .sample_data(mcu_sample_data), - - .clk_bram(clk_bram), - .bram_wr(bram_wr), - .bram_data(bram_data), - .bram_addr(bram_addr), - .bram_prom_cs(bram_cs[0]), - .bram_samples_cs(bram_cs[1]), - - .dbg_rom_addr(mcu_dbg_rom_addr) -); - -wire [7:0] signed_mcu_sample = mcu_sample_data - 8'h80; -reg [2:0] ce_filter_counter = 0; -wire ce_filter = &ce_filter_counter; -reg [15:0] filtered_mcu_sample; -reg [15:0] filtered_ym_audio; - -// 3.5Khz 2nd order low pass filter with additional 10dB attenuation -IIR_filter #( .use_params(1), .stereo(0), .coeff_x(0.00004185087102461337 * 0.31622776601), .coeff_x0(2), .coeff_x1(1), .coeff_x2(0), .coeff_y0(-1.99222499379830120247), .coeff_y1(0.99225510233860669818), .coeff_y2(0)) samples_lpf ( - .clk(CLK_32M), - .reset(~reset_n), - - .ce(ce_filter), - .sample_ce(1), - - .cx(), - .cx0(), - .cx1(), - .cx2(), - .cy0(), - .cy1(), - .cy2(), - - .input_l({signed_mcu_sample[7:0], 8'd0}), - .input_r(), - .output_l(filtered_mcu_sample), - .output_r() -); - - -// 9khz 1st order, 10khz 2nd order -IIR_filter #( .use_params(1), .stereo(0), .coeff_x(0.00000476166826258131), .coeff_x0(3), .coeff_x1(3), .coeff_x2(1), .coeff_y0(-2.96374831301152275032), .coeff_y1(2.92805248787211569450), .coeff_y2(-0.96430074919997255112)) music_lpf ( - .clk(CLK_32M), - .reset(~reset_n), - - .ce(ce_filter), - .sample_ce(1), - - .cx(), - .cx0(), - .cx1(), - .cx2(), - .cy0(), - .cy1(), - .cy2(), - - .input_l(ym_audio), - .input_r(), - .output_l(filtered_ym_audio), - .output_r() -); - -reg [16:0] audio_out; - -assign AUDIO_L = audio_out[16:1]; -assign AUDIO_R = audio_out[16:1]; - -always @(posedge CLK_32M) begin - ce_filter_counter <= ce_filter_counter + 3'd1; - - if (en_audio_filters) - audio_out <= {filtered_ym_audio[15], filtered_ym_audio[15:0]} + {filtered_mcu_sample[15], filtered_mcu_sample[15:0]}; - else - audio_out <= {ym_audio[15], ym_audio[15:0]} + {{signed_mcu_sample[7:0], 9'd0}}; -end - - - - - - - - - - - - - - - - - -reg [11:0] dbg_cpu_ext_addr; -reg [15:0] dbg_cpu_ext_data; -reg [1:0] dbg_cpu_ext_we; - -assign ddr_debug_data.cpu_ext_addr = dbg_cpu_ext_addr; -assign ddr_debug_data.cpu_ext_data = dbg_cpu_ext_data; -assign ddr_debug_data.cpu_ext_we = dbg_cpu_ext_we; - -// CPU debug -always @(posedge CLK_32M) begin - reg cs; - reg [11:0] addr; - reg [15:0] data; - reg [1:0] we; - - cs <= (cpu_word_addr[19:16] == 4'hb) && ( MWR || MRD ); - addr <= cpu_word_addr[11:0]; - data <= cpu_word_out; - we <= MWR ? cpu_word_byte_sel : 2'b00; - - if (cs & ~((cpu_word_addr[19:16] == 4'hb) && ( MWR || MRD ))) begin - dbg_cpu_ext_addr <= addr; - dbg_cpu_ext_we <= we; - if (we != 2'b00) dbg_cpu_ext_data <= data; - else dbg_cpu_ext_data <= cpu_shared_ram_dout; - end -end - -reg [11:0] dbg_mcu_ext_addr; -reg [7:0] dbg_mcu_ext_data; -reg dbg_mcu_ext_we; - -assign ddr_debug_data.mcu_ext_addr = dbg_mcu_ext_addr; -assign ddr_debug_data.mcu_ext_data = dbg_mcu_ext_data; -assign ddr_debug_data.mcu_ext_we = dbg_mcu_ext_we; - -// MCU debug -always @(posedge CLK_32M) begin - reg cs; - reg [11:0] addr; - reg [7:0] data; - reg we; - - cs <= mcu_ram_cs; - addr <= mcu_ram_addr; - data <= mcu_ram_dout; - we <= mcu_ram_we; - - if (cs & ~mcu_ram_cs) begin - dbg_mcu_ext_addr <= addr; - dbg_mcu_ext_we <= we; - if (we) dbg_mcu_ext_data <= data; - else dbg_mcu_ext_data <= mcu_ram_din; - end -end - - -wire [15:0] mcu_dbg_rom_addr; -reg [15:0] latched_mcu_dbg_rom_addr; -assign ddr_debug_data.mcu_rom_addr = latched_mcu_dbg_rom_addr; -always @(posedge CLK_32M) if (ce_cpu) latched_mcu_dbg_rom_addr <= mcu_dbg_rom_addr; - -endmodule diff --git a/Arcade_MiST/IremM72 Hardware/rtl/m72_pkg.sv b/Arcade_MiST/IremM72 Hardware/rtl/m72_pkg.sv index 84713388..7064db13 100644 --- a/Arcade_MiST/IremM72 Hardware/rtl/m72_pkg.sv +++ b/Arcade_MiST/IremM72 Hardware/rtl/m72_pkg.sv @@ -23,30 +23,36 @@ package m72_pkg; typedef struct packed { bit [24:0] base_addr; bit reorder_64; - bit [1:0] bram_cs; + bit [3:0] bram_cs; } region_t; - parameter region_t REGION_CPU_ROM = '{ 25'h000000, 0, 2'b00 }; - parameter region_t REGION_SPRITE = '{ 25'h100000, 1, 2'b00 }; - parameter region_t REGION_BG_A = '{ 25'h200000, 0, 2'b00 }; - parameter region_t REGION_BG_B = '{ 25'h300000, 0, 2'b00 }; - parameter region_t REGION_MCU = '{ 25'h000000, 0, 2'b01 }; - parameter region_t REGION_SAMPLES = '{ 25'h600000, 0, 2'b00 }; + parameter region_t REGION_CPU_ROM = '{ 25'h000000, 0, 4'b0000 }; + parameter region_t REGION_SPRITE = '{ 25'h100000, 1, 4'b0000 }; + parameter region_t REGION_BG_A = '{ 25'h200000, 0, 4'b0000 }; + parameter region_t REGION_BG_B = '{ 25'h400000, 0, 4'b0000 }; + parameter region_t REGION_MCU = '{ 25'h000000, 0, 4'b0001 }; + parameter region_t REGION_SAMPLES = '{ 25'h600000, 0, 4'b0000 }; + parameter region_t REGION_OFFSETS = '{ 25'h000000, 0, 4'b0100 }; + parameter region_t REGION_PROTECT = '{ 25'h000000, 0, 4'b1000 }; + parameter region_t REGION_SOUND = '{ 25'h500000, 0, 4'b0000 }; - parameter region_t LOAD_REGIONS[6] = '{ + parameter region_t LOAD_REGIONS[9] = '{ REGION_CPU_ROM, REGION_SPRITE, REGION_BG_A, REGION_BG_B, REGION_MCU, - REGION_SAMPLES + REGION_SAMPLES, + REGION_OFFSETS, + REGION_PROTECT, + REGION_SOUND }; parameter region_t REGION_CPU_RAM = '{ 25'h400000, 0, 2'b00 }; - parameter region_t REGION_CPU2_RAM = '{ 25'h500000, 0, 2'b00 }; typedef struct packed { - bit [3:0] reserved; + bit [2:0] reserved; + bit m84; bit main_mculatch; bit [2:0] memory_map; } board_cfg_t; diff --git a/Arcade_MiST/IremM72 Hardware/rtl/mcu.sv b/Arcade_MiST/IremM72 Hardware/rtl/mcu.sv index c314de0e..7b4be1ed 100644 --- a/Arcade_MiST/IremM72 Hardware/rtl/mcu.sv +++ b/Arcade_MiST/IremM72 Hardware/rtl/mcu.sv @@ -36,12 +36,13 @@ module mcu( input z80_latch_en, // sample output, 8-bit unsigned - output reg [7:0] sample_data, + output reg [7:0] sample_out, - output reg [24:0] sample_rom_addr, - input [63:0] sample_rom_data, - output reg sample_rom_req = 0, - input sample_rom_ack, + output reg [1:0] sample_addr_wr, + output reg [7:0] sample_addr, + output reg sample_inc, + input [7:0] sample_rom_data, + input sample_ready, // ioctl input clk_bram, @@ -61,13 +62,13 @@ reg ram_we, ram_cs; wire [7:0] sample_port; reg [3:0] delayed_ce_count = 0; -wire delayed_ce = ce_8m & ~|delayed_ce_count & sample_rom_req == sample_rom_ack; +wire delayed_ce = ce_8m & ~|delayed_ce_count & sample_ready; always @(posedge CLK_32M) begin if (reset) - sample_data <= 8'h80; + sample_out <= 8'h80; else - sample_data <= sample_port; + sample_out <= sample_port; end dpramv #(.widthad_a(7)) internal_ram @@ -100,24 +101,18 @@ dpramv #(.widthad_a(13)) prom .q_b() ); -wire [7:0] sample_data_dout; -reg [7:0] sample_data_latch; -reg [17:0] sample_addr; - reg [7:0] z80_latch; reg z80_latch_int = 0; -reg [7:0] ext_dout; -reg [15:0] ext_addr; -reg ext_cs, ext_we; +wire [7:0] ext_dout; +wire [15:0] ext_addr; +wire ext_cs, ext_we; enum { SAMPLE, Z80, RAM } ext_src = SAMPLE; -always @(posedge CLK_32M) begin +assign sample_addr = ext_dout; - if (reset) begin - sample_rom_addr[17:0] <= 18'h3FFFF; - end +always @(posedge CLK_32M) begin if (z80_latch_en) begin z80_latch <= z80_din; @@ -128,6 +123,8 @@ always @(posedge CLK_32M) begin ext_ram_cs <= 0; ext_ram_we <= 0; + sample_inc <= 0; + sample_addr_wr <= 0; if (delayed_ce) begin dbg_rom_addr <= prom_addr; @@ -135,17 +132,14 @@ always @(posedge CLK_32M) begin if (ext_cs) begin casex (ext_addr) 16'h0000: if (ext_we) begin - sample_addr[12:0] <= { ext_dout, 5'd0 }; + sample_addr_wr <= 2'b01; end else begin ext_src <= SAMPLE; - sample_addr <= sample_addr + 18'd1; - sample_rom_addr <= {REGION_SAMPLES.base_addr[24:18], sample_addr[17:0]}; - if(sample_addr[17:3] != sample_rom_addr[17:3]) - sample_rom_req <= ~sample_rom_req; + sample_inc <= 1; end 16'h0001: if (ext_we) begin - sample_addr[17:13] <= ext_dout[4:0]; + sample_addr_wr <= 2'b10; end 16'h0002: if (ext_we) begin @@ -167,20 +161,7 @@ always @(posedge CLK_32M) begin end end -always @(*) begin - case(sample_rom_addr[2:0]) - 3'd0: sample_data_dout = sample_rom_data[ 7: 0]; - 3'd1: sample_data_dout = sample_rom_data[15: 8]; - 3'd2: sample_data_dout = sample_rom_data[23:16]; - 3'd3: sample_data_dout = sample_rom_data[31:24]; - 3'd4: sample_data_dout = sample_rom_data[39:32]; - 3'd5: sample_data_dout = sample_rom_data[47:40]; - 3'd6: sample_data_dout = sample_rom_data[55:48]; - default: sample_data_dout = sample_rom_data[63:56]; - endcase; -end - -wire [7:0] ext_din = ext_src == SAMPLE ? sample_data_dout : ext_src == Z80 ? z80_latch : ext_ram_din; +wire [7:0] ext_din = ext_src == SAMPLE ? sample_rom_data : ext_src == Z80 ? z80_latch : ext_ram_din; reg [12:0] prom_addr; wire [12:0] pre_prom_addr; @@ -190,17 +171,7 @@ wire [6:0] pre_ram_addr; wire [7:0] pre_ram_dout; wire pre_ram_we, pre_ram_cs; -wire [7:0] pre_ext_dout; -wire [15:0] pre_ext_addr; -wire pre_ext_cs; -wire pre_ext_we; - always @(posedge CLK_32M) begin - ext_dout <= pre_ext_dout; - ext_addr <= pre_ext_addr; - ext_cs <= pre_ext_cs; - ext_we <= pre_ext_we; - if (delayed_ce) begin ram_dout <= pre_ram_dout; ram_addr <= pre_ram_addr; @@ -236,10 +207,10 @@ mc8051_core mc8051( // external ram .datax_i(ext_din), - .datax_o(pre_ext_dout), - .adrx_o(pre_ext_addr), - .memx_o(pre_ext_cs), - .wrx_o(pre_ext_we) + .datax_o(ext_dout), + .adrx_o(ext_addr), + .memx_o(ext_cs), + .wrx_o(ext_we) ); endmodule \ No newline at end of file diff --git a/Arcade_MiST/IremM72 Hardware/rtl/pal.sv b/Arcade_MiST/IremM72 Hardware/rtl/pal.sv index c2421f91..1bc1304e 100644 --- a/Arcade_MiST/IremM72 Hardware/rtl/pal.sv +++ b/Arcade_MiST/IremM72 Hardware/rtl/pal.sv @@ -22,125 +22,178 @@ import m72_pkg::*; -module pal_3a +module address_translator ( input logic [19:0] A, + input logic [15:0] data, + input logic [1:0] bytesel, + + input logic rd, + input logic wr, input board_cfg_t board_cfg, - input logic BANK, input logic DBEN, input logic M_IO, - input logic [12:0] COD, output logic ls245_en, // TODO this signal might be better named - output [24:1] sdr_addr, + output [24:0] sdr_addr, output writable, - output logic S + + output bg_a_memrq, // CHARA + output bg_b_memrq, // CHARA + output bg_palette_memrq, // CHARA_P + + output sprite_memrq, // + output sprite_palette_memrq, // OBJ_P + output sound_memrq, + + output sprite_dma, + output [1:0] iset, + output [15:0] iset_data, + + output snd_latch1_wr, + output snd_latch2_wr ); + assign snd_latch1_wr = ~M_IO & wr & ( A[7:0] == 8'h00 ); + assign snd_latch2_wr = (board_cfg.m84) ? 1'b0 : ( ~M_IO & wr & ( A[7:0] == 8'hc0)); + always_comb begin case (board_cfg.memory_map) 0: begin casex (A[19:16]) - 4'b010x: begin ls245_en = DBEN & M_IO; writable = 1; sdr_addr = REGION_CPU_RAM.base_addr[24:1] | A[16:1]; end - 4'b00xx: begin ls245_en = DBEN & M_IO; writable = 0; sdr_addr = REGION_CPU_ROM.base_addr[24:1] | A[17:1]; end - 4'b1111: begin ls245_en = DBEN & M_IO; writable = 0; sdr_addr = REGION_CPU_ROM.base_addr[24:1] | A[17:1]; end + 4'b010x: begin ls245_en = DBEN & M_IO; writable = 1; sdr_addr = REGION_CPU_RAM.base_addr[24:0] | A[16:0]; end + 4'b00xx: begin ls245_en = DBEN & M_IO; writable = 0; sdr_addr = REGION_CPU_ROM.base_addr[24:0] | A[17:0]; end + 4'b1111: begin ls245_en = DBEN & M_IO; writable = 0; sdr_addr = REGION_CPU_ROM.base_addr[24:0] | A[17:0]; end default: begin ls245_en = 0; writable = 0; sdr_addr = 24'd0; end endcase end 1: begin casex (A[19:16]) - 4'b1010: begin ls245_en = DBEN & M_IO; writable = 1; sdr_addr = REGION_CPU_RAM.base_addr[24:1] | A[16:1]; end - 4'b0xxx: begin ls245_en = DBEN & M_IO; writable = 0; sdr_addr = REGION_CPU_ROM.base_addr[24:1] | A[18:1]; end - 4'b1111: begin ls245_en = DBEN & M_IO; writable = 0; sdr_addr = REGION_CPU_ROM.base_addr[24:1] | A[18:1]; end + 4'b1010: begin ls245_en = DBEN & M_IO; writable = 1; sdr_addr = REGION_CPU_RAM.base_addr[24:0] | A[16:0]; end + 4'b0xxx: begin ls245_en = DBEN & M_IO; writable = 0; sdr_addr = REGION_CPU_ROM.base_addr[24:0] | A[18:0]; end + 4'b1111: begin ls245_en = DBEN & M_IO; writable = 0; sdr_addr = REGION_CPU_ROM.base_addr[24:0] | A[18:0]; end default: begin ls245_en = 0; writable = 0; sdr_addr = 24'd0; end endcase end 2: begin casex (A[19:16]) - 4'b100x: begin ls245_en = DBEN & M_IO; writable = 1; sdr_addr = REGION_CPU_RAM.base_addr[24:1] | A[16:1]; end - 4'b0xxx: begin ls245_en = DBEN & M_IO; writable = 0; sdr_addr = REGION_CPU_ROM.base_addr[24:1] | A[18:1]; end - 4'b1111: begin ls245_en = DBEN & M_IO; writable = 0; sdr_addr = REGION_CPU_ROM.base_addr[24:1] | A[18:1]; end + 4'b100x: begin ls245_en = DBEN & M_IO; writable = 1; sdr_addr = REGION_CPU_RAM.base_addr[24:0] | A[16:0]; end + 4'b0xxx: begin ls245_en = DBEN & M_IO; writable = 0; sdr_addr = REGION_CPU_ROM.base_addr[24:0] | A[18:0]; end + 4'b1111: begin ls245_en = DBEN & M_IO; writable = 0; sdr_addr = REGION_CPU_ROM.base_addr[24:0] | A[18:0]; end default: begin ls245_en = 0; writable = 0; sdr_addr = 24'd0; end endcase end - - default: begin - ls245_en = 0; - writable = 0; - sdr_addr = 0; - end - + + 3,4: begin + casex (A[19:16]) + 4'b1110: begin ls245_en = DBEN & M_IO; writable = 1; sdr_addr = REGION_CPU_RAM.base_addr[24:0] | A[16:0]; end + 4'b0xxx: begin ls245_en = DBEN & M_IO; writable = 0; sdr_addr = REGION_CPU_ROM.base_addr[24:0] | A[18:0]; end + 4'b1111: begin ls245_en = DBEN & M_IO; writable = 0; sdr_addr = REGION_CPU_ROM.base_addr[24:0] | A[18:0]; end + default: begin ls245_en = 0; writable = 0; sdr_addr = 24'd0; end + endcase + end + + default: begin + ls245_en = 0; + writable = 0; + sdr_addr = 0; + end + endcase - - S = COD[11]; end -endmodule - -module pal_4d -( - input logic IOWR, - input logic IORD, - input logic [7:0] A, - - output logic SW, - output logic FLAG, - output logic DSW, - output logic SND, - output logic SND2, - output logic FSET, - output logic DMA_ON, - output logic ISET, - output logic INTCS -); - always_comb begin - SW = IORD & !A[7] & !A[6] & !A[3] & !A[2] & !A[1]; - FLAG = IORD & !A[7] & !A[6] & !A[3] & !A[2] & A[1]; - DSW = IORD & !A[7] & !A[6] & !A[3] & A[2] & !A[1]; - SND = IOWR & !A[7] & !A[6] & !A[3] & !A[2] & !A[1]; - SND2 = IOWR & A[7] & A[6] & !A[3] & !A[2] & !A[1]; - FSET = IOWR & !A[7] & !A[6] & !A[3] & !A[2] & A[1]; - DMA_ON = IOWR & !A[7] & !A[6] & !A[3] & A[2] & !A[1]; - ISET = IOWR & !A[7] & !A[6] & !A[3] & A[2] & A[1]; - INTCS = (IOWR | IORD) & !A[7] & A[6]; + bg_a_memrq = 0; + bg_b_memrq = 0; + bg_palette_memrq = 0; + sprite_memrq = 0; + sprite_palette_memrq = 0; + sound_memrq = 0; + + case (board_cfg.memory_map) + // M84 rtype2 + 3: begin + casex (A[19:12]) + // 0xc0xxx + 8'b1100_0000: sprite_memrq = 1; + // 0xc8xxx + 8'b1100_1000: sprite_palette_memrq = 1; + // 0xd8xxx + 8'b1101_1000: bg_palette_memrq = 1; + // 0xd0000 - 0xd3fff + 8'b1101_00xx: bg_a_memrq = 1; + // 0xd4000 - 0xd7fff + 8'b1101_01xx: bg_b_memrq = 1; + default: begin end// nothing + endcase + end + // M84 Hammerin' Harry + 4: begin + casex (A[19:12]) + // 0xc0xxx + 8'b1100_0000: sprite_memrq = 1; + // 0xa0xxx + 8'b1010_0000: sprite_palette_memrq = 1; + // 0xa8xxx + 8'b1010_1000: bg_palette_memrq = 1; + // 0xd0000 - 0xd3fff + 8'b1101_00xx: bg_a_memrq = 1; + // 0xd4000 - 0xd7fff + 8'b1101_01xx: bg_b_memrq = 1; + default: begin end// nothing + endcase + end + + // M72 + default: begin + casex (A[19:12]) + // 0xc0xxx + 8'b1100_0000: sprite_memrq = 1; + // 0xc8xxx + 8'b1100_1000: sprite_palette_memrq = 1; + // 0xccxxx + 8'b1100_1100: bg_palette_memrq = 1; + // 0xd0000 - 0xd3fff + 8'b1101_00xx: bg_a_memrq = 1; + // 0xd8000 - 0xdbfff + 8'b1101_10xx: bg_b_memrq = 1; + // 0xexxxx + 8'b1110_xxxx: sound_memrq = 1; + default: begin end// nothing + endcase + end + endcase end -endmodule - -module pal_3d -( - input logic [19:0] A, - input logic M_IO, - input logic DBEN, - input logic TNSL, - input logic BRQ, - - output logic BUFDBEN, - output logic BUFCS, - output logic OBJ_P, - output logic CHARA_P, - output logic CHARA, - output logic SOUND, - output logic SDBEN -); - always_comb begin - BUFDBEN = A[19] & A[18] & !A[17] & !A[16] & !A[15] & !A[14] & M_IO & !DBEN & TNSL; + sprite_dma = 0; + iset_data = 16'd0; + iset = 2'b00; - BUFCS = TNSL & (!A[19] | !A[18] | A[17] | A[16] | A[15] | A[14] | !M_IO); // TODO unused, neg M_IO is not safe here - - OBJ_P = A[19] & A[18] & !A[17] & !A[16] & A[15] & !A[14] & M_IO; - - CHARA_P = A[19] & A[18] & !A[17] & !A[16] & A[15] & A[14] & M_IO; - - CHARA = A[19] & A[18] & !A[17] & A[16] & M_IO; - - SOUND = A[19] & A[18] & A[17] & !A[16] & M_IO; - - SDBEN = A[19] & A[18] & A[17] & !A[16] & M_IO & !DBEN & BRQ; + // M84 + if (board_cfg.m84) begin + if (M_IO & wr) begin + sprite_dma = A == 20'hbc000; + if (A == 20'hb0000) begin + iset = bytesel; + iset_data = data; + end else if (A == 20'hb0001) begin + iset = 2'b10; + iset_data = { data[7:0], 8'h00 }; + end + end + end else begin + if (!M_IO & wr) begin + sprite_dma = A == 8'h04; + if (A == 8'h06) begin + iset = 2'b01; + iset_data = { 8'h00, data[7:0] }; + end else if (A == 8'h07) begin + iset = 2'b10; + iset_data = { data[7:0], 8'h00 }; + end + end + end end - endmodule - diff --git a/Arcade_MiST/IremM72 Hardware/rtl/rom.sv b/Arcade_MiST/IremM72 Hardware/rtl/rom.sv index a9b2b8c5..7ceb27f4 100644 --- a/Arcade_MiST/IremM72 Hardware/rtl/rom.sv +++ b/Arcade_MiST/IremM72 Hardware/rtl/rom.sv @@ -30,7 +30,7 @@ module rom_loader output ioctl_wait, - output [24:1] sdr_addr, + output [24:0] sdr_addr, output [15:0] sdr_data, output [1:0] sdr_be, output reg sdr_req, @@ -38,7 +38,7 @@ module rom_loader output [19:0] bram_addr, output [7:0] bram_data, - output reg [1:0] bram_cs, + output reg [3:0] bram_cs, output bram_wr, output board_cfg_t board_cfg @@ -47,14 +47,14 @@ module rom_loader reg [24:0] base_addr; reg reorder_64; reg [24:0] offset; -reg [31:0] size; +reg [23:0] size; enum { BOARD_CFG, + REGION_IDX, SIZE_0, SIZE_1, SIZE_2, - SIZE_3, SDR_DATA, BRAM_DATA } stage = BOARD_CFG; @@ -73,20 +73,23 @@ always @(posedge sys_clk) begin if (ioctl_wr) begin case (stage) - BOARD_CFG: begin board_cfg <= board_cfg_t'(ioctl_data); stage <= SIZE_0; end - SIZE_0: begin size[31:24] <= ioctl_data; stage <= SIZE_1; end - SIZE_1: begin size[23:16] <= ioctl_data; stage <= SIZE_2; end - SIZE_2: begin size[15:8] <= ioctl_data; stage <= SIZE_3; end - SIZE_3: begin + BOARD_CFG: begin board_cfg <= board_cfg_t'(ioctl_data); stage <= REGION_IDX; end + REGION_IDX: begin + if (ioctl_data == 8'hff) region <= region + 4'd1; + else region <= ioctl_data[3:0]; + stage <= SIZE_0; + end + SIZE_0: begin size[23:16] <= ioctl_data; stage <= SIZE_1; end + SIZE_1: begin size[15:8] <= ioctl_data; stage <= SIZE_2; end + SIZE_2: begin size[7:0] <= ioctl_data; base_addr <= LOAD_REGIONS[region].base_addr; reorder_64 <= LOAD_REGIONS[region].reorder_64; bram_cs <= LOAD_REGIONS[region].bram_cs; - region <= region + 4'd1; offset <= 25'd0; - if ({size[31:8], ioctl_data} == 32'd0) - stage <= SIZE_0; + if ({size[23:8], ioctl_data} == 24'd0) + stage <= REGION_IDX; else if (LOAD_REGIONS[region].bram_cs != 0) stage <= BRAM_DATA; else @@ -94,16 +97,16 @@ always @(posedge sys_clk) begin end SDR_DATA: begin if (reorder_64) - sdr_addr <= base_addr[24:1] + {offset[24:7], offset[5:2], offset[6], offset[1]}; + sdr_addr <= base_addr[24:0] + {offset[24:7], offset[5:2], offset[6], offset[1:0]}; else - sdr_addr <= base_addr[24:1] + offset[24:1]; + sdr_addr <= base_addr[24:0] + offset[24:0]; sdr_data = {ioctl_data, ioctl_data}; sdr_be <= { offset[0], ~offset[0] }; offset <= offset + 25'd1; sdr_req <= ~sdr_req; ioctl_wait <= 1; - if (offset == ( size - 1)) stage <= SIZE_0; + if (offset == ( size - 1)) stage <= REGION_IDX; end BRAM_DATA: begin bram_addr <= offset[19:0]; @@ -111,7 +114,7 @@ always @(posedge sys_clk) begin bram_wr <= 1; offset <= offset + 25'd1; - if (offset == ( size - 1)) stage <= SIZE_0; + if (offset == ( size - 1)) stage <= REGION_IDX; end endcase end diff --git a/Arcade_MiST/IremM72 Hardware/rtl/sample_rom.sv b/Arcade_MiST/IremM72 Hardware/rtl/sample_rom.sv new file mode 100644 index 00000000..1248a70b --- /dev/null +++ b/Arcade_MiST/IremM72 Hardware/rtl/sample_rom.sv @@ -0,0 +1,49 @@ +module sample_rom( + input clk, + input reset, + + input [7:0] sample_addr_in, + input [1:0] sample_addr_wr, + + output reg [7:0] sample_data, + input sample_inc, + + // ioctl + output reg [24:0] sample_rom_addr, + input [63:0] sample_rom_dout, + output reg sample_rom_req = 0, + input sample_rom_ack +); + +reg [17:0] sample_addr = 0; + +always_ff @(posedge clk) begin + if (sample_inc) begin + sample_addr <= sample_addr + 18'd1; + sample_rom_addr <= {REGION_SAMPLES.base_addr[24:18], sample_addr[17:0]}; + if(sample_addr[17:3] != sample_rom_addr[17:3]) + sample_rom_req <= ~sample_rom_req; + end + + if (sample_addr_wr[0]) sample_addr[12:0] <= {sample_addr_in, 5'd0}; + if (sample_addr_wr[1]) begin + sample_addr[17:13] <= sample_addr_in[4:0]; + sample_rom_addr <= {REGION_SAMPLES.base_addr[24:18], sample_addr_in[4:0], sample_addr[12:0]}; + sample_rom_req <= ~sample_rom_req; + end +end + +always @(*) begin + case(sample_rom_addr[2:0]) + 3'd0: sample_data = sample_rom_dout[ 7: 0]; + 3'd1: sample_data = sample_rom_dout[15: 8]; + 3'd2: sample_data = sample_rom_dout[23:16]; + 3'd3: sample_data = sample_rom_dout[31:24]; + 3'd4: sample_data = sample_rom_dout[39:32]; + 3'd5: sample_data = sample_rom_dout[47:40]; + 3'd6: sample_data = sample_rom_dout[55:48]; + default: sample_data = sample_rom_dout[63:56]; + endcase; +end + +endmodule diff --git a/Arcade_MiST/IremM72 Hardware/rtl/sdram_4w.sv b/Arcade_MiST/IremM72 Hardware/rtl/sdram_4w.sv index ba594201..a5804623 100644 --- a/Arcade_MiST/IremM72 Hardware/rtl/sdram_4w.sv +++ b/Arcade_MiST/IremM72 Hardware/rtl/sdram_4w.sv @@ -98,7 +98,7 @@ module sdram_4w ( input sample_req, output reg sample_ack = 0, input [22:1] sample_addr, - output reg [63:0] sample_data, + output reg [63:0] sample_q, input sp_req, output reg sp_ack = 0, @@ -434,7 +434,7 @@ always @(posedge clk) begin PORT_REQ : port2_q[15:0] <= sd_din; PORT_GFX1 : gfx1_q[15:0] <= sd_din; PORT_GFX2 : gfx2_q[15:0] <= sd_din; - PORT_SAMPLE: sample_data[15:0] <= sd_din; + PORT_SAMPLE: sample_q[15:0] <= sd_din; PORT_SP : sp_q[15:0] <= sd_din; default: ; endcase; @@ -449,22 +449,22 @@ always @(posedge clk) begin PORT_REQ : begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end PORT_GFX1 : begin gfx1_q[31:16] <= sd_din; gfx1_ack <= gfx1_req; end PORT_GFX2 : begin gfx2_q[31:16] <= sd_din; gfx2_ack <= gfx2_req; end - PORT_SAMPLE: sample_data[31:16] <= sd_din; + PORT_SAMPLE: sample_q[31:16] <= sd_din; PORT_SP : sp_q[31:16] <= sd_din; default: ; endcase; end if(t == STATE_READ1c && oe_latch[1]) begin case(port[1]) - PORT_SAMPLE: sample_data[47:32] <= sd_din; - PORT_SP: sp_q[47:32] <= sd_din; + PORT_SAMPLE: sample_q[47:32] <= sd_din; + PORT_SP: sp_q[47:32] <= sd_din; default: ; endcase; end if(t == STATE_READ1d && oe_latch[1]) begin case(port[1]) - PORT_SAMPLE: begin sample_data[63:48] <= sd_din; sample_ack <= sample_req; end - PORT_SP: begin sp_q[63:48] <= sd_din; sp_ack <= sp_req; end + PORT_SAMPLE: begin sample_q[63:48] <= sd_din; sample_ack <= sample_req; end + PORT_SP: begin sp_q[63:48] <= sd_din; sp_ack <= sp_req; end default: ; endcase; end diff --git a/Arcade_MiST/IremM72 Hardware/rtl/sound.sv b/Arcade_MiST/IremM72 Hardware/rtl/sound.sv index 0f092395..6a7af489 100644 --- a/Arcade_MiST/IremM72 Hardware/rtl/sound.sv +++ b/Arcade_MiST/IremM72 Hardware/rtl/sound.sv @@ -29,13 +29,21 @@ module sound ( output [7:0] snd_io_data, output snd_io_req, - input SOUND, + output reg sample_inc, + output [7:0] sample_addr, + output reg [1:0] sample_addr_wr, + output reg [7:0] sample_out, + input [7:0] sample_in, + input sample_ready, + input SND, input SND2, input BRQ, input pause, + input m84, + output [15:0] ym_audio_l, output [15:0] ym_audio_r, @@ -58,14 +66,15 @@ jtframe_frac_cen #(2) jt51_cen .cen({CE_AUDIO_P1, CE_AUDIO}) ); +wire ram_region = m84 ? &ram_addr[15:12] : 1'b1; assign ram_cs = ~z80_MREQ_n & z80_IORQ_n & z80_RFSH_n; -assign ram_we = ~z80_WR_n; +assign ram_we = ~z80_WR_n & ram_region; wire [7:0] SD_IN = z80_dout; wire [7:0] SD_OUT; wire SA0 = z80_addr[0]; -wire SCS = ~z80_IORQ_n && (z80_addr[2:1] == 2'b00); +wire SCS = ~z80_IORQ_n & ~|z80_addr[7:1]; wire SIRQ_N; wire SRESET; wire SWR_N = z80_WR_n; @@ -74,15 +83,38 @@ wire M1_n; wire [15:0] z80_addr; wire z80_IORQ_n, z80_RD_n, z80_WR_n, z80_MREQ_n, z80_M1_n, z80_RFSH_n; -assign ram_addr = {REGION_CPU2_RAM.base_addr[24:16], z80_addr}; +assign ram_addr = {REGION_SOUND.base_addr[24:16], z80_addr}; assign ram_data = z80_dout; -wire [7:0] z80_din = ( ~z80_M1_n & ~z80_IORQ_n ) ? {2'b11, ~snd_latch1_ready, SIRQ_N, 4'b1111} : - ( ~z80_RD_n & ~z80_IORQ_n & (z80_addr[2:1] == 2'b01)) ? snd_latch1 : - ( ~z80_RD_n & ~z80_IORQ_n & (z80_addr[2:1] == 2'b10)) ? snd_latch2 : - ( ~z80_RD_n & SCS ) ? SD_OUT : - ( ~z80_RD_n ) ? ram_dout : 8'hff; +reg [7:0] z80_din; wire [7:0] z80_dout; +always_comb begin + z80_din = 8'hff; + if ( ~z80_M1_n & ~z80_IORQ_n ) begin + z80_din = {2'b11, ~snd_latch1_ready, SIRQ_N, 4'b1111}; + end else if ( ~z80_RD_n ) begin + if (SCS) begin + z80_din = SD_OUT; + end else if (~z80_IORQ_n) begin + if (m84) begin + casex (z80_addr[7:0]) + 8'h80: z80_din = snd_latch1; + 8'h84: z80_din = sample_in; + default: z80_din = 8'hff; + endcase + end else begin + casex (z80_addr[7:0]) + 8'bxxxx_x01x: z80_din = snd_latch1; + 8'bxxxx_x10x: z80_din = snd_latch2; + default: z80_din = 8'hff; + endcase + end + end else begin + z80_din = ram_dout; + end + end +end + assign snd_io_addr = z80_addr[7:0]; assign snd_io_req = ~z80_IORQ_n; assign snd_io_data = z80_dout; @@ -90,7 +122,7 @@ assign snd_io_data = z80_dout; T80s z80( .RESET_n(~BRQ & reset_n), .CLK(CLK_32M), - .CEN(CE_AUDIO & ~pause & ~(ram_cs & ~ram_valid)), + .CEN(CE_AUDIO & ~pause & ~(ram_cs & ~ram_valid) & sample_ready), .INT_n(~(~SIRQ_N | snd_latch1_ready)), .BUSRQ_n(~BRQ), .M1_n(z80_M1_n), @@ -102,7 +134,7 @@ T80s z80( .A(z80_addr), .DI(z80_din), .DO(z80_dout), - .NMI_n(~snd_latch2_ready) + .NMI_n(m84 ? ~m84_nmi : ~snd_latch2_ready) ); jt51 ym2151( @@ -126,11 +158,23 @@ reg snd_latch1_ready = 0; reg [7:0] snd_latch2; reg snd_latch2_ready = 0; +reg [11:0] nmi_counter = 0; +reg m84_nmi = 0; +reg z80_IORQ_n_old; +assign sample_addr = z80_dout; + always @(posedge CLK_32M) begin + sample_inc <= 0; + sample_addr_wr <= 2'b00; + if (~reset_n) begin - snd_latch1_ready <= 0; - snd_latch2_ready <= 0; - end else begin + m84_nmi <= 0; + nmi_counter <= 0; + end else if (~pause) begin + + nmi_counter <= nmi_counter + 12'd1; + if (&nmi_counter) m84_nmi <= 1; + if (SND & ~IO_A[0]) begin snd_latch1 <= IO_DIN[7:0]; snd_latch1_ready <= 1; @@ -141,10 +185,33 @@ always @(posedge CLK_32M) begin snd_latch2_ready <= 1; end - if (~z80_IORQ_n & ~z80_WR_n & z80_addr[2:1] == 2'b11) snd_latch1_ready <= 0; - if (~z80_IORQ_n & ~z80_RD_n & (z80_addr[2:1] == 2'b10)) snd_latch2_ready <= 0; - end + if (~z80_M1_n && ~z80_MREQ_n && z80_addr == 16'h0066) + m84_nmi <= 0; + z80_IORQ_n_old <= z80_IORQ_n; + if (z80_IORQ_n_old & ~z80_IORQ_n) begin + + if (m84) begin + if (~z80_WR_n & z80_addr[7:0] == 8'h80) begin + sample_addr_wr <= 2'b01; + end + + if (~z80_WR_n & z80_addr[7:0] == 8'h81) begin + sample_addr_wr <= 2'b10; + end + + if (~z80_WR_n & z80_addr[7:0] == 8'h82) begin + sample_out <= z80_dout; + sample_inc <= 1; + end + + if (~z80_WR_n & z80_addr[7:0] == 8'h83) snd_latch1_ready <= 0; + end else begin + if (~z80_WR_n & z80_addr[2:1] == 2'b11) snd_latch1_ready <= 0; + if (~z80_RD_n & (z80_addr[2:1] == 2'b10)) snd_latch2_ready <= 0; + end + end + end end endmodule diff --git a/Arcade_MiST/IremM72 Hardware/rtl/sprite.sv b/Arcade_MiST/IremM72 Hardware/rtl/sprite.sv index 6678c687..dca16b0e 100644 --- a/Arcade_MiST/IremM72 Hardware/rtl/sprite.sv +++ b/Arcade_MiST/IremM72 Hardware/rtl/sprite.sv @@ -230,7 +230,7 @@ always_ff @(posedge CLK_96M) begin st <= st; // wait else begin line_buffer_color <= obj_color; - line_buffer_x = obj_org_x + ( 10'd16 * span ); + line_buffer_x <= obj_org_x + ( 10'd16 * span ); line_buffer_req <= ~line_buffer_ack; end end