From f1b4412be93f3967708d87a937409b03490c6b5a Mon Sep 17 00:00:00 2001 From: Jose Tejada Date: Tue, 9 Mar 2021 19:11:30 +0100 Subject: [PATCH] Still no input read --- .../rtl/druaga_sprite.v | 4 +++ .../rtl/druaga_video.v | 8 ++++- .../rtl/fpga_druaga.v | 16 +++++++--- .../Namco Super Pacman Hardware/rtl/hvgen.v | 15 ++++++--- .../Namco Super Pacman Hardware/rtl/ioctrl.v | 32 +++++++++++-------- .../rtl/ioctrl_1.v | 21 ++++++------ 6 files changed, 62 insertions(+), 34 deletions(-) diff --git a/Arcade_MiST/Namco Super Pacman Hardware/rtl/druaga_sprite.v b/Arcade_MiST/Namco Super Pacman Hardware/rtl/druaga_sprite.v index 851af789..087da6bc 100644 --- a/Arcade_MiST/Namco Super Pacman Hardware/rtl/druaga_sprite.v +++ b/Arcade_MiST/Namco Super Pacman Hardware/rtl/druaga_sprite.v @@ -2,6 +2,10 @@ FPGA Druaga ( Sprite Part ) Copyright (c) 2007 MiSTer-X + + Super Pacman Support + (c) 2021 Jose Tejada, jotego + ************************************/ module DRUAGA_SPRITE ( diff --git a/Arcade_MiST/Namco Super Pacman Hardware/rtl/druaga_video.v b/Arcade_MiST/Namco Super Pacman Hardware/rtl/druaga_video.v index 07a4dc6a..77954e86 100644 --- a/Arcade_MiST/Namco Super Pacman Hardware/rtl/druaga_video.v +++ b/Arcade_MiST/Namco Super Pacman Hardware/rtl/druaga_video.v @@ -2,6 +2,10 @@ FPGA Druaga ( Video Part ) Copyright (c) 2007 MiSTer-X + + Super Pacman Support + (c) 2021 Jose Tejada, jotego + ************************************/ module DRUAGA_VIDEO ( @@ -37,7 +41,7 @@ wire [8:0] VPOS = PV; wire oHB = (PH>=290) & (PH<492); -assign VB = (PV==224); +assign VB = (PV==227); reg [4:0] PALT_A; wire [7:0] PALT_D; @@ -95,6 +99,8 @@ always @(*) begin ROW = VPOS[8:3]; if( MODEL==SUPERPAC ) begin + // This +2 adjustment is due to using a linear video timing generator + // rather than the original circuit count. ROW = ROW + 6'h2; VRAMADRS = { 1'b0, COL[5] ? {COL[4:0], ROW[4:0]} : diff --git a/Arcade_MiST/Namco Super Pacman Hardware/rtl/fpga_druaga.v b/Arcade_MiST/Namco Super Pacman Hardware/rtl/fpga_druaga.v index b9bb4c15..44515e8c 100644 --- a/Arcade_MiST/Namco Super Pacman Hardware/rtl/fpga_druaga.v +++ b/Arcade_MiST/Namco Super Pacman Hardware/rtl/fpga_druaga.v @@ -3,8 +3,11 @@ Copyright (c) 2007 MiSTer-X - Conversion to clock-enable: - (c) 2019 Slingshot + Conversion to clock-enable: + (c) 2019 Slingshot + + Super Pacman Support + (c) 2021 Jose Tejada, jotego ************************************/ module fpga_druaga ( @@ -14,9 +17,9 @@ module fpga_druaga input [8:0] PH, // Screen H input [8:0] PV, // Screen V - output PCLK, // Pixel Clock + output PCLK, // Pixel Clock output PCLK_EN, - output [7:0] POUT, // Pixel Color + output [7:0] POUT, // Pixel Color output [7:0] SOUT, // Sound Out output [14:0] rom_addr, @@ -138,7 +141,10 @@ DRUAGA_VIDEO video .ROMAD(ROMAD),.ROMDT(ROMDT),.ROMEN(ROMEN), .MODEL(MODEL) ); -assign POUT = (IsMOTOS & (PV==0)) ? 8'h0 : oPOUT; + +// This prevents a glitch in the sprites for the first line +// but it hides the top line of the CRT test screen +assign POUT = (IsMOTOS && (PV==0)) ? 8'h0 : oPOUT; // MainCPU diff --git a/Arcade_MiST/Namco Super Pacman Hardware/rtl/hvgen.v b/Arcade_MiST/Namco Super Pacman Hardware/rtl/hvgen.v index e3dc0905..322471a9 100644 --- a/Arcade_MiST/Namco Super Pacman Hardware/rtl/hvgen.v +++ b/Arcade_MiST/Namco Super Pacman Hardware/rtl/hvgen.v @@ -11,6 +11,11 @@ module hvgen output reg VSYN = 1 ); +localparam [8:0] VS_START = 9'd228, + VS_END = VS_START+9'd3, + VB_START = 9'd223, + VB_END = 9'd511; + reg [8:0] hcnt = 0; reg [8:0] vcnt = 0; @@ -26,10 +31,10 @@ always @(posedge MCLK) begin 342: begin HSYN <= 1; hcnt <= 9'd470; end 511: begin hcnt <= 0; case (vcnt) - 223: begin VBLK <= 1; vcnt <= vcnt+1'd1; end - 226: begin VSYN <= 0; vcnt <= vcnt+1'd1; end - 233: begin VSYN <= 1; vcnt <= 9'd483; end - 511: begin VBLK <= 0; vcnt <= 0; end + VB_START: begin VBLK <= 1; vcnt <= vcnt+1'd1; end + VS_START: begin VSYN <= 0; vcnt <= vcnt+1'd1; end + VS_END: begin VSYN <= 1; vcnt <= 9'd483; end + VB_END: begin VBLK <= 0; vcnt <= 0; end default: vcnt <= vcnt+1'd1; endcase end @@ -37,4 +42,4 @@ always @(posedge MCLK) begin endcase end -endmodule \ No newline at end of file +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Namco Super Pacman Hardware/rtl/ioctrl.v b/Arcade_MiST/Namco Super Pacman Hardware/rtl/ioctrl.v index a6a8ba32..34bb82c3 100644 --- a/Arcade_MiST/Namco Super Pacman Hardware/rtl/ioctrl.v +++ b/Arcade_MiST/Namco Super Pacman Hardware/rtl/ioctrl.v @@ -1,10 +1,18 @@ /**************************************************** FPGA Druaga ( Custom I/O chip emulation part ) - Copyright (c) 2007 MiSTer-X + Copyright (c) 2007 MiSTer-X + + Super Pacman Support + (c) 2021 Jose Tejada, jotego + *****************************************************/ -module IOCTRL( CLK, UPDATE, RESET, ENABLE, WR, ADRS, IN, OUT, STKTRG12, CSTART12, - DIPSW, IsMOTOS, MODEL ); +module IOCTRL( CLK, UPDATE, RESET, ENABLE, WR, ADRS, IN, OUT, + STKTRG12, // Joystick controls + CSTART12, // Start buttons + DIPSW, + IsMOTOS, + MODEL ); input CLK; input UPDATE; input RESET; @@ -34,13 +42,14 @@ reg [9:0] pSTKTRG12; reg [2:0] pCSTART12; reg bUpdate; -reg bIOMode = 0; +reg bIOMode; parameter [2:0] SUPERPAC=3'd5; assign OUT = { 4'b1111, outr }; assign IsMOTOS = bIOMode; +// Detect falling edges: wire [11:0] iSTKTRG12 = ( STKTRG12 ^ pSTKTRG12 ) & STKTRG12; wire [ 2:0] iCSTART12 = ( CSTART12 ^ pCSTART12 ) & CSTART12; @@ -48,7 +57,6 @@ wire [ 3:0] CREDIT_ONES, CREDIT_TENS; BCDCONV creditsBCD( credits, CREDIT_ONES, CREDIT_TENS ); always @ ( posedge CLK ) begin - if ( ENABLE ) begin if ( ADRS[5] ) begin if ( WR ) memc[ADRS[4:0]] <= IN; @@ -61,19 +69,18 @@ always @ ( posedge CLK ) begin outr <= mema[ADRS[3:0]]; end end - if ( RESET ) begin pCSTART12 <= 0; pSTKTRG12 <= 0; bUpdate <= 0; - bIOMode = 0; - credits = 0; - end - else begin + bIOMode <= 0; + credits <= 0; + end else begin if ( UPDATE & (~bUpdate) ) begin - if ( mema[4'h8] == 4'h8 ) bIOMode = 1'b1; // Is running "Motos" ? + if ( mema[4'h8] == 4'h8 || MODEL==SUPERPAC ) + bIOMode <= 1'b1; // Is running "Motos" ? - if ( bIOMode || MODEL==SUPERPAC) begin + if ( bIOMode ) begin `include "ioctrl_1.v" end else begin @@ -85,7 +92,6 @@ always @ ( posedge CLK ) begin end bUpdate <= UPDATE; end - end endmodule diff --git a/Arcade_MiST/Namco Super Pacman Hardware/rtl/ioctrl_1.v b/Arcade_MiST/Namco Super Pacman Hardware/rtl/ioctrl_1.v index 9e12d024..ec449a50 100644 --- a/Arcade_MiST/Namco Super Pacman Hardware/rtl/ioctrl_1.v +++ b/Arcade_MiST/Namco Super Pacman Hardware/rtl/ioctrl_1.v @@ -4,7 +4,7 @@ // Copyright (c) 2007,19 MiSTer-X //------------------------------------------ - case ( mema[4'h8] ) + case ( mema[4'h8] ) 4'h1: begin mema[4'h0] <= { 3'd0, CSTART12[2] }; @@ -17,22 +17,23 @@ mema[4'h7] <= STKTRG12[9:6]; mema[4'h9] <= 0; end - - 4'h8: begin + + 4'h8: begin // Boot up check, expected values by + // the software (Super Pacman, Motos $69, Phozon $1C) mema[4'h0] <= 4'h6; - mema[4'h1] <= 4'h9; + mema[4'h1] <= 4'h9; end default:; - - endcase + + endcase - case ( memb[4'h8] ) - + case ( memb[4'h8] ) + 4'h8: begin memb[4'h0] <= 4'h6; - memb[4'h1] <= 4'h9; + memb[4'h1] <= 4'h9; end 4'h9: begin @@ -49,5 +50,5 @@ default:; - endcase + endcase