mirror of
https://github.com/Gehstock/Mist_FPGA.git
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Merge pull request #40 from gyurco/master
Lunar Landing: works with 512x512x2 bit VRAM
This commit is contained in:
Marcel
GitHub
commit
f4717d6ff0
@ -40,7 +40,7 @@
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# Project-Wide Assignments
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# ========================
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.2
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set_global_assignment -name LAST_QUARTUS_VERSION 13.1
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set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:48:06 MAY 24,2017"
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set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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@ -117,6 +117,41 @@ set_location_assignment PIN_66 -to SDRAM_nWE
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set_location_assignment PIN_59 -to SDRAM_nCS
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set_location_assignment PIN_33 -to SDRAM_CKE
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set_location_assignment PIN_43 -to SDRAM_CLK
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set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
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# Classic Timing Assignments
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# ==========================
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@ -155,7 +190,7 @@ set_global_assignment -name GENERATE_RBF_FILE ON
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# SignalTap II Assignments
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# ========================
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/ll.stp
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# Power Estimation Assignments
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# ============================
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@ -190,6 +225,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/LunarLander_MiST.sv
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set_global_assignment -name VHDL_FILE rtl/llander_top.vhd
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set_global_assignment -name VHDL_FILE rtl/llander.vhd
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set_global_assignment -name VHDL_FILE rtl/llander_vg.vhd
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set_global_assignment -name VHDL_FILE rtl/llander_sb.vhd
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set_global_assignment -name VHDL_FILE rtl/llander_dw.vhd
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set_global_assignment -name VHDL_FILE rtl/llander_ram.vhd
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set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
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@ -200,4 +236,9 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
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set_global_assignment -name VERILOG_FILE rtl/pll.v
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set_global_assignment -name QIP_FILE ../../../common/CPU/T65/T65.qip
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set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
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set_global_assignment -name SIGNALTAP_FILE output_files/ll.stp
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set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
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set_global_assignment -name AUTO_RAM_RECOGNITION ON
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set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION ON
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set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@ -53,7 +53,8 @@ set_time_format -unit ns -decimal_places 3
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create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
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set sys_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
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set sys_clk "pll|altpll_component|auto_generated|pll1|clk[2]"
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set vid_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
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set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
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#**************************************************************
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# Create Generated Clock
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@ -92,7 +93,7 @@ set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [ge
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set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}]
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set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}]
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set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}]
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set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}]
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set_output_delay -add_delay -clock_fall -clock [get_clocks $vid_clk] 1.000 [get_ports {VGA_*}]
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set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
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set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
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@ -113,6 +114,9 @@ set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks
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# Set Multicycle Path
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#**************************************************************
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set_multicycle_path -from [get_clocks $sys_clk] -to [get_clocks $vid_clk] -setup 2
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set_multicycle_path -from [get_clocks $sys_clk] -to [get_clocks $vid_clk] -hold 1
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set_multicycle_path -to {VGA_*[*]} -setup 2
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set_multicycle_path -to {VGA_*[*]} -hold 1
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3
Arcade_MiST/Atari Vector/LunarLander_MiST/README.txt
Normal file
3
Arcade_MiST/Atari Vector/LunarLander_MiST/README.txt
Normal file
@ -0,0 +1,3 @@
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Lunar Lander for MiST
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VGA only
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@ -33,7 +33,6 @@ module LunarLander_MiST(
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localparam CONF_STR = {
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"LLANDER;ROM;",
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"O12,Scanlines,None,CRT 25%,CRT 50%,CRT 75%;",
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"O3,Test,Off,On;",
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"O45,Language,English,Spanish,French,German;",
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"O68,Fuel,450,600,750,900,1100,1300,1550,1800;",
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@ -43,15 +42,15 @@ localparam CONF_STR = {
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assign LED = ~ioctl_downl;
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assign AUDIO_R = AUDIO_L;
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assign SDRAM_CLK = clk_50;
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assign SDRAM_CLK = clk_72;
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assign SDRAM_CKE = 1;
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wire clk_50, clk_25, clk_6, locked;
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wire clk_72, clk_50, clk_6, locked;
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pll pll(
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.inclk0(CLOCK_27),
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.c0(clk_50),
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.c1(clk_25),
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.c2(clk_6),
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.c0(clk_72), //memclk = 12x sysclk
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.c1(clk_50), //video clk
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.c2(clk_6), //sysclk
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.locked(locked)
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);
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@ -72,10 +71,6 @@ wire [7:0] audio;
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wire key_strobe;
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wire key_pressed;
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wire [7:0] key_code;
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wire [12:0] cpu_rom_addr;
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wire [15:0] cpu_rom_data;
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wire [12:0] vector_rom_addr;
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wire [15:0] vector_rom_data;
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wire ioctl_downl;
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wire [7:0] ioctl_index;
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wire ioctl_wr;
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@ -83,7 +78,7 @@ wire [24:0] ioctl_addr;
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wire [7:0] ioctl_dout;
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data_io data_io(
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.clk_sys ( clk_25 ),
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.clk_sys ( clk_72 ),
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.SPI_SCK ( SPI_SCK ),
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.SPI_SS2 ( SPI_SS2 ),
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.SPI_DI ( SPI_DI ),
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@ -94,11 +89,22 @@ data_io data_io(
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.ioctl_dout ( ioctl_dout )
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);
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wire [12:0] cpu_rom_addr;
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wire [15:0] cpu_rom_data;
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wire [12:0] vector_rom_addr;
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wire [15:0] vector_rom_data;
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wire [9:0] vector_ram_addr;
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wire [15:0] vector_ram_din;
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wire [15:0] vector_ram_dout;
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wire vector_ram_we;
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wire vector_ram_cs1;
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wire vector_ram_cs2;
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reg port1_req, port2_req;
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sdram sdram(
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.*,
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.init_n ( locked ),
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.clk ( clk_50 ),
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.clk ( clk_72 ),
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// port1 used for main CPU
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.port1_req ( port1_req ),
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@ -109,37 +115,44 @@ sdram sdram(
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.port1_d ( {ioctl_dout, ioctl_dout} ),
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.port1_q ( ),
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.cpu1_addr ( ioctl_downl ? 15'h7fff : {3'b000, cpu_rom_addr[12:1]} ),
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.cpu1_q ( cpu_rom_data ),
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.cpu1_addr ( ioctl_downl ? 15'h7fff : {3'b001, vector_rom_addr[12:1]} ),
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.cpu1_q ( vector_rom_data ),
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.cpu2_addr ( ioctl_downl ? 15'h7fff : {3'b000, cpu_rom_addr[12:1]} ),
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.cpu2_q ( cpu_rom_data ),
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// port2 for sound board
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// port2 is for vector RAM
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.port2_req ( port2_req ),
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.port2_ack ( ),
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.port2_a ( ioctl_addr[23:1] - 16'h1000 ),
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.port2_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
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.port2_we ( ioctl_downl ),
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.port2_d ( {ioctl_dout, ioctl_dout} ),
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.port2_q ( ),
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.snd_addr ( ioctl_downl ? 15'h7fff : {3'b000, vector_rom_addr[12:1]} ),
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.snd_q ( vector_rom_data )
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.port2_a ( vector_ram_addr_last ),
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.port2_ds ( {vector_ram_cs2, vector_ram_cs1} ),
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.port2_we ( vector_ram_we_last ),
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.port2_d ( vector_ram_din ),
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.port2_q ( vector_ram_dout )
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);
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always @(posedge clk_25) begin
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reg [9:0] vector_ram_addr_last = 0;
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reg vector_ram_we_last = 0;
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always @(posedge clk_72) begin
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reg ioctl_wr_last = 0;
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ioctl_wr_last <= ioctl_wr;
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if (ioctl_downl) begin
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if (~ioctl_wr_last && ioctl_wr) begin
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port1_req <= ~port1_req;
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port2_req <= ~port2_req;
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end
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end
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if ((vector_ram_cs1 || vector_ram_cs2) && (vector_ram_addr_last != vector_ram_addr || vector_ram_we_last != vector_ram_we)) begin
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vector_ram_addr_last <= vector_ram_addr;
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vector_ram_we_last <= vector_ram_we;
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port2_req <= ~port2_req;
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end
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end
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reg reset = 1;
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reg rom_loaded = 0;
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always @(posedge clk_25) begin
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always @(posedge clk_6) begin
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reg ioctl_downlD;
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ioctl_downlD <= ioctl_downl;
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@ -177,13 +190,22 @@ LLANDER_TOP LLANDER_TOP (
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.DIP({1'b0,1'b0,status[4],status[5],~status[6],1'b1,status[7],status[8]}),//todo dip full
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.RESET_L(~(reset)),
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.clk_6(clk_6),
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.clk_25(clk_25),
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.cpu_rom_addr(cpu_rom_addr),
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.cpu_rom_data (cpu_rom_addr[0] ? cpu_rom_data[15:8] : cpu_rom_data[7:0] ),
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.vector_rom_addr(vector_rom_addr),
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.vector_rom_data (vector_rom_addr[0] ? vector_rom_data[15:8] : vector_rom_data[7:0])
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.clk_50(clk_50),
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.cpu_rom_addr (cpu_rom_addr),
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.cpu_rom_data (cpu_rom_addr[0] ? cpu_rom_data[15:8] : cpu_rom_data[7:0] ),
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.vector_rom_addr (vector_rom_addr),
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.vector_rom_data (vector_rom_addr[0] ? vector_rom_data[15:8] : vector_rom_data[7:0]),
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.vector_ram_addr (vector_ram_addr),
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.vector_ram_din (vector_ram_din),
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.vector_ram_dout (vector_ram_dout),
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.vector_ram_we (vector_ram_we),
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.vector_ram_cs1 (vector_ram_cs1),
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.vector_ram_cs2 (vector_ram_cs2)
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);
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reg ce_pix;
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always @(posedge clk_50) ce_pix <= ~ce_pix;
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ovo #(
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.COLS(1),
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.LINES(1),
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@ -195,8 +217,8 @@ diff (
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.i_hs(~hs),
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.i_vs(~vs),
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.i_de(vgade),
|
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.i_en(1),
|
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.i_clk(clk_25),
|
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.i_en(ce_pix),
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.i_clk(clk_50),
|
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|
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.o_r(ro),
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.o_g(go),
|
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@ -211,13 +233,13 @@ diff (
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reg [7:0] thrust = 0;
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// 1 second = 50,000,000 cycles (duh)
|
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// 1 second = 6,000,000 cycles (duh)
|
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// If we want to go from zero to full throttle in 1 second we tick every
|
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// 196,850 cycles.
|
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always @(posedge clk_50) begin :thrust_count
|
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// 23,529 cycles.
|
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always @(posedge clk_6) begin :thrust_count
|
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int thrust_count;
|
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thrust_count <= thrust_count + 1'd1;
|
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if (thrust_count == 'd196_850) begin
|
||||
if (thrust_count == 'd23529) begin
|
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thrust_count <= 0;
|
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if (m_down && thrust > 0)
|
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thrust <= thrust - 1'd1;
|
||||
@ -228,11 +250,11 @@ always @(posedge clk_50) begin :thrust_count
|
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end
|
||||
|
||||
int diff_count = 0;
|
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always @(posedge clk_50) begin
|
||||
always @(posedge clk_6) begin
|
||||
if (diff_count > 0)
|
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diff_count <= diff_count - 1;
|
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if (~m_fire2)
|
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diff_count <= 'd500_000_000; // 10 seconds
|
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diff_count <= 'd60_000_000; // 10 seconds
|
||||
end
|
||||
|
||||
wire lamp2, lamp3, lamp4, lamp5;
|
||||
@ -248,28 +270,28 @@ always_comb begin
|
||||
difficulty = 2'd0;
|
||||
end
|
||||
|
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mist_video #(.COLOR_DEPTH(6), .SD_HCNT_WIDTH(10)) mist_video(
|
||||
.clk_sys ( clk_25 ),
|
||||
mist_video #(.COLOR_DEPTH(6)) mist_video(
|
||||
.clk_sys ( clk_50 ),
|
||||
.SPI_SCK ( SPI_SCK ),
|
||||
.SPI_SS3 ( SPI_SS3 ),
|
||||
.SPI_DI ( SPI_DI ),
|
||||
.R ( blankn ? ro[7:2] : 0 ),
|
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.G ( blankn ? go[7:2] : 0 ),
|
||||
.B ( blankn ? bo[7:2] : 0 ),
|
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.HSync ( hso ),
|
||||
.VSync ( vso ),
|
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.HSync ( ~hso ),
|
||||
.VSync ( ~vso ),
|
||||
.VGA_R ( VGA_R ),
|
||||
.VGA_G ( VGA_G ),
|
||||
.VGA_B ( VGA_B ),
|
||||
.VGA_VS ( VGA_VS ),
|
||||
.VGA_HS ( VGA_HS ),
|
||||
.scandoubler_disable(1),//scandoublerD ),
|
||||
.scanlines ( status[2:1] ),
|
||||
.no_csync ( 1'b1 ),
|
||||
.ypbpr ( ypbpr )
|
||||
);
|
||||
|
||||
user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io(
|
||||
.clk_sys (clk_25 ),
|
||||
.clk_sys (clk_6 ),
|
||||
.conf_str (CONF_STR ),
|
||||
.SPI_CLK (SPI_SCK ),
|
||||
.SPI_SS_IO (CONF_DATA0 ),
|
||||
@ -290,7 +312,7 @@ user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io(
|
||||
dac #(
|
||||
.C_bits(8))
|
||||
dac(
|
||||
.clk_i(clk_25),
|
||||
.clk_i(clk_6),
|
||||
.res_n_i(1),
|
||||
.dac_i(audio),
|
||||
.dac_o(AUDIO_L)
|
||||
@ -313,10 +335,8 @@ reg btn_fire2 = 0;
|
||||
//reg btn_fire3 = 0;
|
||||
reg btn_coin = 0;
|
||||
|
||||
always @(posedge clk_25) begin
|
||||
reg old_state;
|
||||
old_state <= key_strobe;
|
||||
if(old_state != key_strobe) begin
|
||||
always @(posedge clk_6) begin
|
||||
if(key_strobe) begin
|
||||
case(key_code)
|
||||
'h75: btn_up <= key_pressed; // up
|
||||
'h72: btn_down <= key_pressed; // down
|
||||
|
||||
@ -47,8 +47,8 @@ BEGIN
|
||||
outdata_reg_a => "UNREGISTERED",
|
||||
outdata_reg_b => "UNREGISTERED",
|
||||
power_up_uninitialized => "FALSE",
|
||||
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
|
||||
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
|
||||
read_during_write_mode_port_a => "OLD_DATA",
|
||||
read_during_write_mode_port_b => "OLD_DATA",
|
||||
widthad_a => addr_width_g,
|
||||
widthad_b => addr_width_g,
|
||||
width_a => data_width_g,
|
||||
|
||||
@ -46,15 +46,10 @@ architecture rtl of gen_ram is
|
||||
subtype addressRange is integer range 0 to ((2**aWidth)-1);
|
||||
type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
|
||||
signal ram: ramDef;
|
||||
attribute ramstyle : string;
|
||||
attribute ramstyle of ram : signal is "logic";
|
||||
|
||||
signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
|
||||
signal qReg : std_logic_vector((dWidth-1) downto 0);
|
||||
begin
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Signals to entity interface
|
||||
-- -----------------------------------------------------------------------
|
||||
-- q <= qReg;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Memory write
|
||||
-- -----------------------------------------------------------------------
|
||||
@ -73,12 +68,8 @@ begin
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
-- qReg <= ram(to_integer(unsigned(rAddrReg)));
|
||||
-- rAddrReg <= addr;
|
||||
---- qReg <= ram(to_integer(unsigned(addr)));
|
||||
q <= ram(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
--q <= ram(to_integer(unsigned(addr)));
|
||||
end architecture;
|
||||
|
||||
|
||||
@ -52,7 +52,6 @@ use ieee.std_logic_unsigned.all;
|
||||
entity LLander is
|
||||
port (
|
||||
CLK_6 : in std_logic;
|
||||
CLK_25 : in std_logic;
|
||||
RESET_6_L : in std_logic;
|
||||
--
|
||||
DIP : in std_logic_vector(7 downto 0);
|
||||
@ -85,10 +84,16 @@ entity LLander is
|
||||
Z_VECTOR : out std_logic_vector(3 downto 0);
|
||||
BEAM_ON : out std_logic;
|
||||
BEAM_ENA : out std_logic;
|
||||
cpu_rom_addr : out std_logic_vector(12 downto 0);
|
||||
cpu_rom_data : in std_logic_vector( 7 downto 0);
|
||||
vector_rom_addr : out std_logic_vector(12 downto 0);
|
||||
vector_rom_data : in std_logic_vector( 7 downto 0)
|
||||
cpu_rom_addr : out std_logic_vector(12 downto 0);
|
||||
cpu_rom_data : in std_logic_vector( 7 downto 0);
|
||||
vector_rom_addr : out std_logic_vector(12 downto 0);
|
||||
vector_rom_data : in std_logic_vector( 7 downto 0);
|
||||
vector_ram_addr : out std_logic_vector( 9 downto 0);
|
||||
vector_ram_dout : in std_logic_vector(15 downto 0);
|
||||
vector_ram_din : out std_logic_vector(15 downto 0);
|
||||
vector_ram_we : out std_logic;
|
||||
vector_ram_cs1 : out std_logic;
|
||||
vector_ram_cs2 : out std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
@ -598,9 +603,14 @@ end process;
|
||||
ENA_1_5M_E => ena_1_5m_e,
|
||||
RESET_L => reset_l,
|
||||
CLK_6 => CLK_6,
|
||||
CLK_25 => CLK_25,
|
||||
vector_rom_addr => vector_rom_addr,
|
||||
vector_rom_data => vector_rom_data
|
||||
vector_rom_addr => vector_rom_addr,
|
||||
vector_rom_data => vector_rom_data,
|
||||
vector_ram_addr => vector_ram_addr,
|
||||
vector_ram_din => vector_ram_din,
|
||||
vector_ram_dout => vector_ram_dout,
|
||||
vector_ram_we => vector_ram_we,
|
||||
vector_ram_cs1 => vector_ram_cs1,
|
||||
vector_ram_cs2 => vector_ram_cs2
|
||||
);
|
||||
|
||||
BEAM_ENA <= ena_1_5m;
|
||||
|
||||
@ -423,18 +423,18 @@ begin
|
||||
beam_ena_r := beam_ena;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
video_rgb : work.dpram generic map (16,4)
|
||||
|
||||
|
||||
video_rgb : work.dpram generic map (19,4)
|
||||
port map
|
||||
(
|
||||
clock_a => clk_25,
|
||||
wren_a => vram_wren,
|
||||
address_a => dw_addr(15 downto 0),
|
||||
address_a => dw_addr,
|
||||
data_a => vid_data,
|
||||
|
||||
clock_b => clk_25,
|
||||
address_b => (screen & up_addr(14 downto 0)),
|
||||
address_b => screen & up_addr,
|
||||
q_b => vid_out
|
||||
);
|
||||
|
||||
|
||||
337
Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/llander_sb.vhd
Normal file
337
Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/llander_sb.vhd
Normal file
@ -0,0 +1,337 @@
|
||||
--
|
||||
-- A simulation model of Asteroids Deluxe hardware
|
||||
-- Copyright (c) MikeJ - May 2004
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- You are responsible for any legal issues arising from your use of this code.
|
||||
--
|
||||
-- This code is not part of the original game.
|
||||
|
||||
-- Smaller version (512 x 512 screen), with single buffer and 4 level phosphor persistence
|
||||
-- for flicker-free display and the minimum amount of BRAM.
|
||||
-- Based on LLANDER_DW from Dave Wood (oldgit) Feb 2019
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
--use work.pkg_asteroids.all;
|
||||
|
||||
entity LLANDER_SB is
|
||||
port (
|
||||
RESET : in std_logic;
|
||||
clk_vidx2 : in std_logic;
|
||||
clk_6 : in std_logic;
|
||||
|
||||
X_VECTOR : in std_logic_vector(9 downto 0);
|
||||
Y_VECTOR : in std_logic_vector(9 downto 0);
|
||||
Z_VECTOR : in std_logic_vector(3 downto 0);
|
||||
BEAM_ON : in std_logic;
|
||||
BEAM_ENA : in std_logic;
|
||||
|
||||
VIDEO_R_OUT : out std_logic_vector(3 downto 0);
|
||||
VIDEO_G_OUT : out std_logic_vector(3 downto 0);
|
||||
VIDEO_B_OUT : out std_logic_vector(3 downto 0);
|
||||
HSYNC_OUT : out std_logic;
|
||||
VSYNC_OUT : out std_logic;
|
||||
VID_DE : out std_logic;
|
||||
VID_HBLANK : out std_logic;
|
||||
VID_VBLANK : out std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
architecture RTL of LLANDER_SB is
|
||||
-- types & constants
|
||||
subtype Bus12 is std_logic_vector (11 downto 0);
|
||||
|
||||
constant V_FRONT_PORCH_START : Bus12 := x"1e0"; -- line 480
|
||||
constant V_SYNC_START : Bus12 := x"1ea"; -- line 490
|
||||
constant V_BACK_PORCH_START : Bus12 := x"1ec"; -- line 492
|
||||
constant LINE_PER_FRAME : Bus12 := x"20d"; -- 525 lines
|
||||
|
||||
constant H_FRONT_PORCH_START : Bus12 := x"280"; -- pixel 640
|
||||
constant H_SYNC_START : Bus12 := x"290"; -- pixel 656
|
||||
constant H_BACK_PORCH_START : Bus12 := x"2f0"; -- pixel 752
|
||||
constant PIXEL_PER_LINE : Bus12 := x"320"; -- 800 pixels
|
||||
|
||||
signal CE_PIX : std_logic;
|
||||
|
||||
signal lcount : std_logic_vector(9 downto 0);
|
||||
signal pcount : std_logic_vector(10 downto 0);
|
||||
|
||||
signal hterm : boolean;
|
||||
signal vterm : boolean;
|
||||
signal v_sync : std_logic;
|
||||
signal h_sync : std_logic;
|
||||
signal v_blank : std_logic;
|
||||
signal h_blank : std_logic;
|
||||
signal raster_active : std_logic;
|
||||
|
||||
--
|
||||
signal beam_load : std_logic;
|
||||
signal video_r : std_logic_vector(3 downto 0);
|
||||
signal video_g : std_logic_vector(3 downto 0);
|
||||
signal video_b : std_logic_vector(3 downto 0);
|
||||
|
||||
signal dw_addr : std_logic_vector(17 downto 0);
|
||||
|
||||
signal up_addr : std_logic_vector(17 downto 0);
|
||||
signal Y_Vid : std_logic_vector(8 downto 0);
|
||||
signal X_Vid : std_logic_vector(8 downto 0);
|
||||
|
||||
signal vcount : std_logic_vector(8 downto 0);
|
||||
signal hcount : std_logic_vector(8 downto 0);
|
||||
signal pxcount : std_logic_vector(8 downto 0);
|
||||
signal vram_wren : std_logic;
|
||||
signal vram_clear : std_logic;
|
||||
signal vid_out : std_logic_vector(1 downto 0);
|
||||
signal data_b : std_logic_vector(1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
pixel_ce : process(clk_vidx2, RESET)
|
||||
begin
|
||||
if (RESET = '1') then
|
||||
CE_PIX <= '0';
|
||||
elsif rising_edge(clk_vidx2) then
|
||||
CE_PIX <= not CE_PIX;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
pixel_cnt : process(clk_vidx2, RESET)
|
||||
variable vcnt_front_porch_start : boolean;
|
||||
variable hcnt_front_porch_start : boolean;
|
||||
begin
|
||||
if (RESET = '1') then
|
||||
hcount <= (others => '0');
|
||||
vcount <= (others => '0');
|
||||
|
||||
elsif rising_edge(clk_vidx2) then
|
||||
if CE_PIX = '1' then
|
||||
vcnt_front_porch_start := (vcount = 511);
|
||||
hcnt_front_porch_start := (hcount = 511);
|
||||
|
||||
if hcnt_front_porch_start then
|
||||
hcount <= (others => '0');
|
||||
else
|
||||
hcount <= hcount + "1";
|
||||
end if;
|
||||
|
||||
if hcnt_front_porch_start then
|
||||
if vcnt_front_porch_start then
|
||||
vcount <= (others => '0');
|
||||
else
|
||||
vcount <= vcount + "1";
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- basic raster gen
|
||||
p_cnt_compare_comb : process(pcount,lcount)
|
||||
begin
|
||||
hterm <= (pcount = (PIXEL_PER_LINE(10 downto 0) - "1"));
|
||||
vterm <= (lcount = (LINE_PER_FRAME( 9 downto 0) - "1"));
|
||||
end process;
|
||||
|
||||
p_display_cnt : process(clk_vidx2, RESET)
|
||||
begin
|
||||
if (RESET = '1') then
|
||||
pcount <= (others => '0');
|
||||
lcount <= (others => '0');
|
||||
elsif rising_edge(clk_vidx2) then
|
||||
if CE_PIX = '1' then
|
||||
if hterm then
|
||||
pcount <= (others => '0');
|
||||
else
|
||||
pcount <= pcount + "1";
|
||||
end if;
|
||||
|
||||
if pcount > 63 then
|
||||
pxcount <= pxcount + "1";
|
||||
raster_active <= '1';
|
||||
end if;
|
||||
if pcount > 575 then
|
||||
raster_active <= '0';
|
||||
pxcount <= "111111111";
|
||||
end if;
|
||||
|
||||
if hterm then
|
||||
if vterm then
|
||||
lcount <= (others => '0');
|
||||
else
|
||||
lcount <= lcount + "1";
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_vsync : process(clk_vidx2, RESET)
|
||||
variable vcnt_eq_front_porch_start : boolean;
|
||||
variable vcnt_eq_sync_start : boolean;
|
||||
variable vcnt_eq_back_porch_start : boolean;
|
||||
begin
|
||||
if (RESET = '1') then
|
||||
v_sync <= '1';
|
||||
v_blank <= '0';
|
||||
elsif rising_edge(clk_vidx2) then
|
||||
if CE_PIX = '1' then
|
||||
|
||||
vcnt_eq_front_porch_start := (lcount = (V_FRONT_PORCH_START(9 downto 0) - "1"));
|
||||
vcnt_eq_sync_start := (lcount = ( V_SYNC_START(9 downto 0) - "1"));
|
||||
vcnt_eq_back_porch_start := (lcount = ( V_BACK_PORCH_START(9 downto 0) - "1"));
|
||||
|
||||
if vcnt_eq_sync_start and hterm then
|
||||
v_sync <= '0';
|
||||
elsif vcnt_eq_back_porch_start and hterm then
|
||||
v_sync <= '1';
|
||||
end if;
|
||||
|
||||
if vcnt_eq_front_porch_start and hterm then
|
||||
v_blank <= '1';
|
||||
elsif vterm and hterm then
|
||||
v_blank <= '0';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_hsync : process(clk_vidx2, RESET)
|
||||
variable hcnt_eq_front_porch_start : boolean;
|
||||
variable hcnt_eq_sync_start : boolean;
|
||||
variable hcnt_eq_back_porch_start : boolean;
|
||||
begin
|
||||
if (RESET = '1') then
|
||||
h_sync <= '1';
|
||||
h_blank <= '1'; -- 0
|
||||
elsif rising_edge(clk_vidx2) then
|
||||
if CE_PIX = '1' then
|
||||
hcnt_eq_front_porch_start := (pcount = ( H_FRONT_PORCH_START(10 downto 0) - "1"));
|
||||
hcnt_eq_sync_start := (pcount = ( H_SYNC_START(10 downto 0) - "1"));
|
||||
hcnt_eq_back_porch_start := (pcount = ( H_BACK_PORCH_START(10 downto 0) - "1"));
|
||||
|
||||
if hcnt_eq_sync_start then
|
||||
h_sync <= '0';
|
||||
elsif hcnt_eq_back_porch_start then
|
||||
h_sync <= '1';
|
||||
end if;
|
||||
|
||||
if hcnt_eq_front_porch_start then
|
||||
h_blank <= '1';
|
||||
elsif hterm then
|
||||
h_blank <= '0';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_active_video : process(h_blank, v_blank, raster_active, lcount, pxcount)
|
||||
begin
|
||||
-- raster_active <= not(h_blank or v_blank);
|
||||
if raster_active = '1' then
|
||||
Y_Vid <= not (lcount(8 downto 0) and lcount(8 downto 0)) ;
|
||||
else
|
||||
Y_Vid <= "111111111";
|
||||
end if;
|
||||
if raster_active = '1' then
|
||||
X_Vid <= pxcount(8 downto 0);
|
||||
else
|
||||
X_Vid <= "111111111";
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
p_video_out : process(clk_vidx2)
|
||||
begin
|
||||
if rising_edge(clk_vidx2) then
|
||||
if CE_PIX = '1' then
|
||||
if raster_active = '1' and vid_out /= "00" then
|
||||
VIDEO_R_OUT <= "1111";
|
||||
VIDEO_G_OUT <= "1111";
|
||||
VIDEO_B_OUT <= "1111";
|
||||
else -- blank
|
||||
VIDEO_R_OUT <= "0000";
|
||||
VIDEO_G_OUT <= "0000";
|
||||
VIDEO_B_OUT <= "0000";
|
||||
end if;
|
||||
VID_DE <= not(v_blank or h_blank);
|
||||
VSYNC_OUT <= v_sync;
|
||||
HSYNC_OUT <= h_sync;
|
||||
VID_HBLANK <= h_blank;
|
||||
VID_VBLANK <= v_blank;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
up_addr <= (Y_Vid(8 downto 0) & X_Vid(8 downto 0));
|
||||
|
||||
write_ram : process(clk_6, RESET)
|
||||
begin
|
||||
if RESET = '1' then
|
||||
vram_wren <= '0';
|
||||
elsif rising_edge(clk_6) then
|
||||
vram_wren <= '0';
|
||||
|
||||
dw_addr <= (Y_VECTOR(9 downto 1) ) & X_VECTOR(9 downto 1);
|
||||
if BEAM_ON = '1' and BEAM_ENA = '1' then
|
||||
if Z_VECTOR(3 downto 0) = "0000" then
|
||||
vram_wren <= '0';
|
||||
else
|
||||
vram_wren <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
data_b <= "00" when vid_out = "00" else vid_out - 1;
|
||||
vram_clear <= '1';
|
||||
|
||||
video_rgb : work.dpram generic map (18,2)
|
||||
port map
|
||||
(
|
||||
clock_a => clk_6,
|
||||
wren_a => vram_wren,
|
||||
address_a => dw_addr,
|
||||
data_a => "11", -- more correct, but flickering: Z_VECTOR(3 downto 2),
|
||||
|
||||
clock_b => clk_vidx2,
|
||||
wren_b => vram_clear, -- clear right after read, must use dpram with "READ OLD DATA DURING WRITE"
|
||||
data_b => data_b,
|
||||
address_b => up_addr,
|
||||
q_b => vid_out
|
||||
);
|
||||
|
||||
-- job done !
|
||||
end architecture RTL;
|
||||
@ -101,12 +101,21 @@ entity LLANDER_TOP is
|
||||
RESET_L : in std_logic;
|
||||
|
||||
-- ref clock in
|
||||
clk_6 : in std_logic;
|
||||
clk_25 : in std_logic;
|
||||
cpu_rom_addr : out std_logic_vector(12 downto 0);
|
||||
cpu_rom_data : in std_logic_vector(7 downto 0);
|
||||
vector_rom_addr : out std_logic_vector(12 downto 0);
|
||||
vector_rom_data : in std_logic_vector(7 downto 0)
|
||||
clk_6 : in std_logic;
|
||||
clk_50 : in std_logic;
|
||||
|
||||
cpu_rom_addr : out std_logic_vector(12 downto 0);
|
||||
cpu_rom_data : in std_logic_vector(7 downto 0);
|
||||
|
||||
vector_rom_addr : out std_logic_vector(12 downto 0);
|
||||
vector_rom_data : in std_logic_vector(7 downto 0);
|
||||
vector_ram_addr : out std_logic_vector( 9 downto 0);
|
||||
vector_ram_dout : in std_logic_vector(15 downto 0);
|
||||
vector_ram_din : out std_logic_vector(15 downto 0);
|
||||
vector_ram_we : out std_logic;
|
||||
vector_ram_cs1 : out std_logic;
|
||||
vector_ram_cs2 : out std_logic
|
||||
|
||||
);
|
||||
end;
|
||||
|
||||
@ -153,7 +162,6 @@ begin
|
||||
LLander: entity work.llander
|
||||
port map(
|
||||
clk_6 => clk_6,
|
||||
clk_25 => clk_25,
|
||||
reset_6_l => reset_6_l,
|
||||
dip => DIP,
|
||||
rot_left_l => rot_left_l,
|
||||
@ -182,33 +190,38 @@ port map(
|
||||
cpu_rom_addr => cpu_rom_addr,
|
||||
cpu_rom_data => cpu_rom_data,
|
||||
vector_rom_addr => vector_rom_addr,
|
||||
vector_rom_data => vector_rom_data
|
||||
vector_rom_data => vector_rom_data,
|
||||
vector_ram_addr => vector_ram_addr,
|
||||
vector_ram_din => vector_ram_din,
|
||||
vector_ram_dout => vector_ram_dout,
|
||||
vector_ram_we => vector_ram_we,
|
||||
vector_ram_cs1 => vector_ram_cs1,
|
||||
vector_ram_cs2 => vector_ram_cs2
|
||||
);
|
||||
|
||||
y_vector_w_offset<= y_vector+100;
|
||||
|
||||
u_DW : entity work.LLANDER_DW
|
||||
u_SB : entity work.LLANDER_SB
|
||||
port map (
|
||||
RESET => reset_6,
|
||||
clk_25 => clk_25,
|
||||
clk_6 => clk_6,
|
||||
RESET => reset_6,
|
||||
clk_vidx2 => clk_50,
|
||||
clk_6 => clk_6,
|
||||
|
||||
X_VECTOR => x_vector,
|
||||
Y_VECTOR => y_vector_w_offset,-- AJS move up y_vector,
|
||||
Z_VECTOR => z_vector,
|
||||
X_VECTOR => x_vector,
|
||||
Y_VECTOR => y_vector_w_offset,-- AJS move up y_vector,
|
||||
Z_VECTOR => z_vector,
|
||||
|
||||
BEAM_ON => beam_on,
|
||||
BEAM_ENA => beam_ena,
|
||||
|
||||
VIDEO_R_OUT => VIDEO_R_OUT,
|
||||
VIDEO_G_OUT => VIDEO_G_OUT,
|
||||
VIDEO_B_OUT => VIDEO_B_OUT,
|
||||
HSYNC_OUT => HSYNC_OUT,
|
||||
VSYNC_OUT => VSYNC_OUT,
|
||||
VID_DE => VGA_DE,
|
||||
VID_HBLANK => VID_HBLANK,
|
||||
VID_VBLANK => VID_VBLANK
|
||||
);
|
||||
BEAM_ON => beam_on,
|
||||
BEAM_ENA => beam_ena,
|
||||
|
||||
VIDEO_R_OUT => VIDEO_R_OUT,
|
||||
VIDEO_G_OUT => VIDEO_G_OUT,
|
||||
VIDEO_B_OUT => VIDEO_B_OUT,
|
||||
HSYNC_OUT => HSYNC_OUT,
|
||||
VSYNC_OUT => VSYNC_OUT,
|
||||
VID_DE => VGA_DE,
|
||||
VID_HBLANK => VID_HBLANK,
|
||||
VID_VBLANK => VID_VBLANK
|
||||
);
|
||||
|
||||
end RTL;
|
||||
|
||||
@ -71,9 +71,16 @@ entity LLANDER_VG is
|
||||
ENA_1_5M_E : in std_logic;
|
||||
RESET_L : in std_logic;
|
||||
CLK_6 : in std_logic;
|
||||
Clk_25 : in std_logic;
|
||||
vector_rom_addr : out std_logic_vector(12 downto 0);
|
||||
vector_rom_data : in std_logic_vector( 7 downto 0)
|
||||
|
||||
vector_rom_addr : out std_logic_vector(12 downto 0);
|
||||
vector_rom_data : in std_logic_vector( 7 downto 0);
|
||||
|
||||
vector_ram_addr : out std_logic_vector( 9 downto 0);
|
||||
vector_ram_din : out std_logic_vector(15 downto 0);
|
||||
vector_ram_dout : in std_logic_vector(15 downto 0);
|
||||
vector_ram_we : out std_logic;
|
||||
vector_ram_cs1 : out std_logic;
|
||||
vector_ram_cs2 : out std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
@ -426,28 +433,36 @@ begin
|
||||
ram_din <= C_DIN;
|
||||
C_DOUT <= memory_dout;
|
||||
|
||||
vector_ram_addr <= am_bus(9 downto 0);
|
||||
vector_ram_din <= ram_din & ram_din;
|
||||
ram_dout_1 <= vector_ram_dout( 7 downto 0);
|
||||
ram_dout_2 <= vector_ram_dout(15 downto 8);
|
||||
vector_ram_we <= not vw_l;
|
||||
vector_ram_cs1 <= not vram1_l;
|
||||
vector_ram_cs2 <= not vram2_l;
|
||||
|
||||
-- vector memory
|
||||
u_vector_ram_1 : entity work.LLANDER_RAM
|
||||
port map (
|
||||
ADDR => am_bus(9 downto 0),
|
||||
DIN => ram_din,
|
||||
DOUT => ram_dout_1,
|
||||
RW_L => vw_l,
|
||||
CS_L => vram1_l,
|
||||
ENA => ena_1_5M,
|
||||
CLK => CLK_6
|
||||
);
|
||||
|
||||
u_vector_ram_2 : entity work.LLANDER_RAM
|
||||
port map (
|
||||
ADDR => am_bus(9 downto 0),
|
||||
DIN => ram_din,
|
||||
DOUT => ram_dout_2,
|
||||
RW_L => vw_l,
|
||||
CS_L => vram2_l,
|
||||
ENA => ena_1_5M,
|
||||
CLK => CLK_6
|
||||
);
|
||||
-- u_vector_ram_1 : entity work.LLANDER_RAM
|
||||
-- port map (
|
||||
-- ADDR => am_bus(9 downto 0),
|
||||
-- DIN => ram_din,
|
||||
-- DOUT => ram_dout_1,
|
||||
-- RW_L => vw_l,
|
||||
-- CS_L => vram1_l,
|
||||
-- ENA => ena_1_5M,
|
||||
-- CLK => CLK_6
|
||||
-- );
|
||||
--
|
||||
-- u_vector_ram_2 : entity work.LLANDER_RAM
|
||||
-- port map (
|
||||
-- ADDR => am_bus(9 downto 0),
|
||||
-- DIN => ram_din,
|
||||
-- DOUT => ram_dout_2,
|
||||
-- RW_L => vw_l,
|
||||
-- CS_L => vram2_l,
|
||||
-- ENA => ena_1_5M,
|
||||
-- CLK => CLK_6
|
||||
-- );
|
||||
|
||||
-- u_vector_rom : entity work.llander_vec_rom
|
||||
-- port map (
|
||||
|
||||
@ -14,11 +14,11 @@
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Copyright (C) 1991-2014 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
@ -102,13 +102,13 @@ module pll (
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.bandwidth_type = "AUTO",
|
||||
altpll_component.clk0_divide_by = 27,
|
||||
altpll_component.clk0_divide_by = 3,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 50,
|
||||
altpll_component.clk0_multiply_by = 8,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.clk1_divide_by = 27,
|
||||
altpll_component.clk1_divide_by = 69,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 25,
|
||||
altpll_component.clk1_multiply_by = 128,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.clk2_divide_by = 9,
|
||||
altpll_component.clk2_duty_cycle = 50,
|
||||
@ -187,14 +187,14 @@ endmodule
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "69"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "72.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.086956"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
@ -222,12 +222,12 @@ endmodule
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "50"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "25"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "24"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "128"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "25.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
@ -281,13 +281,13 @@ endmodule
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "69"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "25"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "128"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
|
||||
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
|
||||
@ -48,6 +48,8 @@ module sdram (
|
||||
|
||||
input [15:1] cpu1_addr,
|
||||
output reg [15:0] cpu1_q,
|
||||
input [15:1] cpu2_addr,
|
||||
output reg [15:0] cpu2_q,
|
||||
|
||||
input port2_req,
|
||||
output reg port2_ack,
|
||||
@ -55,10 +57,7 @@ module sdram (
|
||||
input [23:1] port2_a,
|
||||
input [1:0] port2_ds,
|
||||
input [15:0] port2_d,
|
||||
output [15:0] port2_q,
|
||||
|
||||
input [15:1] snd_addr,
|
||||
output reg [15:0] snd_q
|
||||
output [15:0] port2_q
|
||||
);
|
||||
|
||||
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
|
||||
@ -147,7 +146,7 @@ assign SDRAM_nWE = sd_cmd[0];
|
||||
|
||||
reg [24:1] addr_latch[2];
|
||||
reg [24:1] addr_latch_next[2];
|
||||
reg [15:1] addr_last[2];
|
||||
reg [15:1] addr_last[3];
|
||||
reg [15:1] addr_last2[2];
|
||||
reg [15:0] din_latch[2];
|
||||
reg [1:0] oe_latch;
|
||||
@ -156,12 +155,13 @@ reg [1:0] ds[2];
|
||||
|
||||
localparam PORT_NONE = 2'd0;
|
||||
localparam PORT_CPU1 = 2'd1;
|
||||
localparam PORT_REQ = 2'd2;
|
||||
|
||||
localparam PORT_SND = 2'd1;
|
||||
localparam PORT_CPU2 = 2'd2;
|
||||
localparam PORT_REQ = 2'd3;
|
||||
|
||||
reg [2:0] next_port[2];
|
||||
reg [2:0] port[2];
|
||||
reg port1_state;
|
||||
reg port2_state;
|
||||
|
||||
reg refresh;
|
||||
reg [10:0] refresh_cnt;
|
||||
@ -172,12 +172,15 @@ always @(*) begin
|
||||
if (refresh) begin
|
||||
next_port[0] = PORT_NONE;
|
||||
addr_latch_next[0] = addr_latch[0];
|
||||
end else if (port1_req ^ port1_ack) begin
|
||||
end else if (port1_req ^ port1_state) begin
|
||||
next_port[0] = PORT_REQ;
|
||||
addr_latch_next[0] = { 1'b0, port1_a };
|
||||
end else if (cpu1_addr != addr_last[PORT_CPU1]) begin
|
||||
next_port[0] = PORT_CPU1;
|
||||
addr_latch_next[0] = { 9'd0, cpu1_addr };
|
||||
end else if (cpu2_addr != addr_last[PORT_CPU2]) begin
|
||||
next_port[0] = PORT_CPU2;
|
||||
addr_latch_next[0] = { 9'd0, cpu2_addr };
|
||||
end else begin
|
||||
next_port[0] = PORT_NONE;
|
||||
addr_latch_next[0] = addr_latch[0];
|
||||
@ -186,12 +189,9 @@ end
|
||||
|
||||
// PORT2: bank 2,3
|
||||
always @(*) begin
|
||||
if (port2_req ^ port2_ack) begin
|
||||
if (port2_req ^ port2_state) begin
|
||||
next_port[1] = PORT_REQ;
|
||||
addr_latch_next[1] = { 1'b1, port2_a };
|
||||
end else if (snd_addr != addr_last2[PORT_SND]) begin
|
||||
next_port[1] = PORT_SND;
|
||||
addr_latch_next[1] = { 1'b1, 8'd0, snd_addr };
|
||||
end else begin
|
||||
next_port[1] = PORT_NONE;
|
||||
addr_latch_next[1] = addr_latch[1];
|
||||
@ -239,6 +239,7 @@ always @(posedge clk) begin
|
||||
SDRAM_A <= addr_latch_next[0][22:10];
|
||||
SDRAM_BA <= addr_latch_next[0][24:23];
|
||||
addr_last[next_port[0]] <= addr_latch_next[0][15:1];
|
||||
port1_state <= port1_req;
|
||||
if (next_port[0] == PORT_REQ) begin
|
||||
{ oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
|
||||
ds[0] <= port1_ds;
|
||||
@ -262,6 +263,7 @@ always @(posedge clk) begin
|
||||
SDRAM_A <= addr_latch_next[1][22:10];
|
||||
SDRAM_BA <= addr_latch_next[1][24:23];
|
||||
addr_last2[next_port[1]] <= addr_latch_next[1][15:1];
|
||||
port2_state <= port2_req;
|
||||
if (next_port[1] == PORT_REQ) begin
|
||||
{ oe_latch[1], we_latch[1] } <= { ~port2_we, port2_we };
|
||||
ds[1] <= port2_ds;
|
||||
@ -307,13 +309,13 @@ always @(posedge clk) begin
|
||||
case(port[0])
|
||||
PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
|
||||
PORT_CPU1: begin cpu1_q <= sd_din; end
|
||||
PORT_CPU2: begin cpu2_q <= sd_din; end
|
||||
default: ;
|
||||
endcase;
|
||||
end
|
||||
if(t == STATE_READ1 && oe_latch[1]) begin
|
||||
case(port[1])
|
||||
PORT_REQ: begin port2_q <= sd_din; port2_ack <= port2_req; end
|
||||
PORT_SND: begin snd_q <= sd_din; end
|
||||
default: ;
|
||||
endcase;
|
||||
end
|
||||
|
||||
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Reference in New Issue
Block a user