diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/Arcade-Pong.sv b/Arcade_MiST/Atari Discrete Logic/Pong/Arcade-Pong.sv new file mode 100644 index 00000000..87a1e48d --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/Arcade-Pong.sv @@ -0,0 +1,317 @@ +//============================================================================ +// Arcade: Atari Pong (1972) for MiSTer +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module emu +( + //Master input clock + input CLK_50M, + + //Async reset from top-level module. + //Can be used as initial reset. + input RESET, + + //Must be passed to hps_io module + inout [44:0] HPS_BUS, + + //Base video clock. Usually equals to CLK_SYS. + output VGA_CLK, + + //Multiple resolutions are supported using different VGA_CE rates. + //Must be based on CLK_VIDEO + output VGA_CE, + + output [7:0] VGA_R, + output [7:0] VGA_G, + output [7:0] VGA_B, + output VGA_HS, + output VGA_VS, + output VGA_DE, // = ~(VBlank | HBlank) + + //Base video clock. Usually equals to CLK_SYS. + output HDMI_CLK, + + //Multiple resolutions are supported using different HDMI_CE rates. + //Must be based on CLK_VIDEO + output HDMI_CE, + + output [7:0] HDMI_R, + output [7:0] HDMI_G, + output [7:0] HDMI_B, + output HDMI_HS, + output HDMI_VS, + output HDMI_DE, // = ~(VBlank | HBlank) + output [1:0] HDMI_SL, // scanlines fx + + //Video aspect ratio for HDMI. Most retro systems have ratio 4:3. + output [7:0] HDMI_ARX, + output [7:0] HDMI_ARY, + + output LED_USER, // 1 - ON, 0 - OFF. + + // b[1]: 0 - LED status is system status OR'd with b[0] + // 1 - LED status is controled solely by b[0] + // hint: supply 2'b00 to let the system control the LED. + output [1:0] LED_POWER, + output [1:0] LED_DISK, + + output [15:0] AUDIO_L, + output [15:0] AUDIO_R, + output AUDIO_S // 1 - signed audio samples, 0 - unsigned +); + +assign LED_USER = ioctl_download; +assign LED_DISK = 0; +assign LED_POWER = 0; + +assign HDMI_ARX = status[1] ? 8'd16 : 8'd4; +assign HDMI_ARY = status[1] ? 8'd9 : 8'd3; + +`include "build_id.v" +localparam CONF_STR = { + "A.PONG;;", +// "F,rom;", // allow loading of alternate ROMs + "-;", + "O1,Aspect Ratio,Original,Wide;", +// "O2,Orientation,Vert,Horz;", + "O35,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%,CRT 75%;", + "-;", + "O8,Max Points,11,15;", +// "OA,Language,English,Spanish;", +// "OB,Body Fault,On,Off;", + //"OC,Cabinet,Upright,Cocktail;", +// "ODE,Difficulty,L1,L2,L3,L4;", + "-;", + "R0,Reset;", + "J1,Serve,Paddle Left,Paddle Right,Start 1P,Start 2P;", + "V,v2",`BUILD_DATE +}; +wire [7:0] m_dip = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, status[8]}; +//////////////////// CLOCKS /////////////////// + +wire clk_sys, clk_vid; +wire pll_locked; + +pll pll +( + .refclk(CLK_50M), + .rst(0), + .outclk_0(clk_sys), // 7.159mhz + .outclk_1(clk_vid), // 28.636mhz + .locked(pll_locked) +); + +/////////////////////////////////////////////////// + +wire [31:0] status; +wire [1:0] buttons; +wire forced_scandoubler; + +wire ioctl_download; +wire ioctl_wr; +wire [24:0] ioctl_addr; +wire [7:0] ioctl_dout; + +wire [10:0] ps2_key; + +wire [15:0] joystick_0, joystick_1; +wire [15:0] joy = joystick_0 ; +wire [15:0] joy2 = joystick_1; +wire [15:0] joystick_analog_0; +wire [15:0] joystick_analog_1; + +hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io +( + .clk_sys(clk_sys), + .HPS_BUS(HPS_BUS), + + .conf_str(CONF_STR), + + .buttons(buttons), + .status(status), + .forced_scandoubler(forced_scandoubler), + + .ioctl_download(ioctl_download), + .ioctl_wr(ioctl_wr), + .ioctl_addr(ioctl_addr), + .ioctl_dout(ioctl_dout), + + .joystick_0(joystick_0), + .joystick_1(joystick_1), + .joystick_analog_0(joystick_analog_0), + .joystick_analog_1(joystick_analog_1), + .ps2_key(ps2_key) +); + +wire pressed = ps2_key[9]; +wire [8:0] code = ps2_key[8:0]; +always @(posedge clk_sys) begin + reg old_state; + old_state <= ps2_key[10]; + + if(old_state != ps2_key[10]) begin + casex(code) + 'hX75: btn_up <= pressed; // up + 'hX72: btn_down <= pressed; // down + 'hX6B: btn_left <= pressed; // left + 'hX74: btn_right <= pressed; // right + 'h014: btn_fire <= pressed; // ctrl + 'h026: btn_paddle_left <= pressed; // lalt + 'h029: btn_paddle_right<= pressed; // space + + // JPAC/IPAC/MAME Style Codes + 'h005: btn_one_player <= pressed; // F1 + 'h006: btn_two_players <= pressed; // F2 + 'h016: btn_start_1 <= pressed; // 1 + 'h01E: btn_start_2 <= pressed; // 2 + 'h02E: btn_coin_1 <= pressed; // 5 + 'h036: btn_coin_2 <= pressed; // 6 + 'h02D: btn_up_2 <= pressed; // R + 'h02B: btn_down_2 <= pressed; // F + 'h023: btn_left_2 <= pressed; // D + 'h034: btn_right_2 <= pressed; // G + 'h01C: btn_fire_2 <= pressed; // A + 'h01B: btn_paddle_left_2 <= pressed; // S + 'h015: btn_paddle_right_2 <= pressed; // Q + 'h02C: btn_test <= pressed; // T + endcase + end +end + +reg btn_up = 0; +reg btn_down = 0; +reg btn_right = 0; +reg btn_left = 0; +reg btn_fire = 0; +reg btn_paddle_left= 0; +reg btn_paddle_right= 0; +reg btn_one_player = 0; +reg btn_two_players = 0; + +reg btn_start_1=0; +reg btn_start_2=0; +reg btn_coin_1=0; +reg btn_coin_2=0; + +reg btn_up_2=0; +reg btn_down_2=0; +reg btn_left_2=0; +reg btn_right_2=0; +reg btn_fire_2 = 0; +reg btn_paddle_left_2= 0; +reg btn_paddle_right_2= 0; +reg btn_test=0; + + +wire m_up = btn_up | joy[3]; +wire m_down = btn_down | joy[2]; +wire m_left = btn_left | joy[1]; +wire m_right = btn_right | joy[0]; + +wire m_fire = btn_fire | joy[4]; +wire m_paddle_left = btn_paddle_left | joy[5]; +wire m_paddle_right = btn_paddle_right | joy[6]; + +wire m_up_2 = btn_up_2 | joy2[3]; +wire m_down_2 = btn_down_2 | joy2[2]; +wire m_left_2 = btn_left_2 | joy2[1]; +wire m_right_2 = btn_right_2 | joy2[0]; + +wire m_fire_2 = btn_fire_2 | joy2[4]; +wire m_paddle_left_2 = btn_paddle_left_2 | joy2[5]; +wire m_paddle_right_2 = btn_paddle_right_2 | joy2[6]; + +wire m_start1 = btn_one_player | joy[7] | joy2[7]; +wire m_start2 = btn_two_players | joy[8] | joy2[8]; +wire m_coin = m_start1 | m_start2; + +wire hblank, vblank; +//wire ce_vid = clk_sys; +wire hs, vs; +wire [3:0] r,g, b; + +/* +reg ce_pix; +always @(posedge clk_48m) begin + reg old_clk; + + old_clk <= clk_sys; + ce_pix <= old_clk & ~clk_sys; +end +*/ + +arcade_fx #(375, 12) arcade_video +( + .*, + + .clk_video(clk_vid), + .ce_pix(clk_sys), + + .RGB_in({r,g,b}), + .HBlank(hblank), + .VBlank(vblank), + .HSync(hs), + .VSync(vs), + + .fx(status[5:3]) + //.no_rotate(status[2]) +); + +wire audio; +assign AUDIO_L = {audio, 15'd0}; +assign AUDIO_R = AUDIO_L; +assign AUDIO_S = 0; + +reg initReset_n = 0; +always @(posedge clk_sys) begin + reg old_download = 0; + old_download <= ioctl_download; + + if(old_download & ~ioctl_download) initReset_n <= 1; +end + +wire [7:0] paddle1_vpos; +assign paddle1_vpos = joystick_analog_0[15:8] + 8'h80; + +wire [7:0] paddle2_vpos; +assign paddle2_vpos = joystick_analog_1[15:8] + 8'h80; + +pong pong +( + .mclk(CLK_50M), + .clk7_159(clk_sys), +// .reset(~initReset_n|RESET | status[0] | buttons[1]), + .coin_sw(m_coin|btn_coin_1|btn_coin_2), + .dip_sw(m_dip), + .paddle1_vpos(paddle1_vpos), + .paddle2_vpos(paddle2_vpos), + + .r(r), + .g(g), + .b(b), + .hsync(hs), + .vsync(vs), + .hblank(hblank), + .vblank(vblank), + + .sound_out(audio) +); + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/LICENSE b/Arcade_MiST/Atari Discrete Logic/Pong/LICENSE new file mode 100644 index 00000000..ae33849e --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/LICENSE @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2019 Richard Eng + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/Pong.qpf b/Arcade_MiST/Atari Discrete Logic/Pong/Pong.qpf new file mode 100644 index 00000000..fd86c72f --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/Pong.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "Pong" diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/Pong.qsf b/Arcade_MiST/Atari Discrete Logic/Pong/Pong.qsf new file mode 100644 index 00000000..666ec185 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/Pong.qsf @@ -0,0 +1,193 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition +# Date created = 15:43:32 October 09, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Pong_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Pong_Mist.sv +set_global_assignment -name VERILOG_FILE rtl/pong.v +set_global_assignment -name VERILOG_FILE rtl/vsync.v +set_global_assignment -name VERILOG_FILE rtl/video.v +set_global_assignment -name VERILOG_FILE rtl/vcounter.v +set_global_assignment -name VERILOG_FILE rtl/timer.v +set_global_assignment -name VERILOG_FILE rtl/srlatch.v +set_global_assignment -name VERILOG_FILE rtl/sound.v +set_global_assignment -name VERILOG_FILE rtl/score_segments_to_video.v +set_global_assignment -name VERILOG_FILE rtl/score_counters_to_segments.v +set_global_assignment -name VERILOG_FILE rtl/score_counters.v +set_global_assignment -name VERILOG_FILE rtl/score.v +set_global_assignment -name VERILOG_FILE rtl/png_jkff.v +set_global_assignment -name VERILOG_FILE rtl/png_dff.v +set_global_assignment -name VERILOG_FILE rtl/paddles.v +set_global_assignment -name VERILOG_FILE rtl/paddle.v +set_global_assignment -name VERILOG_FILE rtl/net.v +set_global_assignment -name VERILOG_FILE rtl/hsync.v +set_global_assignment -name VERILOG_FILE rtl/hcounter.v +set_global_assignment -name VERILOG_FILE rtl/game_control.v +set_global_assignment -name VERILOG_FILE rtl/dm9316.v +set_global_assignment -name VERILOG_FILE rtl/ball_vertical_move.v +set_global_assignment -name VERILOG_FILE rtl/ball_vertical_counter.v +set_global_assignment -name VERILOG_FILE rtl/ball_vertical.v +set_global_assignment -name VERILOG_FILE rtl/ball_horizontal_video.v +set_global_assignment -name VERILOG_FILE rtl/ball_horizontal_move.v +set_global_assignment -name VERILOG_FILE rtl/ball_horizontal_direction.v +set_global_assignment -name VERILOG_FILE rtl/ball_horizontal.v +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name VERILOG_FILE rtl/ttl/ls153.v +set_global_assignment -name VERILOG_FILE rtl/ttl/ls107.v +set_global_assignment -name VERILOG_FILE rtl/ttl/ls93.v +set_global_assignment -name VERILOG_FILE rtl/ttl/ls90.v +set_global_assignment -name VERILOG_FILE rtl/ttl/ls86.v +set_global_assignment -name VERILOG_FILE rtl/ttl/ls83.v +set_global_assignment -name VERILOG_FILE rtl/ttl/ls74.v +set_global_assignment -name VERILOG_FILE rtl/ttl/ls50.v +set_global_assignment -name VERILOG_FILE rtl/ttl/ls48.v +set_global_assignment -name VERILOG_FILE rtl/ttl/ls30.v +set_global_assignment -name VERILOG_FILE rtl/ttl/ls27.v +set_global_assignment -name VERILOG_FILE rtl/ttl/ls25.v +set_global_assignment -name VERILOG_FILE rtl/ttl/ls20.v +set_global_assignment -name VERILOG_FILE rtl/ttl/ls10.v +set_global_assignment -name VERILOG_FILE rtl/ttl/ls04.v +set_global_assignment -name VERILOG_FILE rtl/ttl/ls02.v +set_global_assignment -name VERILOG_FILE rtl/ttl/ls00.v +set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name TOP_LEVEL_ENTITY Pong_Mist +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ------------------ +# start ENTITY(pong) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(pong) +# ---------------- +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/README.txt b/Arcade_MiST/Atari Discrete Logic/Pong/README.txt new file mode 100644 index 00000000..d4547814 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/README.txt @@ -0,0 +1,72 @@ +***************************************************************** +** Arcade: Atari Pong (1972) ** +** A Verilog implementation based on the original schematics. ** +***************************************************************** + + Written by: Richard Eng + email: engric@gmail.com + twitter: @richard_eng + www: retrobits.no + git: github.com/Eicar + +--------- +Changelog +--------- + 2019-10-06 Initial release + +------ +Inputs +------ + +MAME/IPAC/JPAC Style Keyboard inputs: + 5 : Coin 1 + 6 : Coin 2 + ++Analog joysticks for paddles (player 1+2) + +--------- +File list +--------- + +sys/* GPL-2, Copyright (C) 2019 Sorgelig +rtl/* MIT, Copyright (c) 2019 Richard Eng + +--- +Q&A +--- + +-Q: How accurate is this implementation? + A: This implementation is based on the original Atari schematics. However, the + original hardware consists of both digital (sync+async logic) and analog circuits. The analog circuits + are simulated using digital logic. All signals should be accurate to the system clock edges (7.159MHz). + +-Q: Help! I'm unable to move the paddles using the keyboard! + A: Currently only analog joystick controls are supported. + +-Q: Help! I'm unable to move the paddle to the top of the screen! + A: This is not a bug. The original hardware design did not allow for this to happen. + +-Q: The core "reset" does not seem to work + A: This is true. The original Pong hardware did not support a global "reset" signal. + I might add support for this in the future. + +-Q: Can you please add support for XXX! + A: I will probably not add features not present in the original game. + This core is all about accuracy. + +-Q: Your HDL code looks like crap! + A: You are probably right about that! I have a 20+ years software developer background but HDL is + pretty new to me. Hopefully I will get better at it :) + +-Q: I've found a bug! + A: Please let me know about it! I really want this core to be as accurate as possible. + I will make sure you will get credit for it! + +-Q: This core is awesome! How can I make a donation? + A: All donations are welcome and extremely appreciated! Donations will make it possible + for me to spend more time on writing new cores. + + Donations can be sent to: paypal.me/riceng + + +-End of file diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/clean.bat b/Arcade_MiST/Atari Discrete Logic/Pong/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/Pong_Mist.sv b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/Pong_Mist.sv new file mode 100644 index 00000000..f0121f81 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/Pong_Mist.sv @@ -0,0 +1,128 @@ + +module Pong_Mist( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Pong;;", + "T1,Coin;", + "O2,Max Points,11,15;", + "O34,Scanlines,Off,25%,50%,75%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +assign LED = 1; +assign AUDIO_R = AUDIO_L; + +wire clock_50, clock_7p159; +wire pll_locked; +pll pll( + .inclk0(CLOCK_27), + .areset(status[0] | status[6] | buttons[1]), + .c0(clock_50), + .c1(clock_7p159), + .locked(pll_locked) + ); + + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [15:0] joystick_analog_0; +wire [15:0] joystick_analog_1; +wire scandoublerD; +wire ypbpr; +wire audio; +wire hs, vs; +wire blankn = ~(hb | vb); +wire hb, vb; +wire [3:0] r,b,g; + +wire [7:0] paddle1_vpos; +assign paddle1_vpos = joystick_analog_0[15:8] + 8'h80; +wire [7:0] paddle2_vpos; +assign paddle2_vpos = joystick_analog_1[15:8] + 8'h80; + + +pong pong( + .mclk(clock_50), + .clk7_159(clock_7p159), + .coin_sw(status[1]), + .dip_sw({"0000000",status[2]}), + .paddle1_vpos(paddle1_vpos), + .paddle2_vpos(paddle2_vpos), + .r(r), + .g(g), + .b(b), + .hsync(hs), + .vsync(vs), + .hblank(hb), + .vblank(vb), + .sound_out(audio) +); + +mist_video #(.COLOR_DEPTH(4)) mist_video( + .clk_sys(clock_50), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(blankn ? r : 0), + .G(blankn ? g : 0), + .B(blankn ? b : 0), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .ce_divider(1), + .scandoubler_disable(scandoublerD), + .scanlines(status[4:3]), + .ypbpr(ypbpr) + ); + +user_io #( + .STRLEN(($size(CONF_STR)>>3))) +user_io( + .clk_sys (clock_50 ), + .conf_str (CONF_STR ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable (scandoublerD), + .ypbpr (ypbpr ), + .joystick_analog_0(joystick_analog_0), + .joystick_analog_1(joystick_analog_1), + .status (status ) + ); + +dac #(4)dac( + .clk_i(clock_50), + .res_n_i({4{audio}}), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ball_horizontal.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ball_horizontal.v new file mode 100644 index 00000000..023e6776 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ball_horizontal.v @@ -0,0 +1,42 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + Pong - Ball Horizontal Circuit + ------------------------------ +*/ +`default_nettype none + +module ball_horizontal +( + input wire _h256, vreset, rst_speed, hit_sound, _hit2, sc, attract, _hit1, _hblank, clk7_159, _attract, serve, + output wire l, r, _hvid +); + +wire move, aa, ba; +ball_horizontal_move ball_hor_mov(_h256, vreset, rst_speed, hit_sound, move); +ball_horizontal_direction ball_hor_dir(move, _hit2, sc, attract, _hit1, l, r, aa, ba); +ball_horizontal_video ball_hor_video(aa, ba, _hblank, clk7_159, _attract, serve, _hvid); + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ball_horizontal_direction.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ball_horizontal_direction.v new file mode 100644 index 00000000..fa412476 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ball_horizontal_direction.v @@ -0,0 +1,50 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + Pong - Ball Horizontal Direction Circuit + ---------------------------------------- +*/ +`default_nettype none + +module ball_horizontal_direction +( + input wire move, _hit2, sc, attract, _hit1, + output wire l, r, aa, ba +); + +wire c1d_to_d1a; +ls00 c1d(sc, attract, c1d_to_d1a); + +wire d1a_to_h3b; +ls04 d1a(c1d_to_d1a, d1a_to_h3b); + +ls74 h3b(d1a_to_h3b, r, _hit1, _hit2, l, r); + +wire h4d_to_h4c; +ls00 h4d(move, l, h4d_to_h4c); +ls00 h4b(move, r, ba); +ls00 h4c(h4d_to_h4c, ba, aa); + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ball_horizontal_move.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ball_horizontal_move.v new file mode 100644 index 00000000..6bf15422 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ball_horizontal_move.v @@ -0,0 +1,72 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + Pong - Ball Horizontal Move Circuit + ----------------------------------- +*/ +`default_nettype none + +module ball_horizontal_move +( + input wire _h256, vreset, rst_speed, hit_sound, + output wire move +); + +wire e1d_to_f1; +ls00 e1d(e1c_out, hit_sound, e1d_to_f1); + +wire unused2, unused3, qc, qd; +ls93 f1(e1d_to_f1, 1'b0, rst_speed, rst_speed, unused2, unused3, qc, qd); + +wire e1c_out; +ls00 e1c(qc, qd, e1c_out); + +wire g1d_to_h1a; +ls02 g1d(qc, qd, g1d_to_h1a); + +wire h1a_out; +ls00 h1a(g1d_to_h1a, g1d_to_h1a, h1a_out); + +wire h1d_to_h1c; +ls00 h1d(e1c_out, h1a_out, h1d_to_h1c); + +wire h1c_to_h2b; +ls00 h1c(vreset, h1d_to_h1c, h1c_to_h2b); + +wire h1b_to_h2a; +ls00 h1b(h1a_out, vreset, h1b_to_h2a); + +wire g1c_out; +ls02 g1c(_h256, vreset, g1c_out); + +wire unused4, h2b_out; +ls107 h2b(g1c_out, h1c_to_h2b, 1'b1, move, h2b_out, unused4); + +wire unused5, h2a_to_h4a; +ls107 h2a(g1c_out, h1b_to_h2a, h2b_out, 1'b0, h2a_to_h4a, unused5); + +ls00 h4a(h2b_out, h2a_to_h4a, move); + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ball_horizontal_video.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ball_horizontal_video.v new file mode 100644 index 00000000..c73eaef0 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ball_horizontal_video.v @@ -0,0 +1,52 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + Pong - Ball Horizontal Video Circuit + ------------------------------------ +*/ +`default_nettype none + +module ball_horizontal_video +( + input wire aa, ba, _hblank, clk7_159, _attract, serve, + output wire _hvid +); + +wire _clr; +ls00 e1b(_attract, serve, _clr); + +wire /* verilator lint_off UNUSED */ qa, qb /* verilator lint_on UNUSED */, qc, qd, g7_carry, h7_carry; +dm9316 g7(clk7_159, _clr, aa, ba, 1'b0, 1'b1, _load, 1'b1, _hblank, qa, qb, qc, qd, g7_carry); +wire /* verilator lint_off UNUSED */ qa2, qb2, qc2, qd2 /* verilator lint_on UNUSED */; +dm9316 h7(clk7_159, _clr, 1'b0, 1'b0, 1'b0, 1'b1, _load, g7_carry, 1'b1, qa2, qb2, qc2, qd2, h7_carry); + +wire unused, g6b_out; +ls107 g6b(h7_carry, _clr, 1'b1, 1'b1, g6b_out, unused); + +wire _load; +ls10 g5c(h7_carry, g7_carry, g6b_out, _load); +ls20 h6b(qc, qd, h7_carry, g6b_out, _hvid); + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ball_vertical.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ball_vertical.v new file mode 100644 index 00000000..f86d33b8 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ball_vertical.v @@ -0,0 +1,41 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + Pong - Ball Vertical Circuit + ---------------------------- +*/ +`default_nettype none + +module ball_vertical +( + input wire _hsync, _vblank, vblank, _hit, d1, _h256, d2, h256, c1, c2, b2, b1, attract, hit, + output wire vball16, vball32, vball240, _vvid, vvid +); + +wire ab, bb, cb, db; +ball_vertical_move bal_vert_move(vvid, vblank, _hit, d1, _h256, d2, h256, c1, c2, b2, b1, attract, hit, ab, bb, cb, db); +ball_vertical_counter bal_vert(_hsync, _vblank, ab, bb, cb, db, vball16, vball32, vball240, _vvid, vvid); + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ball_vertical_counter.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ball_vertical_counter.v new file mode 100644 index 00000000..71bc0f4f --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ball_vertical_counter.v @@ -0,0 +1,56 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + Pong - Ball Vertical Counter Circuit + ------------------------------------ +*/ +`default_nettype none + +module ball_vertical_counter +( + input wire _hsync, _vblank, ab, bb, cb, db, + output wire vball16, vball32, vball240, _vvid, vvid +); + +wire b3_carry, /* verilator lint_off UNUSED */ b3qa, b3qb /* verilator lint_on UNUSED */, b3qc, b3qd; +dm9316 b3(_hsync, 1'b1, ab, bb, cb, db, b2b_out, 1'b1, _vblank, b3qa, b3qb, b3qc, b3qd, b3_carry); + +wire a3_carry, a3qa, a3qb, /* verilator lint_off UNUSED */ a3qc, a3qd /* verilator lint_on UNUSED */; +dm9316 a3(_hsync, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, b2b_out, b3_carry, 1'b1, a3qa, a3qb, a3qc, a3qd, a3_carry); + +wire b2b_out; +ls00 b2b(a3_carry, b3_carry, b2b_out); + +wire e2b_out; +ls10 e2b(a3_carry, b3qd, b3qc, e2b_out); + +ls02 d2d(e2b_out, e2b_out, vvid); + +assign _vvid = e2b_out; +assign vball240 = a3_carry; +assign vball16 = a3qa; +assign vball32 = a3qb; + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ball_vertical_move.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ball_vertical_move.v new file mode 100644 index 00000000..7716391b --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ball_vertical_move.v @@ -0,0 +1,76 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + Pong - Ball Vertical Move Circuit + --------------------------------- +*/ +`default_nettype none + +module ball_vertical_move +( + input wire vvid, vblank, _hit, d1, _h256, d2, h256, c1, c2, b2, b1, attract, hit, + output wire ab, bb, cb, db +); + +wire b6b_out; +ls50 b6b(_h256, d1, d2, h256, b6b_out); + +wire a6b_out; +ls50 a6b(_h256, c1, c2, h256, a6b_out); + +wire a6a_out; +ls50 a6a(b2, _h256, h256, b1, a6a_out); + +wire d1c_out; +ls04 d1c(attract, d1c_out); + +wire b5a_q, b5a__q; +ls74 b5a(hit, b6b_out, d1c_out, 1'b1, b5a_q, b5a__q); + +wire a5a_q, /* verilator lint_off UNUSED */ a5a__q /* verilator lint_on UNUSED */; +ls74 a5a(hit, a6b_out, d1c_out, 1'b1, a5a_q, a5a__q); + +wire a5b_q, /* verilator lint_off UNUSED */ a5b__q /* verilator lint_on UNUSED */; +ls74 a5b(hit, a6a_out, d1c_out, 1'b1, a5b_q, a5b__q); + +wire a2a_q, a2a__q; +ls107 a2a(vblank, _hit, vvid, vvid, a2a_q, a2a__q); + +wire b6a_out; +ls50 b6a(a2a_q, b5a_q, a2a__q, b5a__q, b6a_out); + +wire a4b_out; +ls86 a4b(a2a_q, a5a_q, a4b_out); + +wire a4c_out; +ls86 a4c(a5b_q, a2a_q, a4c_out); + +wire c4a_out; +ls10 c4a(b6a_out, b6a_out, b6a_out, c4a_out); + +wire /* verilator lint_off UNUSED */ b4_c4 /* verilator lint_on UNUSED */; +ls83 b4(a4c_out, a4b_out, b6a_out, 1'b0, c4a_out, 1'b1, 1'b1, 1'b0, 1'b0, ab, bb, cb, db, b4_c4); + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/build_id.tcl b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/dm9316.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/dm9316.v new file mode 100644 index 00000000..52f9b976 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/dm9316.v @@ -0,0 +1,98 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + DM9316 + ------ + Synchronous 4-Bit Counters + + Pinout + ------ + _______ + | | + _clr -| 1 16 |- VCC + clk -| 2 15 |- carry + a -| 3 14 |- qa + b -| 4 13 |- qb + c -| 5 12 |- qc + d -| 6 11 |- qd + en_p -| 7 10 |- en_t + GND -| 8 9 |- _load + |_______| +*/ +`default_nettype none + +module dm9316 +( + input wire clk, _clr, a, b, c, d, _load, en_p, en_t, + output wire qa, qb, qc, qd, carry +); + +wire _clk, load, _en_p, _en_t; + +not(_clk, clk); +not(load, _load); +not(_en_p, en_p); +not(_en_t, en_t); + +wire a1; +nor(a1, load, _en_p, _en_t); + +wire b1, b2, bb3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14, b15, b16; +and(b1, qa, a1); +and(b2, load, c2); +and(bb3, a, load); +and(b4, a1, _qa); +and(b5, qb, qa, a1); +and(b6, load, c4); +and(b7, b, load); +and(b8, a1, qa, _qb); +and(b9, qc, qa, qb, a1); +and(b10, load, c6); +and(b11, c, load); +and(b12, a1, qa, qb, _qc); +and(b13, qd, qa, qb, qc, a1); +and(b14, load, c8); +and(b15, d, load); +and(b16, a1, qa, qb, qc, _qd); + +wire c1, c2, c3, c4, c5, c6, c7, c8; +nor(c1, b1, b2); +nor(c2, bb3, b4); +nor(c3, b5, b6); +nor(c4, b7, b8); +nor(c5, b9, b10); +nor(c6, b11, b12); +nor(c7, b13, b14); +nor(c8, b15, b16); + +nor(carry, _qd, _qc, _qb, _qa, _en_t); + +wire _qa, _qb, _qc, _qd; +png_jkff ff1(_clk, ~c2, ~c1, 1'b1, _clr, qa, _qa); +png_jkff ff2(_clk, ~c4, ~c3, 1'b1, _clr, qb, _qb); +png_jkff ff3(_clk, ~c6, ~c5, 1'b1, _clr, qc, _qc); +png_jkff ff4(_clk, ~c8, ~c7, 1'b1, _clr, qd, _qd); + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/game_control.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/game_control.v new file mode 100644 index 00000000..e6f807d9 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/game_control.v @@ -0,0 +1,78 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + Pong - Game Control Circuit + --------------------------- +*/ +`default_nettype none + +module game_control +( + input wire clk7_159, _miss, stop_g, pad1, coin_sw, + output wire _srst, srst, rst_speed, attract, _attract, serve, _serve +); + +wire e6b_out; +ls00 e6b(_srst, _miss, e6b_out); +assign rst_speed = e6b_out; + +wire e6a_out; +ls00 e6a(e6b_out, e6b_out, e6a_out); + +wire f4_out; +timer #(7_159_000, 1700) f4(clk7_159, e6a_out, f4_out); + +wire _run; +wire e5a_out; +ls27 e5a(_run, stop_g, f4_out, e5a_out); +assign _run = ~running; + +ls74 b5b(pad1, e5a_out, e5a_out, 1'b1, _serve, serve); + +ls02 d2a(stop_g, _run, _attract); +ls04 d1b(_attract, attract); + +assign srst = coin_sw; +assign _srst = ~srst; + +reg running, coin_sw_old, stop_g_old; + +initial begin + running = 1'b0; + coin_sw_old = 1'b0; + stop_g_old = 1'b0; +end + +always @(negedge clk7_159) begin + if (coin_sw_old == 1'b0 && coin_sw == 1'b1) begin + running <= 1'b1; + end else if (stop_g_old == 1'b0 && stop_g == 1'b1) begin + running <= 1'b0; + end + coin_sw_old <= coin_sw; + stop_g_old <= stop_g; +end + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/hcounter.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/hcounter.v new file mode 100644 index 00000000..b55b54cf --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/hcounter.v @@ -0,0 +1,73 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + Pong - Horizontal Counter Circuit + --------------------------------- +*/ +`default_nettype none + +module hcounter +( + input wire clk7_159, + output wire h1, h2, h4, h8, h16, h32, h64, h128, h256, _h256, hreset, _hreset +); + +/* +wire f7_to_e7b; + +ls93 f8(clk7_159, , hreset, hreset, h1, h2, h4, h8); +ls93 f9(h8, , hreset, hreset, h16, h32, h64, h128); +ls107 f6b(h128, _hreset, 1'b1, 1'b1, h256, _h256); +ls30 f7(h256, 1'b1, 1'b1, 1'b1, h4, h2, h128, h64, f7_to_e7b); +ls74 e7b(clk7_159, f7_to_e7b, 1'b1, 1'b1, _hreset, hreset); +*/ + +/* verilator lint_off UNOPTFLAT */ +reg [8:0] hcnt; +/* verilator lint_on UNOPTFLAT */ + +initial hcnt = 9'd0; + +assign { _h256, h256, h128, h64, h32, h16, h8, h4, h2, h1 } = { ~hcnt[8], hcnt[8], hcnt[7], hcnt[6], hcnt[5], hcnt[4], hcnt[3], hcnt[2], hcnt[1], hcnt[0] }; + +always @(negedge clk7_159 or posedge hreset) begin + if (hreset) + hcnt <= 9'd0; + else + hcnt <= hcnt + 1'b1; +end + +reg rst; + +initial rst = 1'b0; + +always @(posedge clk7_159) begin + rst <= (hcnt == 9'd454); +end + +assign hreset = rst; +assign _hreset = ~hreset; + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/hsync.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/hsync.v new file mode 100644 index 00000000..541c623d --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/hsync.v @@ -0,0 +1,42 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + Pong - Horizontal Sync Circuit + ------------------------------ +*/ +`default_nettype none + +module hsync +( + input wire mclk, clk7_159, _hreset, h16, h32, h64, + output wire hblank, _hblank, _hsync +); + +// hack-hack: "and" with clock to simulate propagation delay of ripple counter... +srlatch h5bc(mclk, ~(h16 & h64 & clk7_159), _hreset, _hblank, hblank); +assign _hsync = ~(hblank & h32); + +endmodule + diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/net.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/net.v new file mode 100644 index 00000000..1f59e111 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/net.v @@ -0,0 +1,43 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + Pong - The Net Circuit + ---------------------- +*/ +`default_nettype none + +module net +( + input wire clk7_159, vblank, v4, h256, _h256, + output wire net +); + +wire unused, f3b_to_g3b, g3b_to_g2b; + +ls107 f3b(clk7_159, 1'b1, h256, _h256, unused, f3b_to_g3b); +ls00 g3b(h256, f3b_to_g3b, g3b_to_g2b); +ls27 g2b(vblank, v4, g3b_to_g2b, net); + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/paddle.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/paddle.v new file mode 100644 index 00000000..4e156696 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/paddle.v @@ -0,0 +1,82 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + Pong - Paddle Circuit + --------------------- +*/ +`default_nettype none + +module paddle +( + input wire [7:0] paddle_vpos, input wire _hsync, _v256, + output wire b, c, d, _vpad +); + +wire b7b_c_out; +ls00 b7b_c(_hsync, a7a_b_out, b7b_c_out); + +wire a8_9_qa, a8_9_qb, a8_9_qc, a8_9_qd; +ls93 a8_9(b7b_c_out, 1'b0, a9_b9_out, a9_b9_out, a8_9_qa, a8_9_qb, a8_9_qc, a8_9_qd); + +wire a7a_b_out; +ls20 a7a_b(a8_9_qa, a8_9_qb, a8_9_qc, a8_9_qd, a7a_b_out); + +wire a9_b9_out; + +wire c9a_b_out; +ls04 c9a_b(a9_b9_out, c9a_b_out); + +wire b7a_d_out; +ls00 b7a_d(c9a_b_out, a7a_b_out, b7a_d_out); + +assign b = a8_9_qb; +assign c = a8_9_qc; +assign d = a8_9_qd; +assign _vpad = b7a_d_out; + +assign a9_b9_out = trigger; + +// Simulate 555 timer to position paddle vertical position +reg [8:0] counter; +reg trigger; + +always @(negedge _hsync) begin + if (counter > 9'd0) begin + counter <= counter - 9'd1; + if (counter == 9'd1) begin + trigger <= 1'b0; + end + end else if (counter == 9'd0 && !_v256) begin + // 22 full range + // 38 limited (authentic) + counter <= ( { 1'b0, paddle_vpos } + 9'd5 + 9'd16) < 9'd38 ? 9'd38 : + ( { 1'b0, paddle_vpos } + 9'd5 + 9'd16) > 9'd261 ? 9'd261 : + ( { 1'b0, paddle_vpos } + 9'd5 + 9'd16); // 261-256=5 lines + 16 vblank lines + trigger <= 1'b1; + + end +end + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/paddles.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/paddles.v new file mode 100644 index 00000000..30f97a9b --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/paddles.v @@ -0,0 +1,60 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + Pong - Paddles Circuit + ---------------------- +*/ +`default_nettype none + +module paddles +( + input wire [7:0] paddle1_vpos, input wire [7:0] paddle2_vpos, input wire _hsync, _v256, _attract, h4, h128, h256, _h256, + output wire b1, c1, d1, pad1, b2, c2, d2, pad2 +); + +wire _vpad1; +paddle p1(paddle1_vpos, _hsync, _v256, b1, c1, d1, _vpad1); + +wire _vpad2; +paddle p2(paddle2_vpos, _hsync, _v256, b2, c2, d2, _vpad2); + +/* verilator lint_off UNUSED */ +wire h3a_q; +/* verilator lint_on UNUSED */ +wire h3a__q; +ls74 h3a(h4, h128, 1'b1, _attract, h3a_q, h3a__q); + +wire g3c_out; +ls00 g3c(h128, h3a__q, g3c_out); + +wire g2c_out; +ls27 g2c(_vpad1, h256, g3c_out, g2c_out); +assign pad1 = g2c_out; + +wire g2a_out; +ls27 g2a(_vpad2, _h256, g3c_out, g2a_out); +assign pad2 = g2a_out; + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/pll.qip b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/pll.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/pll.v new file mode 100644 index 00000000..f9fd79bc --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/pll.v @@ -0,0 +1,348 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.4 Build 182 03/12/2014 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2014 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + c1, + locked); + + input areset; + input inclk0; + output c0; + output c1; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [4:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire6 = 1'h0; + wire [0:0] sub_wire3 = sub_wire0[0:0]; + wire [1:1] sub_wire1 = sub_wire0[1:1]; + wire c1 = sub_wire1; + wire locked = sub_wire2; + wire c0 = sub_wire3; + wire sub_wire4 = inclk0; + wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire5), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 27, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 25, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 525, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 139, + altpll_component.clk1_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "525" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "7.148571" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "50" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "139" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "7.15900000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "525" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "139" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/png_dff.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/png_dff.v new file mode 100644 index 00000000..26964ae5 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/png_dff.v @@ -0,0 +1,50 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + Positive-Edge-Triggered D Flip-Flop with + Preset, Clear and Complementary Outputs +*/ +`default_nettype none + +module png_dff +( + input wire clk, d, _clr, _pre, + output reg q, + output wire _q +); + +always @(posedge clk or negedge _clr or negedge _pre) begin + if (_clr == 1'b0) begin + q <= 1'b0; + end else if (_pre == 1'b0) begin + q <= 1'b1; + end else begin + q <= d; + end +end + +assign _q = ~q; + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/png_jkff.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/png_jkff.v new file mode 100644 index 00000000..6eeeaad5 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/png_jkff.v @@ -0,0 +1,56 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + JK Flip-Flop with Set and Clear +*/ +`default_nettype none + +module png_jkff +( + input wire _clk, j, k, _set, _clr, + output reg q, + output wire _q +); + +initial q = 1'b0; + +always @(negedge _clk or negedge _clr or negedge _set) begin + if (_clr == 1'b0) begin + q <= 1'b0; + end else if (_set == 1'b0) begin + q <= 1'b1; + end else begin + case ({j, k}) + 2'b00: q <= q; + 2'b01: q <= 1'b0; + 2'b10: q <= 1'b1; + 2'b11: q <= ~q; + endcase + end +end + +assign _q = ~q; + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/pong.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/pong.v new file mode 100644 index 00000000..4fe31e6b --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/pong.v @@ -0,0 +1,110 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + Arcade: Atari Pong (1972) + A Verilog implementation based on the original schematics. + + Written by: Richard Eng +*/ +`default_nettype none + +module pong( + input wire mclk, + input wire clk7_159, coin_sw, + input wire [7:0] dip_sw, // dip_sw[0] - 0: 11 points, 1: 15 points + input wire [7:0] paddle1_vpos, + input wire [7:0] paddle2_vpos, + /* verilator lint_off UNOPTFLAT */ + output wire net, _hsync, _vsync, sync_2_2k, pads_net_1k, score_1_2k, sound_out, hsync, vsync, hblank, vblank, + output wire [3:0] r, + output wire [3:0] g, + output wire [3:0] b + /* verilator lint_on UNOPTFLAT */ +); + +// hcounter +/* verilator lint_off UNUSED */ +wire h1, h2, h4, h8, h16, h32, h64, h128, h256, _h256, hreset, _hreset; + /* verilator lint_on UNUSED */ +//wire [8:0] hcnt; +//assign hcnt = { h256, h128, h64, h32, h16, h8, h4, h2, h1 }; +hcounter hc(clk7_159, h1, h2, h4, h8, h16, h32, h64, h128, h256, _h256, hreset, _hreset); + +// hsync +wire _hblank; +hsync hs(mclk, clk7_159, _hreset, h16, h32, h64, hblank, _hblank, _hsync); +assign hsync = ~_hsync; + +// vcounter +/* verilator lint_off UNUSED */ +wire v1, v2, v4, v8, v16, v32, v64, v128, v256, _v256, vreset, _vreset; +/* verilator lint_on UNUSED */ +//wire [8:0] vcnt; +//assign vcnt = { v256, v128, v64, v32, v16, v8, v4, v2, v1 }; +vcounter vc(hreset, v1, v2, v4, v8, v16, v32, v64, v128, v256, _v256, vreset, _vreset); + +// vsync +/* verilator lint_off UNOPTFLAT */ +wire _vblank; +/* verilator lint_on UNOPTFLAT */ +vsync vs(mclk, vreset, v4, v8, v16, vblank, _vblank, _vsync); +assign vsync = ~_vsync; + +// net +net n(clk7_159, vblank, v4, h256, _h256, net); + +// sound +wire sc, hit_sound; +sound snd(clk7_159, _miss, v32, vball16, _hit, vball240, _serve, _vvid, vblank, vvid, vball32, _attract, sc, hit_sound, sound_out); + +// video +wire hit, _hit, _hit1, _hit2; +video v(score, _hsync, _vsync, pad1, pad2, net, _hvid, _vvid, score_1_2k, sync_2_2k, pads_net_1k, _hit, _hit2, hit, _hit1); +assign r = hblank ? 4'h0 : vblank ? 4'h0 : pads_net_1k ? 4'hf : score_1_2k ? 4'hb : 4'h0; +assign g = r; +assign b = r; + +// score board +wire _miss, stop_g, score; +score s(dip_sw, _hvid, hblank, _attract, left, right, srst, _srst, h4, h8, h16, h32, h64, h128, h256, v4, v8, v16, v32, v64, v128, _miss, stop_g, score); + +// ball horizontal +wire left, right, _hvid; +ball_horizontal bal_hor(_h256, vreset, rst_speed, hit_sound, _hit2, sc, attract, _hit1, _hblank, clk7_159, _attract, serve, left, right, _hvid); + +// ball vertical +wire vball16, vball32, vball240, _vvid, vvid; +ball_vertical bal_ver(_hsync, _vblank, vblank, _hit, d1, _h256, d2, h256, c1, c2, b2, b1, attract, hit, vball16, vball32, vball240, _vvid, vvid); + +// game control +wire _srst, srst, rst_speed, attract, _attract, serve, _serve; +game_control game_control(clk7_159, _miss, stop_g, pad1, coin_sw, _srst, srst, rst_speed, attract, _attract, serve, _serve); + +// paddles +wire pad1, b1, c1, d1; +wire pad2, b2, c2, d2; +paddles paddles(paddle1_vpos, paddle2_vpos, _hsync, _v256, _attract, h4, h128, h256, _h256, b1, c1, d1, pad1, b2, c2, d2, pad2); + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/score.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/score.v new file mode 100644 index 00000000..0c6c7a3a --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/score.v @@ -0,0 +1,47 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + Pong - Score Counters Circuit + ----------------------------- +*/ +`default_nettype none + +module score +( + input wire [7:0] dip_sw, + input wire _hvid, hblank, _attract, l, r, srst, _srst, + input wire h4, h8, h16, h32, h64, h128, h256, v4, v8, v16, v32, v64, v128, + output wire _miss, stop_g, score +); + +wire a, b, c, d, e, f, g; +wire s1a, s1b, s1c, s1d, s1e, _s1e; +wire s2a, s2b, s2c, s2d, s2e, _s2e; + +score_counters sb1(dip_sw, _hvid, hblank, _attract, l, r, srst, _srst, _miss, stop_g, s1a, s1b, s1c, s1d, s1e, _s1e, s2a, s2b, s2c, s2d, s2e, _s2e); +score_counters_to_segments sb2(s1a, s1b, s1c, s1d, s1e, _s1e, s2a, s2b, s2c, s2d, s2e, _s2e, h32, h64, h128, h256, v32, v64, v128, a, b, c, d, e, f, g); +score_segments_to_video sb3(h4, h8, h16, v4, v8, v16, a, b, c, d, e, f, g, score); + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/score_counters.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/score_counters.v new file mode 100644 index 00000000..11d528ef --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/score_counters.v @@ -0,0 +1,63 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + Pong - Score Counters Circuit + ----------------------------- +*/ +`default_nettype none + +module score_counters +( + input wire [7:0] /* verilator lint_off UNUSED */ dip_sw /* verilator lint_on UNUSED */, + input wire _hvid, hblank, _attract, l, r, srst, _srst, + output wire _miss, stop_g, s1a, s1b, s1c, s1d, s1e, _s1e, + output wire s2a, s2b, s2c, s2d, s2e, _s2e +); + +wire h6a_to_e6c, d1f_to_e1a, _missed, f5b_to_c7, f5a_to_d7; + +ls20 h6a(_hvid, _hvid, _hvid, _hvid, h6a_to_e6c); +ls00 e6c(h6a_to_e6c, hblank, _miss); +ls04 d1f(_miss, d1f_to_e1a); +ls00 e1a(d1f_to_e1a, _attract, _missed); +ls02 f5b(_missed, l, f5b_to_c7); +ls02 f5a(_missed, r, f5a_to_d7); + +ls90 c7(f5b_to_c7, 1'b1, srst, srst, 1'b0, 1'b0, s1a, s1b, s1c, s1d); +ls107 c8a(s1d, _srst, 1'b1, 1'b1, s1e, _s1e); + +ls90 d7(f5a_to_d7, 1'b1, srst, srst, 1'b0, 1'b0, s2a, s2b, s2c, s2d); +ls107 c8b(s2d, _srst, 1'b1, 1'b1, s2e, _s2e); + +// stop_g signal handling +// dip_sw[0] = 0 - 11 points +// dip_sw[0] = 1 - 15 points +wire d8a_out; +ls10 d8a(s1a, dip_sw[0] ? s1c : 1'b1, s1e, d8a_out); +wire d8b_out; +ls10 d8b(s2a, dip_sw[0] ? s2c : 1'b1, s2e, d8b_out); +ls00 b2a(d8a_out, d8b_out, stop_g); + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/score_counters_to_segments.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/score_counters_to_segments.v new file mode 100644 index 00000000..39492819 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/score_counters_to_segments.v @@ -0,0 +1,58 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + Pong - Score Counters to Segments Circuit + ----------------------------------------- +*/ +`default_nettype none + +module score_counters_to_segments +( + input wire s1a, s1b, s1c, s1d, /* verilator lint_off UNUSED */ s1e /* verilator lint_on UNUSED */, _s1e, + input wire s2a, s2b, s2c, s2d, /* verilator lint_off UNUSED */ s2e /* verilator lint_on UNUSED */, _s2e, + input wire h32, h64, h128, h256, v32, v64, v128, + output wire a, b, c, d, e, f, g +); + +wire c6_y1, c6_y2, d6_y1, d6_y2; +ls153 c6(1'b0, 1'b0, h32, h64, 1'b1, s1a, 1'b1, s2a, _s1e, s1b, _s2e, s2b, c6_y1, c6_y2); +ls153 d6(1'b0, 1'b0, h32, h64, _s1e, s1c, _s2e, s2c, _s1e, s1d, _s2e, s2d, d6_y1, d6_y2); + +ls48 c5(1'b1, 1'b1, d6_y2, d6_y1, c6_y2, c6_y1, f2a_out, a, b, c, d, e, f, g); + +wire e3a_out, e3b_out, e2c_out, e3c_out, d2c_out; +ls27 e3a(h128, h128, h128, e3a_out); +ls27 e3b(h256, h64, e3a_out, e3b_out); +ls10 e2c(e3a_out, h64, h256, e2c_out); +ls27 e3c(e2c_out, e2c_out, e2c_out, e3c_out); +ls02 d2c(e3b_out, e3c_out, d2c_out); + +wire g1a_out; +ls02 g1a(v32, v32, g1a_out); + +wire f2a_out; +ls25 f2a(g1a_out, v64, v128, d2c_out, 1'b1, f2a_out); + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/score_segments_to_video.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/score_segments_to_video.v new file mode 100644 index 00000000..55646a16 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/score_segments_to_video.v @@ -0,0 +1,85 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + Pong - Score Segments to Video Circuit + -------------------------------------- +*/ +`default_nettype none + +module score_segments_to_video +( + input wire h4, h8, h16, v4, v8, v16, + input wire a, b, c, d, e, f, g, + output wire score +); + +wire c3d_out; +ls00 c3d(h4, h8, c3d_out); + +wire e4b_out; +ls04 e4b(h16, e4b_out); + +wire e2a_out; +ls10 e2a(v4, v8, h16, e2a_out); + +wire e4a_out; +ls04 e4a(e2a_out, e4a_out); + +wire e4c_out; +ls04 e4c(v16, e4c_out); + +wire e5c_out; +ls27 e5c(e4b_out, h4, h8, e5c_out); + +wire d2b_out; +ls02 d2b(c3d_out, e4b_out, d2b_out); + +wire e5b_out; +ls27 e5b(v8, v4, e4b_out, e5b_out); + +wire d4a_out; +ls10 d4a(e4c_out, f, e5c_out, d4a_out); + +wire d5c_out; +ls10 d5c(e, v16, e5c_out, d5c_out); + +wire c4c_out; +ls10 c4c(d2b_out, e4c_out, b, c4c_out); + +wire d5a_out; +ls10 d5a(d2b_out, c, v16, d5a_out); + +wire d4c_out; +ls10 d4c(a, e4c_out, e5b_out, d4c_out); + +wire d4b_out; +ls10 d4b(g, e4a_out, e4c_out, d4b_out); + +wire d5b_out; +ls10 d5b(e4a_out, v16, d, d5b_out); + +ls30 d3(d4a_out, d5c_out, c4c_out, d5a_out, 1'b1, d4c_out, d4b_out, d5b_out, score); + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/sound.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/sound.v new file mode 100644 index 00000000..b4022951 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/sound.v @@ -0,0 +1,68 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + Pong - Sound Circuit + -------------------- +*/ +`default_nettype none + +module sound +( + input wire clk7_159, _miss, v32, vball16, _hit, vball240, _serve, _vvid, vblank, vvid, vball32, _attract, + output wire sc, hit_sound, sound_out +); + +timer #(7_159_000, 240) g4(clk7_159, _miss, sc); + +wire c3c_to_c4b; +ls00 c3c(v32, sc, c3c_to_c4b); + +/* verilator lint_off UNUSED */ +wire c2a_q; +/* verilator lint_on UNUSED */ +wire c2a__q; +ls74 c2a(vball240, 1'b1, _hit, 1'b1, c2a_q, c2a__q); +assign hit_sound = c2a__q; + +wire c3a_to_c4b; +ls00 c3a(c2a__q, vball16, c3a_to_c4b); + +wire f3a_q; +/* verilator lint_off UNUSED */ +wire f3a__q; +/* verilator lint_on UNUSED */ +ls107 f3a(vblank, _serve, vvid, _vvid, f3a_q, f3a__q); + +wire c3b_to_c4b; +ls00 c3b(vball32, f3a_q, c3b_to_c4b); + +wire c4b_to_c1b; +ls10 c4b(c3b_to_c4b, c3a_to_c4b, c3c_to_c4b, c4b_to_c1b); + +wire c1b_out; +ls00 c1b(_attract, c4b_to_c1b, c1b_out); +assign sound_out = c1b_out; + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/srlatch.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/srlatch.v new file mode 100644 index 00000000..475ec034 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/srlatch.v @@ -0,0 +1,56 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + inputs outputs + _s _r q _q + 0 0 x x + 0 1 1 0 + 1 0 0 1 + 1 1 q0 _q0 +*/ + +module srlatch +( + input wire mclk, _s, _r, + output wire q, + output wire _q +); + +reg val; +initial val = 1'b0; + +always @(posedge mclk) begin + case({_s, _r}) + {1'b0, 1'b0}: val <= 1'bx; + {1'b0, 1'b1}: val <= 1'b1; + {1'b1, 1'b0}: val <= 1'b0; + {1'b1, 1'b1}: val <= val; + endcase +end + +assign q = val; +assign _q = ~q; + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/timer.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/timer.v new file mode 100644 index 00000000..7014e791 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/timer.v @@ -0,0 +1,60 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + Pong - Single Shot Timer + Simple emulation of an analogue 555 timer + ----------------------------------------- +*/ +`default_nettype none + +module timer +#( + parameter CLK_FREQ = 0, + parameter DURATION_MS = 0 +) +( + input wire _clk, _trigger, + output reg out +); + +localparam TIMEOUT = (CLK_FREQ / 1000) * DURATION_MS; + +reg [31:0] counter; + +initial counter = 32'd0; + +always @(negedge _clk) begin + if (counter > 0) begin + counter <= counter - 32'd1; + if (counter == 32'd1) begin + out <= 1'b0; + end + end else if (counter == 32'd0 && !_trigger) begin + counter <= TIMEOUT; + out <= 1'b1; + end +end + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls00.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls00.v new file mode 100644 index 00000000..50ebb25b --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls00.v @@ -0,0 +1,53 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + 74LS00 + ------ + Quad 2-Input NAND Gate + + Pinout + ------ + _______ + | | + a1 -| 1 14 |- VCC + b1 -| 2 13 |- b4 + y1 -| 3 12 |- a4 + a2 -| 4 11 |- y4 + b2 -| 5 10 |- b3 + y2 -| 6 9 |- a3 + GND -| 7 8 |- y3 + |_______| +*/ +`default_nettype none + +module ls00 +( + input wire a, b, + output wire y +); + +nand(y, a, b); + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls02.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls02.v new file mode 100644 index 00000000..39e05383 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls02.v @@ -0,0 +1,53 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + 74LS02 + ------ + Quad 2-Input NOR Gate + + Pinout + ------ + _______ + | | + y1 -| 1 14 |- VCC + a1 -| 2 13 |- y4 + b1 -| 3 12 |- b4 + y2 -| 4 11 |- a4 + a2 -| 5 10 |- y3 + b2 -| 6 9 |- b3 + GND -| 7 8 |- a3 + |_______| +*/ +`default_nettype none + +module ls02 +( + input wire a, b, + output wire y +); + +nor(y, a, b); + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls04.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls04.v new file mode 100644 index 00000000..0276e3b6 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls04.v @@ -0,0 +1,53 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + 74LS04 + ------ + Hex Inverting Gates + + Pinout + ------ + _______ + | | + a1 -| 1 14 |- VCC + y1 -| 2 13 |- a6 + a2 -| 3 12 |- y6 + y2 -| 4 11 |- a5 + a3 -| 5 10 |- y5 + y3 -| 6 9 |- a4 + GND -| 7 8 |- y4 + |_______| +*/ +`default_nettype none + +module ls04 +( + input wire a, + output wire y +); + +not(y, a); + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls10.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls10.v new file mode 100644 index 00000000..10af2805 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls10.v @@ -0,0 +1,53 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + 74LS10 + ------ + Triple 3-Input NAND Gate + + Pinout + ------ + _______ + | | + a1 -| 1 14 |- VCC + b1 -| 2 13 |- c1 + a2 -| 3 12 |- y1 + b2 -| 4 11 |- c3 + c2 -| 5 10 |- b3 + y2 -| 6 9 |- a3 + GND -| 7 8 |- y3 + |_______| +*/ +`default_nettype none + +module ls10 +( + input wire a, b, c, + output wire y +); + +nand(y, a, b, c); + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls107.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls107.v new file mode 100644 index 00000000..9096930a --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls107.v @@ -0,0 +1,68 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + 74LS107 + ------- + Dual Negative-Edge-Triggered J-K Flip-Flops with clear + + Pinout + ------ + _______ + | | + j1 -| 1 14 |- VCC + _q1 -| 2 13 |- _clr1 + q1 -| 3 12 |- _clk1 + k1 -| 4 11 |- k2 + q2 -| 5 10 |- _clr2 + _q2 -| 6 9 |- _clk2 + GND -| 7 8 |- j2 + |_______| +*/ +`default_nettype none + +module ls107 +( + input wire _clk, _clr, j, k, + output reg q, + output wire _q +); + +initial q = 1'b0; + +always @(negedge _clk or negedge _clr) begin + if (_clr == 1'b0) begin + q <= 1'b0; + end else if (j == 1'b1 && k == 1'b0) begin + q <= 1'b1; + end else if (j == 1'b0 && k == 1'b1) begin + q <= 1'b0; + end else if (j == 1'b1 && k == 1'b1) begin + q <= ~q; + end +end + +assign _q = ~q; + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls153.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls153.v new file mode 100644 index 00000000..c5dbdf01 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls153.v @@ -0,0 +1,66 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + 74LS153 + ------ + Dual 1-of-4 Line Data Selectors/Multiplexers + + Pinout + ------ + _______ + | | +_stb_g1 -| 1 16 |- VCC + sel_b -| 2 15 |- _stb_g2 + g1c3 -| 3 14 |- sel_a + g1c2 -| 4 13 |- g2c3 + g1c1 -| 5 12 |- g2c2 + g1c0 -| 6 11 |- g2c1 + y1 -| 7 10 |- g2c0 + GND -| 8 9 |- y2 + |_______| +*/ +`default_nettype none + +module ls153 +( + input wire _stb_g1, _stb_g2, sel_a, sel_b, g1c0, g1c1, g1c2, g1c3, g2c0, g2c1, g2c2, g2c3, + output wire y1, y2 +); + +wire cc1, cc2, cc3, cc4, cc5, cc6, cc7, cc8; +and(cc1, ~_stb_g1, ~sel_b, ~sel_a, g1c0); +and(cc2, ~_stb_g1, ~sel_b, sel_a, g1c1); +and(cc3, ~_stb_g1, sel_b, ~sel_a, g1c2); +and(cc4, ~_stb_g1, sel_b, sel_a, g1c3); + +and(cc5, ~_stb_g2, ~sel_b, ~sel_a, g2c0); +and(cc6, ~_stb_g2, ~sel_b, sel_a, g2c1); +and(cc7, ~_stb_g2, sel_b, ~sel_a, g2c2); +and(cc8, ~_stb_g2, sel_b, sel_a, g2c3); + +or(y1, cc1, cc2, cc3, cc4); +or(y2, cc5, cc6, cc7, cc8); + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls20.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls20.v new file mode 100644 index 00000000..3f7587d3 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls20.v @@ -0,0 +1,53 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + 74LS20 + ------ + Dual 4-Input NAND Gate + + Pinout + ------ + _______ + | | + a1 -| 1 14 |- VCC + b1 -| 2 13 |- d2 + NC -| 3 12 |- c2 + c1 -| 4 11 |- NC + d1 -| 5 10 |- b2 + y1 -| 6 9 |- a2 + GND -| 7 8 |- y2 + |_______| +*/ +`default_nettype none + +module ls20 +( + input wire a, b, c, d, + output wire y +); + +nand(y, a, b, c, d); + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls25.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls25.v new file mode 100644 index 00000000..881915ec --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls25.v @@ -0,0 +1,51 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + 74LS25 + ------ + Dual 4-Input NOR Gates With Strobe + + Pinout + ------ + _______ + | | + a1 -| 1 14 |- VCC + b1 -| 2 13 |- d2 + g1 -| 3 12 |- c2 + c1 -| 4 11 |- g2 + d1 -| 5 10 |- b2 + y1 -| 6 9 |- a2 + GND -| 7 8 |- y2 + |_______| +*/ +module ls25 +( + input wire a, b, c, d, g, + output wire y +); + +assign y = (g == 1'b1) ? ~(a | b | c | d) : 1'b1; + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls27.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls27.v new file mode 100644 index 00000000..b6dd9d10 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls27.v @@ -0,0 +1,53 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + 74LS27 + ------ + Triple 3-Input NOR Gate + + Pinout + ------ + _______ + | | + a1 -| 1 14 |- VCC + b1 -| 2 13 |- c1 + a2 -| 3 12 |- y1 + b2 -| 4 11 |- c3 + c2 -| 5 10 |- b3 + y2 -| 6 9 |- a3 + GND -| 7 8 |- y3 + |_______| +*/ +`default_nettype none + +module ls27 +( + input wire a, b, c, + output wire y +); + +nor(y, a, b, c); + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls30.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls30.v new file mode 100644 index 00000000..27f7a84a --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls30.v @@ -0,0 +1,53 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + 74LS30 + ------ + 8-Input NAND Gate + + Pinout + ------ + _______ + | | + a -| 1 14 |- VCC + b -| 2 13 |- NC + c -| 3 12 |- h + d -| 4 11 |- g + e -| 5 10 |- NC + f -| 6 9 |- NC + GND -| 7 8 |- y + |_______| +*/ +`default_nettype none + +module ls30 +( + input wire a, b, c, d, e, f, g, h, + output wire y +); + +assign y = ~(a & b & c & d & e & f & g & h); + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls48.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls48.v new file mode 100644 index 00000000..aadb6402 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls48.v @@ -0,0 +1,111 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + 74LS48 + ------ + BCD to 7-Segment Decoder + + Pinout + ------ + _______ + | | + a1 -| 1 14 |- VCC + a2 -| 2 13 |- f + _lt -| 3 12 |- g +_bi_rbo -| 4 11 |- a + _rbi -| 5 10 |- b + a3 -| 6 9 |- c + a0 -| 7 8 |- d + GND -| 8 9 |- e + |_______| +*/ +`default_nettype none + +module ls48 +( + input wire _lt, _rbi, a3, a2, a1, a0, _bi_rbo, + output wire a, b, c, d, e, f, g +); + +wire _a3, _a2, _a1, _a0; +not(_a3, a3); +nand(_a2, a2, _lt); +nand(_a1, a1, _lt); +nand(_a0, a0, _lt); + +wire d1, d2, a3_2, a2_2, a1_2, a0_2; +nand(d1, _lt, ~_rbi, _a3, _a2, a2_2, _a0); +assign d2 = _bi_rbo == 1'b1 ? d1 : 1'b0; +nand(a3_2, d2, _a3); +nand(a2_2, d2, _a2); +nand(a1_2, d2, _a1); +nand(a0_2, d2, _a0); + +// segment a +wire aa1, aa2, aa3; +and(aa1, _a3, _a2, _a1, a0_2); +and(aa2, a2_2, _a0); +and(aa3, a3_2, a1_2); +and(a, ~aa1, ~aa2, ~aa3); + +// segment b +wire bb1, bb2, bb3; +and(bb1, a2_2, a1_2, _a0); +and(bb2, a2_2, _a1, a0_2); +and(bb3, a3_2, a1_2); +and(b, ~bb1, ~bb2, ~bb3); + +// segment c +wire cc1, cc2; +and(cc1, _a2, a1_2, _a0); +and(cc2, a3_2, a2_2); +and(c, ~cc1, ~cc2); + +// segment d +wire dd1, dd2, dd3; +and(dd1, a2_2, a1_2, a0_2); +and(dd2, a2_2, _a1, _a0); +and(dd3, _a2, _a1, a0_2); +and(d, ~dd1, ~dd2, ~dd3); + +// segment e +wire ee1; +and(ee1, a2_2, _a1); +and(e, ~ee1, ~a0_2); + +// segment f +wire ff1, ff2, ff3; +and(ff1, _a3, _a2, a0_2); +and(ff2, _a2, a1_2); +and(ff3, a1_2, a0_2); +and(f, ~ff1, ~ff2, ~ff3); + +// segment g +wire gg1, gg2; +and(gg1, _lt, _a3, _a2, _a1); +and(gg2, a2_2, a1_2, a0_2); +and(g, ~gg1, ~gg2); + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls50.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls50.v new file mode 100644 index 00000000..58c0560b --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls50.v @@ -0,0 +1,58 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + 74LS50 + ------ + Dual 2-Wide 2-Input And-Or-Invert Gates (One Gate Expandable) + + Pinout + ------ + _______ + | | + a1 -| 1 14 |- VCC + a2 -| 2 13 |- b1 + b2 -| 3 12 |- _x1 + c2 -| 4 11 |- x1 + d2 -| 5 10 |- d1 + y2 -| 6 9 |- c1 + GND -| 7 8 |- y1 + |_______| +*/ +`default_nettype none + +module ls50 +( + input wire a, b, c, d, + output wire y +); + +wire a2, b2; +and(a2, a, b); +and(b2, c, d); +nor(y, a2, b2); + +// TODO: What's the purpose with x1 and _x1? + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls74.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls74.v new file mode 100644 index 00000000..8d67cc82 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls74.v @@ -0,0 +1,69 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + 74LS74 + ------ + Dual Positive-Edge-Triggered D Flip-Flops with + Preset, Clear and Complementary Outputs + + Pinout + ------ + _______ + | | + _clr1 -| 1 14 |- VCC + d1 -| 2 13 |- _clr2 + clk1 -| 3 12 |- d2 + _pr1 -| 4 11 |- clk2 + q1 -| 5 10 |- _pr2 + _q1 -| 6 9 |- q2 + GND -| 7 8 |- _q2 + |_______| +*/ +`default_nettype none + +module ls74 +( + input wire clk, d, _clr, _pr, + output reg q, + output wire _q +); + +initial begin + q = 1'b0; +end + +always @(posedge clk or negedge _clr or negedge _pr) begin + if (_clr == 1'b0) begin + q <= 1'b0; + end else if (_pr == 1'b0) begin + q <= 1'b1; + end else begin + q <= d; + end +end + +assign _q = ~q; + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls83.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls83.v new file mode 100644 index 00000000..b84f97be --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls83.v @@ -0,0 +1,106 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + 74LS83 + ------ + 4-Bit Binary Adder with Fast Carry + + Pinout + ------ + _______ + | | + a4 -| 1 16 |- b4 + s3 -| 2 15 |- s4 + a3 -| 3 14 |- c4 + b3 -| 4 13 |- c0 + VCC -| 5 12 |- GND + s2 -| 6 11 |- b1 + b2 -| 7 10 |- a1 + a2 -| 8 9 |- s1 + |_______| +*/ +`default_nettype none + +module ls83 +( + input wire a1, a2, a3, a4, bb1, bb2, bb3, bb4, c0, + output wire s1, s2, s3, s4, c4 +); + +wire i1, i2, i3, i4, i5, i6, i7, i8, i9; +nand(i1, bb4, a4); +nor(i2, bb4, a4); +nand(i3, bb3, a3); +nor(i4, bb3, a3); +nand(i5, bb2, a2); +nor(i6, bb2, a2); +nand(i7, bb1, a1); +nor(i8, bb1, a1); +not(i9, c0); + +wire j1, j2, j3, j4, j5, j6, j7, j8, j9, j10, j11, j12, j13, j14, j15, j16, j17, j18, j19; + +assign j1 = i2; +and(j2, i4, i1); +and(j3, i6, i1, i3); +and(j4, i8, i1, i3, i5); +and(j5, i1, i3, i5, i7, i9); +and(j6, i1, ~i2); + +assign j7 = i4; +and(j8, i6, i3); +and(j9, i8, i3, i5); +and(j10, i3, i5, i7, i9); +and(j11, i3, ~i4); + +assign j12 = i6; +and(j13, i8, i5); +and(j14, i5, i7, i9); +and(j15, i5, ~i6); + +assign j16 = i8; +and(j17, i7, i9); +and(j18, i7, ~i8); +not(j19, i9); + +wire k1, k2, k3, k4; +nor(k1, j1, j2, j3, j4, j5); +nor(k2, j7, j8, j9, j10); +nor(k3, j12, j13, j14); +nor(k4, j16, j17); + +wire l1, l2, l3, l4; +xor(l1, j6, k2); +xor(l2, j11, k3); +xor(l3, j15, k4); +xor(l4, j18, j19); + +assign c4 = k1; +assign s4 = l1; +assign s3 = l2; +assign s2 = l3; +assign s1 = l4; + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls86.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls86.v new file mode 100644 index 00000000..d6b30094 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls86.v @@ -0,0 +1,53 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + 74LS86 + ------ + Quad 2-Input Exclusive-OR Gate + + Pinout + ------ + _______ + | | + a1 -| 1 14 |- VCC + b1 -| 2 13 |- b4 + y1 -| 3 12 |- a4 + a2 -| 4 11 |- y4 + b2 -| 5 10 |- b3 + y2 -| 6 9 |- a3 + GND -| 7 8 |- y3 + |_______| +*/ +`default_nettype none + +module ls86 +( + input wire a, b, + output wire y +); + +xor(y, a, b); + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls90.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls90.v new file mode 100644 index 00000000..64ca016e --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls90.v @@ -0,0 +1,62 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + 74LS90 + ------ + Decade and Binary Counters + + Pinout + ------ + _______ + | | + _ckb -| 1 14 |- _cka + r0_1 -| 2 13 |- NC + r0_2 -| 3 12 |- qa + NC -| 4 11 |- qd + VCC -| 5 10 |- GND + r9_1 -| 6 9 |- qb + r9_2 -| 7 8 |- qc + |_______| +*/ +`default_nettype none + +module ls90 +( + input wire _cka, /* verilator lint_off UNUSED */ _ckb /* verilator lint_on UNUSED */, r0_1, r0_2, r9_1, r9_2, + output wire qa, qb, qc, qd +); + +wire r0, r9; +assign r0 = ~(r0_1 & r0_2); +assign r9 = ~(r9_1 & r9_2); + +wire unused, unused2, unused3, _qd; +// _clk j k _set _clr q _q +png_jkff jkff1(_cka, 1'b1, 1'b1, r9, r0, qa, unused); +png_jkff jkff2(qa, _qd, 1'b1, 1'b1, ~(~r0 | ~r9), qb, unused2); +png_jkff jkff3(qb, 1'b1, 1'b1, 1'b1, ~(~r0 | ~r9), qc, unused3); +png_jkff jkff4(qa, (qc & qb), qd, r9, r0, qd, _qd); + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls93.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls93.v new file mode 100644 index 00000000..b1ff2af1 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/ttl/ls93.v @@ -0,0 +1,86 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + 74LS93 + ------ + 4-Bit Ripple Counter + + Pinout + ------ + _______ + | | + _cp1 -| 1 14 |- _cp0 + mr1 -| 2 13 |- NC + mr2 -| 3 12 |- q0 + NC -| 4 11 |- q3 + VCC -| 5 10 |- GND + NC -| 6 9 |- q1 + NC -| 7 8 |- q2 + |_______| +*/ +`default_nettype none + +module ls93 +( + input wire _cp0, /* verilator lint_off UNUSED */ _cp1 /* verilator lint_on UNUSED */, mr1, mr2, + output reg q0, q1, q2, q3 +); + +wire mr; +assign mr = (mr1 & mr2); + +always @(negedge _cp0 or posedge mr) begin + if (mr == 1'b1) begin + q0 <= 1'b0; + end else begin + q0 <= ~q0; + end +end + +always @(negedge q0 or posedge mr) begin + if (mr == 1'b1) begin + q1 <= 1'b0; + end else begin + q1 <= ~q1; + end +end + +always @(negedge q1 or posedge mr) begin + if (mr == 1'b1) begin + q2 <= 1'b0; + end else begin + q2 <= ~q2; + end +end + +always @(negedge q2 or posedge mr) begin + if (mr == 1'b1) begin + q3 <= 1'b0; + end else begin + q3 <= ~q3; + end +end + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/vcounter.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/vcounter.v new file mode 100644 index 00000000..99e6b3b6 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/vcounter.v @@ -0,0 +1,68 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + Pong - Vertical Counter Circuit + ------------------------------- +*/ +`default_nettype none + +module vcounter +( + input wire hreset, + output wire v1, v2, v4, v8, v16, v32, v64, v128, v256, _v256, vreset, _vreset +); + +/* +wire d8c_to_e7a; + +ls93 e8(hreset, , vreset, vreset, v1, v2, v4, v8); +ls93 e9(v8, , vreset, vreset, v16, v32, v64, v128); +ls107 d9b(v128, _vreset, 1'b1, 1'b1, v256, _v256); +ls10 d8c(v256, v4, v1, d8c_to_e7a); +ls74 e7a(hreset, d8c_to_e7a, 1'b1, 1'b1, _vreset, vreset); +*/ + +reg [8:0] vcnt; + +initial vcnt = 9'd0; + +assign { _v256, v256, v128, v64, v32, v16, v8, v4, v2, v1 } = { ~vcnt[8], vcnt[8], vcnt[7], vcnt[6], vcnt[5], vcnt[4], vcnt[3], vcnt[2], vcnt[1], vcnt[0] }; + +always @(negedge hreset or posedge vreset) begin + if (vreset) + vcnt <= 9'd0; + else + vcnt <= vcnt + 1'b1; +end + +reg rst; +always @(posedge hreset) begin + rst <= (vcnt == 9'd261); +end + +assign vreset = rst; +assign _vreset = ~vreset; + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/video.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/video.v new file mode 100644 index 00000000..2780d219 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/video.v @@ -0,0 +1,56 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + Pong - Video Generator Circuit + ------------------------------ +*/ +`default_nettype none + +module video +( + input wire score, _hsync, _vsync, pad1, pad2, net, _hvid, _vvid, + output wire score_1_2k, sync_2_2k, pads_net_1k, _hit, _hit2, hit, _hit1 +); + +wire a4d_to_e4e; +ls86 a4d(_hsync, _vsync, a4d_to_e4e); +ls04 e4e(a4d_to_e4e, sync_2_2k); + +wire f2b_to_e4f; +ls25 f2b(pad1, net, pad2, g1b_out, 1'b1, f2b_to_e4f); +ls04 e4f(f2b_to_e4f, pads_net_1k); + +wire g1b_out; +ls02 g1b(_hvid, _vvid, g1b_out); + +ls00 g3a(pad2, g1b_out, _hit2); +ls00 g3d(pad1, g1b_out, _hit1); + +ls00 b2c(_hit1, _hit2, hit); +ls00 b2d(hit, hit, _hit); + +assign score_1_2k = score; + +endmodule diff --git a/Arcade_MiST/Atari Discrete Logic/Pong/rtl/vsync.v b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/vsync.v new file mode 100644 index 00000000..ae7b09e0 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/Pong/rtl/vsync.v @@ -0,0 +1,40 @@ +/* + MIT License + + Copyright (c) 2019 Richard Eng + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +*/ + +/* + Pong - Vertical Sync Circuit + ---------------------------- +*/ +`default_nettype none + +module vsync +( + input wire mclk, vreset, v4, v8, v16, + output wire vblank, _vblank, _vsync +); + +srlatch f5cd(mclk, ~vreset, ~v16, vblank, _vblank); +assign _vsync = ~(vblank & v4 & ~v8); + +endmodule diff --git a/Arcade_MiST/Scramble Hardware/Amored Car.jpg b/Arcade_MiST/Scramble Hardware/Amored Car.jpg new file mode 100644 index 00000000..a2e0dc82 Binary files /dev/null and b/Arcade_MiST/Scramble Hardware/Amored Car.jpg differ diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/Calipso.qpf b/Arcade_MiST/Scramble Hardware/Calypso_MiST/Calipso.qpf new file mode 100644 index 00000000..a7153522 --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/Calipso.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "Calipso" diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/Calipso.qsf b/Arcade_MiST/Scramble Hardware/Calypso_MiST/Calipso.qsf new file mode 100644 index 00000000..beaef3c7 --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/Calipso.qsf @@ -0,0 +1,170 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition +# Date created = 21:38:42 October 11, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Calipso_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Calipso_Mist.sv +set_global_assignment -name VHDL_FILE rtl/scramble_top.vhd +set_global_assignment -name VHDL_FILE rtl/scramble.vhd +set_global_assignment -name VHDL_FILE rtl/scramble_audio.vhd +set_global_assignment -name VHDL_FILE rtl/scramble_video.vhd +set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd +set_global_assignment -name VHDL_FILE rtl/rom/ROM_PGM.vhd +set_global_assignment -name VHDL_FILE rtl/rom/ROM_OBJ_1.vhd +set_global_assignment -name VHDL_FILE rtl/rom/ROM_OBJ_0.vhd +set_global_assignment -name VHDL_FILE rtl/rom/ROM_SND_2.vhd +set_global_assignment -name VHDL_FILE rtl/rom/ROM_SND_1.vhd +set_global_assignment -name VHDL_FILE rtl/rom/ROM_SND_0.vhd +set_global_assignment -name VHDL_FILE rtl/rom/ROM_LUT.vhd +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name VHDL_FILE rtl/MULT18X18.vhd +set_global_assignment -name VHDL_FILE rtl/i82c55.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd +set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name TOP_LEVEL_ENTITY Calipso_Mist +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# -------------------------- +# start ENTITY(Calypso_Mist) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Calypso_Mist) +# ------------------------ +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/README.txt b/Arcade_MiST/Scramble Hardware/Calypso_MiST/README.txt new file mode 100644 index 00000000..f79868c7 --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/README.txt @@ -0,0 +1,28 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Calipso port to MiST by Gehstock +-- 10 November 2017 +-- + +ToDo: Grafic Problems in Attract Mode maybe in Game +--------------------------------------------------------------------------------- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +--------------------------------------------------------------------------------- +-- +-- Only controls and OSD are rotated on Video output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- SPACE : Fire+Bomb + +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- + diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/Release/Calipso.rbf b/Arcade_MiST/Scramble Hardware/Calypso_MiST/Release/Calipso.rbf new file mode 100644 index 00000000..141fb8ae Binary files /dev/null and b/Arcade_MiST/Scramble Hardware/Calypso_MiST/Release/Calipso.rbf differ diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/clean.bat b/Arcade_MiST/Scramble Hardware/Calypso_MiST/clean.bat new file mode 100644 index 00000000..e7c1ce5e --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/clean.bat @@ -0,0 +1,38 @@ +@echo off +del /s *.bak +del /s PLLJ_PLLSPE_INFO.txt +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/Calipso_Mist.sv b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/Calipso_Mist.sv new file mode 100644 index 00000000..35d0f4a5 --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/Calipso_Mist.sv @@ -0,0 +1,205 @@ +//============================================================================ +// Arcade: Calypso +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module Calipso_Mist +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Calipso;;", + "O2,Rotate Controls,Off,On;", + "O34,Scanlines,Off,25%,50%,75%;", +// "O5,Service,Off,On;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +assign LED = 1; +assign AUDIO_R = AUDIO_L; + +wire clk_sys; +wire pll_locked; +pll pll( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_sys), + .locked(pll_locked) + ); + +reg ce_6p, ce_6n, ce_12, ce_1p79; +always @(negedge clk_sys) begin +reg [1:0] div = 0; +reg [3:0] div179 = 0; + div <= div + 1'd1; + ce_12 <= div[0]; + ce_6p <= div[0] & ~div[1]; + ce_6n <= div[0] & div[1]; + ce_1p79 <= 0; + div179 <= div179 - 1'd1; + if(!div179) begin + div179 <= 13; + ce_1p79 <= 1; + end +end + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoublerD; +wire ypbpr; +wire [10:0] ps2_key; +wire [9:0] audio; +wire hs, vs; +wire blankn = ~(hb | vb); +wire hb, vb; +wire [3:0] r,b,g; + +scramble_top scramble ( + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_HSYNC(hs), + .O_VSYNC(vs), + .O_HBLANK(hb), + .O_VBLANK(vb), + .O_AUDIO(audio), + .ip_dip_switch({5'd1}),//Coining, Coining, Free Play, Rocket,Cabinet + .ip_1p(~{btn_one_player, m_bomb, m_fire, m_left, m_right, m_up, m_down}), + .ip_2p(~{btn_two_players, m_bomb, m_fire, m_left,m_right, m_up, m_down}), + .ip_service(status[5]), + .ip_coin1(~btn_coin), + .ip_coin2(1'b1), + .RESET(status[0] | status[6] | buttons[1]), + .clk(clk_sys), + .ena_12(ce_12), + .ena_6(ce_6p), + .ena_6b(ce_6n), + .ena_1_79(ce_1p79) + ); + +mist_video #(.COLOR_DEPTH(4)) mist_video( + .clk_sys(clk_sys), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(blankn ? r : 0), + .G(blankn ? g : 0), + .B(blankn ? b : 0), + .HSync(~hs), + .VSync(~vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .rotate({1'b1,status[2]}), + .scandoubler_disable(scandoublerD), + .scanlines(status[4:3]), + .ypbpr(ypbpr) + ); + +user_io #( + .STRLEN(($size(CONF_STR)>>3))) +user_io( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable (scandoublerD ), + .ypbpr (ypbpr ), + .key_strobe (key_strobe ), + .key_pressed (key_pressed ), + .key_code (key_code ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) + ); + +dac #(16)dac( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i({audio, audio[9:5]}), + .dac_o(AUDIO_L) + ); +// Rotated Normal +wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3]; +wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2]; +wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1]; +wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0]; + +wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; +wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; + +reg btn_one_player = 0; +reg btn_two_players = 0; +reg btn_left = 0; +reg btn_right = 0; +reg btn_down = 0; +reg btn_up = 0; +reg btn_fire1 = 0; +reg btn_fire2 = 0; +//reg btn_fire3 = 0; +reg btn_coin = 0; +wire key_pressed; +wire [7:0] key_code; +wire key_strobe; + +always @(posedge clk_sys) begin + if(key_strobe) begin + case(key_code) + 'h75: btn_up <= key_pressed; // up + 'h72: btn_down <= key_pressed; // down + 'h6B: btn_left <= key_pressed; // left + 'h74: btn_right <= key_pressed; // right + 'h76: btn_coin <= key_pressed; // ESC + 'h05: btn_one_player <= key_pressed; // F1 + 'h06: btn_two_players <= key_pressed; // F2 +// 'h14: btn_fire3 <= key_pressed; // ctrl + 'h11: btn_fire2 <= key_pressed; // alt + 'h29: btn_fire1 <= key_pressed; // Space + endcase + end +end + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/MULT18X18.vhd b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/MULT18X18.vhd new file mode 100644 index 00000000..32535505 --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/MULT18X18.vhd @@ -0,0 +1,53 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY MULT18X18 IS + PORT + ( + A : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + B : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + P : OUT STD_LOGIC_VECTOR (35 DOWNTO 0) + ); +END MULT18X18; + + +ARCHITECTURE SYN OF mult18x18 IS + + COMPONENT lpm_mult + GENERIC ( + lpm_hint : STRING; + lpm_representation : STRING; + lpm_type : STRING; + lpm_widtha : NATURAL; + lpm_widthb : NATURAL; + lpm_widthp : NATURAL + ); + PORT ( + dataa : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + datab : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + lpm_mult_component : lpm_mult + GENERIC MAP ( + lpm_hint => "MAXIMIZE_SPEED=5", + lpm_representation => "SIGNED", + lpm_type => "LPM_MULT", + lpm_widtha => 18, + lpm_widthb => 18, + lpm_widthp => 36 + ) + PORT MAP ( + dataa => A, + datab => B, + result => P + ); + +END SYN; + diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80sed.vhd b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80sed.vhd new file mode 100644 index 00000000..0c28ec21 --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80sed.vhd @@ -0,0 +1,179 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0238 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80sed is + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80sed; + +architecture rtl of T80sed is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/YM2149_linmix_sep.vhd new file mode 100644 index 00000000..6ed2498a --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/YM2149_linmix_sep.vhd @@ -0,0 +1,574 @@ +-- changes for seperate audio outputs and enable now enables cpu access as well +-- +-- A simulation model of YM2149 (AY-3-8910 with bells on) + +-- Copyright (c) MikeJ - Jan 2005 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA +-- +-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V) +-- vol 15 .. 0 +-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132 +-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order +-- to produced all the required values. +-- (The first part of the curve is a bit steeper and the last bit is more linear than expected) +-- +-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only +-- accurate for designs where the outputs are buffered and not simply wired together. +-- The ouput level is more complex in that case and requires a larger table. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity YM2149 is + port ( + -- data bus + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + O_DA_OE_L : out std_logic; + -- control + I_A9_L : in std_logic; + I_A8 : in std_logic; + I_BDIR : in std_logic; + I_BC2 : in std_logic; + I_BC1 : in std_logic; + I_SEL_L : in std_logic; + + O_AUDIO : out std_logic_vector(7 downto 0); + O_CHAN : out std_logic_vector(1 downto 0); + -- port a + I_IOA : in std_logic_vector(7 downto 0); + O_IOA : out std_logic_vector(7 downto 0); + O_IOA_OE_L : out std_logic; + -- port b + I_IOB : in std_logic_vector(7 downto 0); + O_IOB : out std_logic_vector(7 downto 0); + O_IOB_OE_L : out std_logic; + + ENA : in std_logic; -- clock enable for higher speed operation + RESET_L : in std_logic; + CLK : in std_logic -- note 6 Mhz + ); +end; + +architecture RTL of YM2149 is + type array_16x8 is array (0 to 15) of std_logic_vector( 7 downto 0); + type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0); + + signal cnt_div : std_logic_vector(3 downto 0) := (others => '0'); + signal cnt_div_t1 : std_logic_vector(3 downto 0); + signal noise_div : std_logic := '0'; + signal ena_div : std_logic; + signal ena_div_noise : std_logic; + signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); + + -- registers + signal addr : std_logic_vector(7 downto 0); + signal busctrl_addr : std_logic; + signal busctrl_we : std_logic; + signal busctrl_re : std_logic; + + signal reg : array_16x8; + signal env_reset : std_logic; + signal ioa_inreg : std_logic_vector(7 downto 0); + signal iob_inreg : std_logic_vector(7 downto 0); + + signal noise_gen_cnt : std_logic_vector(4 downto 0); + signal noise_gen_op : std_logic; + signal tone_gen_cnt : array_3x12 := (others => (others => '0')); + signal tone_gen_op : std_logic_vector(3 downto 1) := "000"; + + signal env_gen_cnt : std_logic_vector(15 downto 0); + signal env_ena : std_logic; + signal env_hold : std_logic; + signal env_inc : std_logic; + signal env_vol : std_logic_vector(4 downto 0); + + signal tone_ena_l : std_logic; + signal tone_src : std_logic; + signal noise_ena_l : std_logic; + signal chan_vol : std_logic_vector(4 downto 0); + + signal dac_amp : std_logic_vector(7 downto 0); +begin + -- cpu i/f + p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8) + variable cs : std_logic; + variable sel : std_logic_vector(2 downto 0); + begin + -- BDIR BC2 BC1 MODE + -- 0 0 0 inactive + -- 0 0 1 address + -- 0 1 0 inactive + -- 0 1 1 read + -- 1 0 0 address + -- 1 0 1 inactive + -- 1 1 0 write + -- 1 1 1 read + busctrl_addr <= '0'; + busctrl_we <= '0'; + busctrl_re <= '0'; + + cs := '0'; + if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then + cs := '1'; + end if; + + sel := (I_BDIR & I_BC2 & I_BC1); + case sel is + when "000" => null; + when "001" => busctrl_addr <= '1'; + when "010" => null; + when "011" => busctrl_re <= cs; + when "100" => busctrl_addr <= '1'; + when "101" => null; + when "110" => busctrl_we <= cs; + when "111" => busctrl_addr <= '1'; + when others => null; + end case; + end process; + + p_oe : process(busctrl_re) + begin + -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns + O_DA_OE_L <= not (busctrl_re); + end process; + + -- + -- CLOCKED + -- + p_waddr : process(RESET_L, CLK) + begin + -- looks like registers are latches in real chip, but the address is caught at the end of the address state. + if (RESET_L = '0') then + addr <= (others => '0'); + elsif rising_edge(CLK) then + if (ENA = '1') then + if (busctrl_addr = '1') then + addr <= I_DA; + end if; + end if; + end if; + end process; + + p_wdata : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + reg <= (others => (others => '0')); + env_reset <= '1'; + elsif rising_edge(CLK) then + if (ENA = '1') then + env_reset <= '0'; + if (busctrl_we = '1') then + case addr(3 downto 0) is + when x"0" => reg(0) <= I_DA; + when x"1" => reg(1) <= I_DA; + when x"2" => reg(2) <= I_DA; + when x"3" => reg(3) <= I_DA; + when x"4" => reg(4) <= I_DA; + when x"5" => reg(5) <= I_DA; + when x"6" => reg(6) <= I_DA; + when x"7" => reg(7) <= I_DA; + when x"8" => reg(8) <= I_DA; + when x"9" => reg(9) <= I_DA; + when x"A" => reg(10) <= I_DA; + when x"B" => reg(11) <= I_DA; + when x"C" => reg(12) <= I_DA; + when x"D" => reg(13) <= I_DA; env_reset <= '1'; + when x"E" => reg(14) <= I_DA; + when x"F" => reg(15) <= I_DA; + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_rdata : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg) + begin + O_DA <= (others => '0'); -- 'X' + if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator + case addr(3 downto 0) is + when x"0" => O_DA <= reg(0) ; + when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ; + when x"2" => O_DA <= reg(2) ; + when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ; + when x"4" => O_DA <= reg(4) ; + when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ; + when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ; + when x"7" => O_DA <= reg(7) ; + when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ; + when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ; + when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ; + when x"B" => O_DA <= reg(11); + when x"C" => O_DA <= reg(12); + when x"D" => O_DA <= "0000" & reg(13)(3 downto 0); + when x"E" => if (reg(7)(6) = '0') then -- input + O_DA <= ioa_inreg; + else + O_DA <= reg(14); -- read output reg + end if; + when x"F" => if (Reg(7)(7) = '0') then + O_DA <= iob_inreg; + else + O_DA <= reg(15); + end if; + when others => null; + end case; + end if; + end process; + -- + p_divider : process + begin + wait until rising_edge(CLK); + -- / 8 when SEL is high and /16 when SEL is low + if (ENA = '1') then + ena_div <= '0'; + ena_div_noise <= '0'; + if (cnt_div = "0000") then + cnt_div <= (not I_SEL_L) & "111"; + ena_div <= '1'; + + noise_div <= not noise_div; + if (noise_div = '1') then + ena_div_noise <= '1'; + end if; + else + cnt_div <= cnt_div - "1"; + end if; + end if; + end process; + + p_noise_gen : process + variable noise_gen_comp : std_logic_vector(4 downto 0); + variable poly17_zero : std_logic; + begin + wait until rising_edge(CLK); + if (reg(6)(4 downto 0) = "00000") then + noise_gen_comp := "00000"; + else + noise_gen_comp := (reg(6)(4 downto 0) - "1"); + end if; + + poly17_zero := '0'; + if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; + + if (ENA = '1') then + if (ena_div_noise = '1') then -- divider ena + + if (noise_gen_cnt >= noise_gen_comp) then + noise_gen_cnt <= "00000"; + poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1); + else + noise_gen_cnt <= (noise_gen_cnt + "1"); + end if; + end if; + end if; + end process; + noise_gen_op <= poly17(0); + + p_tone_gens : process + variable tone_gen_freq : array_3x12; + variable tone_gen_comp : array_3x12; + begin + wait until rising_edge(CLK); + -- looks like real chips count up - we need to get the Exact behaviour .. + tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0); + tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2); + tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4); + -- period 0 = period 1 + for i in 1 to 3 loop + if (tone_gen_freq(i) = x"000") then + tone_gen_comp(i) := x"000"; + else + tone_gen_comp(i) := (tone_gen_freq(i) - "1"); + end if; + end loop; + + if (ENA = '1') then + for i in 1 to 3 loop + if (ena_div = '1') then -- divider ena + + if (tone_gen_cnt(i) >= tone_gen_comp(i)) then + tone_gen_cnt(i) <= x"000"; + tone_gen_op(i) <= not tone_gen_op(i); + else + tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1"); + end if; + end if; + end loop; + end if; + end process; + + p_envelope_freq : process + variable env_gen_freq : std_logic_vector(15 downto 0); + variable env_gen_comp : std_logic_vector(15 downto 0); + begin + wait until rising_edge(CLK); + env_gen_freq := reg(12) & reg(11); + -- envelope freqs 1 and 0 are the same. + if (env_gen_freq = x"0000") then + env_gen_comp := x"0000"; + else + env_gen_comp := (env_gen_freq - "1"); + end if; + + if (ENA = '1') then + env_ena <= '0'; + if (ena_div = '1') then -- divider ena + if (env_gen_cnt >= env_gen_comp) then + env_gen_cnt <= x"0000"; + env_ena <= '1'; + else + env_gen_cnt <= (env_gen_cnt + "1"); + end if; + end if; + end if; + end process; + + p_envelope_shape : process(env_reset, reg, CLK) + variable is_bot : boolean; + variable is_bot_p1 : boolean; + variable is_top_m1 : boolean; + variable is_top : boolean; + begin + -- envelope shapes + -- C AtAlH + -- 0 0 x x \___ + -- + -- 0 1 x x /___ + -- + -- 1 0 0 0 \\\\ + -- + -- 1 0 0 1 \___ + -- + -- 1 0 1 0 \/\/ + -- ___ + -- 1 0 1 1 \ + -- + -- 1 1 0 0 //// + -- ___ + -- 1 1 0 1 / + -- + -- 1 1 1 0 /\/\ + -- + -- 1 1 1 1 /___ + if (env_reset = '1') then + -- load initial state + if (reg(13)(2) = '0') then -- attack + env_vol <= "11111"; + env_inc <= '0'; -- -1 + else + env_vol <= "00000"; + env_inc <= '1'; -- +1 + end if; + env_hold <= '0'; + + elsif rising_edge(CLK) then + is_bot := (env_vol = "00000"); + is_bot_p1 := (env_vol = "00001"); + is_top_m1 := (env_vol = "11110"); + is_top := (env_vol = "11111"); + + if (ENA = '1') then + if (env_ena = '1') then + if (env_hold = '0') then + if (env_inc = '1') then + env_vol <= (env_vol + "00001"); + else + env_vol <= (env_vol + "11111"); + end if; + end if; + + -- envelope shape control. + if (reg(13)(3) = '0') then + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + else + if is_top then env_hold <= '1'; end if; + end if; + else + if (reg(13)(0) = '1') then -- hold = 1 + if (env_inc = '0') then -- down + if (reg(13)(1) = '1') then -- alt + if is_bot then env_hold <= '1'; end if; + else + if is_bot_p1 then env_hold <= '1'; end if; + end if; + else + if (reg(13)(1) = '1') then -- alt + if is_top then env_hold <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + end if; + end if; + + elsif (reg(13)(1) = '1') then -- alternate + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + if is_bot then env_hold <= '0'; env_inc <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + if is_top then env_hold <= '0'; env_inc <= '0'; end if; + end if; + end if; + + end if; + end if; + end if; + end if; + end process; + + p_chan_mixer : process(cnt_div, reg, tone_gen_op) + begin + tone_ena_l <= '1'; tone_src <= '1'; + noise_ena_l <= '1'; chan_vol <= "00000"; + case cnt_div(1 downto 0) is + when "00" => + tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0); + noise_ena_l <= reg(7)(3); + when "01" => + tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0); + noise_ena_l <= reg(7)(4); + when "10" => + tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0); + noise_ena_l <= reg(7)(5); + when "11" => null; -- tone gen outputs become valid on this clock + when others => null; + end case; + end process; + + p_op_mixer : process + variable chan_mixed : std_logic; + variable chan_amp : std_logic_vector(4 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + + chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op); + + chan_amp := (others => '0'); + if (chan_mixed = '1') then + if (chan_vol(4) = '0') then + if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet + chan_amp := "00000"; + else + chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone) + end if; + else + chan_amp := env_vol(4 downto 0); + end if; + end if; + + dac_amp <= x"00"; + case chan_amp is + when "11111" => dac_amp <= x"FF"; + when "11110" => dac_amp <= x"D9"; + when "11101" => dac_amp <= x"BA"; + when "11100" => dac_amp <= x"9F"; + when "11011" => dac_amp <= x"88"; + when "11010" => dac_amp <= x"74"; + when "11001" => dac_amp <= x"63"; + when "11000" => dac_amp <= x"54"; + when "10111" => dac_amp <= x"48"; + when "10110" => dac_amp <= x"3D"; + when "10101" => dac_amp <= x"34"; + when "10100" => dac_amp <= x"2C"; + when "10011" => dac_amp <= x"25"; + when "10010" => dac_amp <= x"1F"; + when "10001" => dac_amp <= x"1A"; + when "10000" => dac_amp <= x"16"; + when "01111" => dac_amp <= x"13"; + when "01110" => dac_amp <= x"10"; + when "01101" => dac_amp <= x"0D"; + when "01100" => dac_amp <= x"0B"; + when "01011" => dac_amp <= x"09"; + when "01010" => dac_amp <= x"08"; + when "01001" => dac_amp <= x"07"; + when "01000" => dac_amp <= x"06"; + when "00111" => dac_amp <= x"05"; + when "00110" => dac_amp <= x"04"; + when "00101" => dac_amp <= x"03"; + when "00100" => dac_amp <= x"03"; + when "00011" => dac_amp <= x"02"; + when "00010" => dac_amp <= x"02"; + when "00001" => dac_amp <= x"01"; + when "00000" => dac_amp <= x"00"; + when others => null; + end case; + + cnt_div_t1 <= cnt_div; + end if; + end process; + + p_audio_output : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + O_AUDIO <= (others => '0'); + O_CHAN <= (others => '0'); + elsif rising_edge(CLK) then + + if (ENA = '1') then + O_AUDIO <= dac_amp(7 downto 0); + O_CHAN <= cnt_div_t1(1 downto 0); + end if; + end if; + end process; + + p_io_ports : process(reg) + begin + O_IOA <= reg(14); + O_IOA_OE_L <= not reg(7)(6); + O_IOB <= reg(15); + O_IOB_OE_L <= not reg(7)(7); + end process; + + p_io_ports_inreg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then -- resync + ioa_inreg <= I_IOA; + iob_inreg <= I_IOB; + end if; + end process; +end architecture RTL; diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/build_id.tcl b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/dpram.vhd b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..78823ec4 --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/dpram.vhd @@ -0,0 +1,58 @@ +------------------------------------------------------------------------------- +-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $ +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dpram is + +generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 +); +port ( + clk_a_i : in std_logic; + en_a_i : in std_logic; + we_i : in std_logic; + addr_a_i : in std_logic_vector(addr_width_g-1 downto 0); + data_a_i : in std_logic_vector(data_width_g-1 downto 0); + data_a_o : out std_logic_vector(data_width_g-1 downto 0); + clk_b_i : in std_logic; + addr_b_i : in std_logic_vector(addr_width_g-1 downto 0); + data_b_o : out std_logic_vector(data_width_g-1 downto 0) +); + +end dpram; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dpram is + + type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0); + signal ram_q : ram_t; + +begin + + mem_a: process (clk_a_i) + begin + if rising_edge(clk_a_i) then + if we_i = '1' and en_a_i = '1' then + ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i; + data_a_o <= data_a_i; + else + data_a_o <= ram_q(to_integer(unsigned(addr_a_i))); + end if; + end if; + end process mem_a; + + mem_b: process (clk_b_i) + begin + if rising_edge(clk_b_i) then + data_b_o <= ram_q(to_integer(unsigned(addr_b_i))); + end if; + end process mem_b; + +end rtl; diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/i82c55.vhd b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/i82c55.vhd new file mode 100644 index 00000000..d415d932 --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/i82c55.vhd @@ -0,0 +1,686 @@ +-- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- + +library ieee ; + use ieee.std_logic_1164.all ; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity I82C55 is + port ( + + I_ADDR : in std_logic_vector(1 downto 0); -- A1-A0 + I_DATA : in std_logic_vector(7 downto 0); -- D7-D0 + O_DATA : out std_logic_vector(7 downto 0); + O_DATA_OE_L : out std_logic; + + I_CS_L : in std_logic; + I_RD_L : in std_logic; + I_WR_L : in std_logic; + + I_PA : in std_logic_vector(7 downto 0); + O_PA : out std_logic_vector(7 downto 0); + O_PA_OE_L : out std_logic_vector(7 downto 0); + + I_PB : in std_logic_vector(7 downto 0); + O_PB : out std_logic_vector(7 downto 0); + O_PB_OE_L : out std_logic_vector(7 downto 0); + + I_PC : in std_logic_vector(7 downto 0); + O_PC : out std_logic_vector(7 downto 0); + O_PC_OE_L : out std_logic_vector(7 downto 0); + + RESET : in std_logic; + ENA : in std_logic; -- (CPU) clk enable + CLK : in std_logic + ); +end; + +architecture RTL of I82C55 is + + -- registers + signal bit_mask : std_logic_vector(7 downto 0); + signal r_porta : std_logic_vector(7 downto 0); + signal r_portb : std_logic_vector(7 downto 0); + signal r_portc : std_logic_vector(7 downto 0); + signal r_control : std_logic_vector(7 downto 0); + -- + signal porta_we : std_logic; + signal portb_we : std_logic; + signal porta_re : std_logic; + signal portb_re : std_logic; + -- + signal porta_we_t1 : std_logic; + signal portb_we_t1 : std_logic; + signal porta_re_t1 : std_logic; + signal portb_re_t1 : std_logic; + -- + signal porta_we_rising : boolean; + signal portb_we_rising : boolean; + signal porta_re_rising : boolean; + signal portb_re_rising : boolean; + -- + signal groupa_mode : std_logic_vector(1 downto 0); -- port a/c upper + signal groupb_mode : std_logic; -- port b/c lower + -- + signal porta_read : std_logic_vector(7 downto 0); + signal portb_read : std_logic_vector(7 downto 0); + signal portc_read : std_logic_vector(7 downto 0); + signal control_read : std_logic_vector(7 downto 0); + signal mode_clear : std_logic; + -- + signal a_inte1 : std_logic; + signal a_inte2 : std_logic; + signal b_inte : std_logic; + -- + signal a_intr : std_logic; + signal a_obf_l : std_logic; + signal a_ibf : std_logic; + signal a_ack_l : std_logic; + signal a_stb_l : std_logic; + signal a_ack_l_t1 : std_logic; + signal a_stb_l_t1 : std_logic; + -- + signal b_intr : std_logic; + signal b_obf_l : std_logic; + signal b_ibf : std_logic; + signal b_ack_l : std_logic; + signal b_stb_l : std_logic; + signal b_ack_l_t1 : std_logic; + signal b_stb_l_t1 : std_logic; + -- + signal a_ack_l_rising : boolean; + signal a_stb_l_rising : boolean; + signal b_ack_l_rising : boolean; + signal b_stb_l_rising : boolean; + -- + signal porta_ipreg : std_logic_vector(7 downto 0); + signal portb_ipreg : std_logic_vector(7 downto 0); +begin + -- + -- mode 0 - basic input/output + -- mode 1 - strobed input/output + -- mode 2/3 - bi-directional bus + -- + -- control word (write) + -- + -- D7 mode set flag 1 = active + -- D6..5 GROUPA mode selection (mode 0,1,2) + -- D4 GROUPA porta 1 = input, 0 = output + -- D3 GROUPA portc upper 1 = input, 0 = output + -- D2 GROUPB mode selection (mode 0 ,1) + -- D1 GROUPB portb 1 = input, 0 = output + -- D0 GROUPB portc lower 1 = input, 0 = output + -- + -- D7 bit set/reset 0 = active + -- D6..4 x + -- D3..1 bit select + -- d0 1 = set, 0 - reset + -- + -- all output registers including status are reset when mode is changed + --1. Port A: + --All Modes: Output data is cleared, input data is not cleared. + + --2. Port B: + --Mode 0: Output data is cleared, input data is not cleared. + --Mode 1 and 2: Both output and input data are cleared. + + --3. Port C: + --Mode 0:Output data is cleared, input data is not cleared. + --Mode 1 and 2: IBF and INTR are cleared and OBF# is set. + --Outputs in Port C which are not used for handshaking or interrupt signals are cleared. + --Inputs such as STB#, ACK#, or "spare" inputs are not affected. The interrupts for Ports A and B are disabled. + + p_bit_mask : process(I_DATA) + begin + bit_mask <= x"01"; + case I_DATA(3 downto 1) is + when "000" => bit_mask <= x"01"; + when "001" => bit_mask <= x"02"; + when "010" => bit_mask <= x"04"; + when "011" => bit_mask <= x"08"; + when "100" => bit_mask <= x"10"; + when "101" => bit_mask <= x"20"; + when "110" => bit_mask <= x"40"; + when "111" => bit_mask <= x"80"; + when others => null; + end case; + end process; + + p_write_reg_reset : process(RESET, CLK) + variable r_portc_masked : std_logic_vector(7 downto 0); + variable r_portc_setclr : std_logic_vector(7 downto 0); + begin + if (RESET = '1') then + r_porta <= x"00"; + r_portb <= x"00"; + r_portc <= x"00"; + r_control <= x"9B"; -- 10011011 + mode_clear <= '1'; + elsif rising_edge(CLK) then + + r_portc_masked := (not bit_mask) and r_portc; + for i in 0 to 7 loop + r_portc_setclr(i) := bit_mask(i) and I_DATA(0); + end loop; + + if (ENA = '1') then + mode_clear <= '0'; + if (I_CS_L = '0') and (I_WR_L = '0') then + case I_ADDR is + when "00" => r_porta <= I_DATA; + when "01" => r_portb <= I_DATA; + when "10" => r_portc <= I_DATA; + + when "11" => if (I_DATA(7) = '0') then -- set/clr + r_portc <= r_portc_masked or r_portc_setclr; + else + --mode_clear <= '1'; + --r_porta <= x"00"; + --r_portb <= x"00"; -- clear port b input reg + --r_portc <= x"00"; -- clear control sigs + r_control <= I_DATA; -- load new mode + end if; + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_decode_control : process(r_control) + begin + groupa_mode <= r_control(6 downto 5); + groupb_mode <= r_control(2); + end process; + + p_oe : process(I_CS_L, I_RD_L) + begin + O_DATA_OE_L <= '1'; + if (I_CS_L = '0') and (I_RD_L = '0') then + O_DATA_OE_L <= '0'; + end if; + end process; + + p_read : process(I_ADDR, porta_read, portb_read, portc_read, control_read) + begin + O_DATA <= x"00"; -- default + --if (I_CS_L = '0') and (I_RD_L = '0') then -- not required + case I_ADDR is + when "00" => O_DATA <= porta_read; + when "01" => O_DATA <= portb_read; + when "10" => O_DATA <= portc_read; + when "11" => O_DATA <= control_read; + when others => null; + end case; + --end if; + end process; + control_read(7) <= '1'; -- always 1 + control_read(6 downto 0) <= r_control(6 downto 0); + + p_rw_control : process(I_CS_L, I_RD_L, I_WR_L, I_ADDR) + begin + porta_we <= '0'; + portb_we <= '0'; + porta_re <= '0'; + portb_re <= '0'; + + if (I_CS_L = '0') and (I_ADDR = "00") then + porta_we <= not I_WR_L; + porta_re <= not I_RD_L; + end if; + + if (I_CS_L = '0') and (I_ADDR = "01") then + portb_we <= not I_WR_L; + portb_re <= not I_RD_L; + end if; + end process; + + p_rw_control_reg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + porta_we_t1 <= porta_we; + portb_we_t1 <= portb_we; + porta_re_t1 <= porta_re; + portb_re_t1 <= portb_re; + + a_stb_l_t1 <= a_stb_l; + a_ack_l_t1 <= a_ack_l; + b_stb_l_t1 <= b_stb_l; + b_ack_l_t1 <= b_ack_l; + end if; + end process; + + porta_we_rising <= (porta_we = '0') and (porta_we_t1 = '1'); -- falling as inverted + portb_we_rising <= (portb_we = '0') and (portb_we_t1 = '1'); -- " + porta_re_rising <= (porta_re = '0') and (porta_re_t1 = '1'); -- falling as inverted + portb_re_rising <= (portb_re = '0') and (portb_re_t1 = '1'); -- " + -- + a_stb_l_rising <= (a_stb_l = '1') and (a_stb_l_t1 = '0'); + a_ack_l_rising <= (a_ack_l = '1') and (a_ack_l_t1 = '0'); + b_stb_l_rising <= (b_stb_l = '1') and (b_stb_l_t1 = '0'); + b_ack_l_rising <= (b_ack_l = '1') and (b_ack_l_t1 = '0'); + -- + -- GROUP A + -- in mode 1 + -- + -- d4=1 (porta = input) + -- pc7,6 io (d3=1 input, d3=0 output) + -- pc5 output a_ibf + -- pc4 input a_stb_l + -- pc3 output a_intr + -- + -- d4=0 (porta = output) + -- pc7 output a_obf_l + -- pc6 input a_ack_l + -- pc5,4 io (d3=1 input, d3=0 output) + -- pc3 output a_intr + -- + -- GROUP B + -- in mode 1 + -- d1=1 (portb = input) + -- pc2 input b_stb_l + -- pc1 output b_ibf + -- pc0 output b_intr + -- + -- d1=0 (portb = output) + -- pc2 input b_ack_l + -- pc1 output b_obf_l + -- pc0 output b_intr + + + -- WHEN AN INPUT + -- + -- stb_l a low on this input latches input data + -- ibf a high on this output indicates data latched. set by stb_l and reset by rising edge of RD_L + -- intr a high on this output indicates interrupt. set by stb_l high, ibf high and inte high. reset by falling edge of RD_L + -- inte A controlled by bit/set PC4 + -- inte B controlled by bit/set PC2 + + -- WHEN AN OUTPUT + -- + -- obf_l output will go low when cpu has written data + -- ack_l input - a low on this clears obf_l + -- intr output set when ack_l is high, obf_l is high and inte is one. reset by falling edge of WR_L + -- inte A controlled by bit/set PC6 + -- inte B controlled by bit/set PC2 + + -- GROUP A + -- in mode 2 + -- + -- porta = IO + -- + -- control bits 2..0 still control groupb/c lower 2..0 + -- + -- + -- PC7 output a_obf + -- PC6 input a_ack_l + -- PC5 output a_ibf + -- PC4 input a_stb_l + -- PC3 is still interrupt out + p_control_flags : process(RESET, CLK) + variable we : boolean; + variable set1 : boolean; + variable set2 : boolean; + begin + if (RESET = '1') then + a_obf_l <= '1'; + a_inte1 <= '0'; + a_ibf <= '0'; + a_inte2 <= '0'; + a_intr <= '0'; + -- + b_inte <= '0'; + b_obf_l <= '1'; + b_ibf <= '0'; + b_intr <= '0'; + elsif rising_edge(CLK) then + we := (I_CS_L = '0') and (I_WR_L = '0') and (I_ADDR = "11") and (I_DATA(7) = '0'); + + if (ENA = '1') then + if (mode_clear = '1') then + a_obf_l <= '1'; + a_inte1 <= '0'; + a_ibf <= '0'; + a_inte2 <= '0'; + a_intr <= '0'; + -- + b_inte <= '0'; + b_obf_l <= '1'; + b_ibf <= '0'; + b_intr <= '0'; + else + if (bit_mask(7) = '1') and we then + a_obf_l <= I_DATA(0); + else + if porta_we_rising then + a_obf_l <= '0'; + elsif (a_ack_l = '0') then + a_obf_l <= '1'; + end if; + end if; + -- + if (bit_mask(6) = '1') and we then a_inte1 <= I_DATA(0); end if; -- bus set when mode1 & input? + -- + if (bit_mask(5) = '1') and we then + a_ibf <= I_DATA(0); + else + if porta_re_rising then + a_ibf <= '0'; + elsif (a_stb_l = '0') then + a_ibf <= '1'; + end if; + end if; + -- + if (bit_mask(4) = '1') and we then a_inte2 <= I_DATA(0); end if; -- bus set when mode1 & output? + -- + set1 := a_ack_l_rising and (a_obf_l = '1') and (a_inte1 = '1'); + set2 := a_stb_l_rising and (a_ibf = '1') and (a_inte2 = '1'); + -- + if (bit_mask(3) = '1') and we then + a_intr <= I_DATA(0); + else + if (groupa_mode(1) = '1') then + if (porta_we = '1') or (porta_re = '1') then + a_intr <= '0'; + elsif set1 or set2 then + a_intr <= '1'; + end if; + else + if (r_control(4) = '0') then -- output + if (porta_we = '1') then -- falling ? + a_intr <= '0'; + elsif set1 then + a_intr <= '1'; + end if; + elsif (r_control(4) = '1') then -- input + if (porta_re = '1') then -- falling ? + a_intr <= '0'; + elsif set2 then + a_intr <= '1'; + end if; + end if; + end if; + end if; + -- + if (bit_mask(2) = '1') and we then b_inte <= I_DATA(0); end if; -- bus set? + + if (bit_mask(1) = '1') and we then + b_obf_l <= I_DATA(0); + else + if (r_control(1) = '0') then -- output + if portb_we_rising then + b_obf_l <= '0'; + elsif (b_ack_l = '0') then + b_obf_l <= '1'; + end if; + else + if portb_re_rising then + b_ibf <= '0'; + elsif (b_stb_l = '0') then + b_ibf <= '1'; + end if; + end if; + end if; + + if (bit_mask(0) = '1') and we then + b_intr <= I_DATA(0); + else + if (r_control(1) = '0') then -- output + if (portb_we = '1') then -- falling ? + b_intr <= '0'; + elsif b_ack_l_rising and (b_obf_l = '1') and (b_inte = '1') then + b_intr <= '1'; + end if; + else + if (portb_re = '1') then -- falling ? + b_intr <= '0'; + elsif b_stb_l_rising and (b_ibf = '1') and (b_inte = '1') then + b_intr <= '1'; + end if; + end if; + end if; + + end if; + end if; + end if; + end process; + + p_porta : process(r_control, groupa_mode, r_porta, I_PA, porta_ipreg, a_ack_l) + begin + -- D4 GROUPA porta 1 = input, 0 = output + O_PA <= x"FF"; -- if not driven, float high + O_PA_OE_L <= x"FF"; + porta_read <= x"00"; + + if (groupa_mode = "00") then -- simple io + if (r_control(4) = '0') then -- output + O_PA <= r_porta; + O_PA_OE_L <= x"00"; + end if; + porta_read <= I_PA; + elsif (groupa_mode = "01") then -- strobed + if (r_control(4) = '0') then -- output + O_PA <= r_porta; + O_PA_OE_L <= x"00"; + end if; + porta_read <= porta_ipreg; + else -- if (groupa_mode(1) = '1') then -- bi dir + if (a_ack_l = '0') then -- output enable + O_PA <= r_porta; + O_PA_OE_L <= x"00"; + end if; + porta_read <= porta_ipreg; -- latched data + end if; + + end process; + + p_portb : process(r_control, groupb_mode, r_portb, I_PB, portb_ipreg) + begin + O_PB <= x"FF"; -- if not driven, float high + O_PB_OE_L <= x"FF"; + portb_read <= x"00"; + + if (groupb_mode = '0') then -- simple io + if (r_control(1) = '0') then -- output + O_PB <= r_portb; + O_PB_OE_L <= x"00"; + end if; + portb_read <= I_PB; + else -- strobed mode + if (r_control(1) = '0') then -- output + O_PB <= r_portb; + O_PB_OE_L <= x"00"; + end if; + portb_read <= portb_ipreg; + end if; + end process; + + p_portc_out : process(r_portc, r_control, groupa_mode, groupb_mode, + a_obf_l, a_ibf, a_intr,b_obf_l, b_ibf, b_intr) + begin + O_PC <= x"FF"; -- if not driven, float high + O_PC_OE_L <= x"FF"; + + -- bits 7..4 + if (groupa_mode = "00") then -- simple io + if (r_control(3) = '0') then -- output + O_PC (7 downto 4) <= r_portc(7 downto 4); + O_PC_OE_L(7 downto 4) <= x"0"; + end if; + elsif (groupa_mode = "01") then -- mode1 + + if (r_control(4) = '0') then -- port a output + O_PC (7) <= a_obf_l; + O_PC_OE_L(7) <= '0'; + -- 6 is ack_l input + if (r_control(3) = '0') then -- port c output + O_PC (5 downto 4) <= r_portc(5 downto 4); + O_PC_OE_L(5 downto 4) <= "00"; + end if; + else -- port a input + if (r_control(3) = '0') then -- port c output + O_PC (7 downto 6) <= r_portc(7 downto 6); + O_PC_OE_L(7 downto 6) <= "00"; + end if; + O_PC (5) <= a_ibf; + O_PC_OE_L(5) <= '0'; + -- 4 is stb_l input + end if; + + else -- if (groupa_mode(1) = '1') then -- mode2 + O_PC (7) <= a_obf_l; + O_PC_OE_L(7) <= '0'; + -- 6 is ack_l input + O_PC (5) <= a_ibf; + O_PC_OE_L(5) <= '0'; + -- 4 is stb_l input + end if; + + -- bit 3 (controlled by group a) + if (groupa_mode = "00") then -- group a steals this bit + --if (groupb_mode = '0') then -- we will let bit 3 be driven, data sheet is a bit confused about this + if (r_control(0) = '0') then -- ouput (note, groupb control bit) + O_PC (3) <= r_portc(3); + O_PC_OE_L(3) <= '0'; + end if; + -- + else -- stolen + O_PC (3) <= a_intr; + O_PC_OE_L(3) <= '0'; + end if; + + -- bits 2..0 + if (groupb_mode = '0') then -- simple io + if (r_control(0) = '0') then -- output + O_PC (2 downto 0) <= r_portc(2 downto 0); + O_PC_OE_L(2 downto 0) <= "000"; + end if; + else + -- mode 1 + -- 2 is input + if (r_control(1) = '0') then -- output + O_PC (1) <= b_obf_l; + O_PC_OE_L(1) <= '0'; + else -- input + O_PC (1) <= b_ibf; + O_PC_OE_L(1) <= '0'; + end if; + O_PC (0) <= b_intr; + O_PC_OE_L(0) <= '0'; + end if; + end process; + + p_portc_in : process(r_portc, I_PC, r_control, groupa_mode, groupb_mode, a_ibf, b_obf_l, + a_obf_l, a_inte1, a_inte2, a_intr, b_inte, b_ibf, b_intr) + begin + portc_read <= x"00"; + + a_stb_l <= '1'; + a_ack_l <= '1'; + b_stb_l <= '1'; + b_ack_l <= '1'; + + if (groupa_mode = "01") then -- mode1 or 2 + if (r_control(4) = '0') then -- port a output + a_ack_l <= I_PC(6); + else -- port a input + a_stb_l <= I_PC(4); + end if; + elsif (groupa_mode(1) = '1') then -- mode 2 + a_ack_l <= I_PC(6); + a_stb_l <= I_PC(4); + end if; + + if (groupb_mode = '1') then + if (r_control(1) = '0') then -- output + b_ack_l <= I_PC(2); + else -- input + b_stb_l <= I_PC(2); + end if; + end if; + + if (groupa_mode = "00") then -- simple io + portc_read(7 downto 3) <= I_PC(7 downto 3); + elsif (groupa_mode = "01") then + if (r_control(4) = '0') then -- port a output + portc_read(7 downto 3) <= a_obf_l & a_inte1 & I_PC(5 downto 4) & a_intr; + else -- input + portc_read(7 downto 3) <= I_PC(7 downto 6) & a_ibf & a_inte2 & a_intr; + end if; + else -- mode 2 + portc_read(7 downto 3) <= a_obf_l & a_inte1 & a_ibf & a_inte2 & a_intr; + end if; + + if (groupb_mode = '0') then -- simple io + portc_read(2 downto 0) <= I_PC(2 downto 0); + else + if (r_control(1) = '0') then -- output + portc_read(2 downto 0) <= b_inte & b_obf_l & b_intr; + else -- input + portc_read(2 downto 0) <= b_inte & b_ibf & b_intr; + end if; + end if; + end process; + + p_ipreg : process + begin + wait until rising_edge(CLK); + -- pc4 input a_stb_l + -- pc2 input b_stb_l + + if (ENA = '1') then + if (a_stb_l = '0') then + porta_ipreg <= I_PA; + end if; + + if (mode_clear = '1') then + portb_ipreg <= (others => '0'); + elsif (b_stb_l = '0') then + portb_ipreg <= I_PB; + end if; + end if; + end process; + +end architecture RTL; diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/pll.qip b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/pll.v b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/pll.v new file mode 100644 index 00000000..1d3529bd --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/pll.v @@ -0,0 +1,320 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire sub_wire0; + wire [4:0] sub_wire1; + wire [0:0] sub_wire5 = 1'h0; + wire locked = sub_wire0; + wire [0:0] sub_wire2 = sub_wire1[0:0]; + wire c0 = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire4), + .locked (sub_wire0), + .clk (sub_wire1), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 78, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 71, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "78" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.576923" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "71" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.57627100" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "78" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "71" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/rom/ROM_LUT.vhd b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/rom/ROM_LUT.vhd new file mode 100644 index 00000000..d752a1e2 --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/rom/ROM_LUT.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_LUT is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_LUT is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"1C",X"36",X"05",X"00",X"79",X"A7",X"07",X"00",X"5B",X"F8",X"27",X"00",X"A5",X"07",X"3F", + X"00",X"FF",X"87",X"38",X"00",X"27",X"FF",X"C1",X"00",X"1B",X"3F",X"80",X"00",X"18",X"1F",X"86"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/rom/ROM_OBJ_0.vhd b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/rom/ROM_OBJ_0.vhd new file mode 100644 index 00000000..b5081774 --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/rom/ROM_OBJ_0.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_OBJ_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_OBJ_0 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"7C",X"C6",X"C6",X"82",X"C6",X"C6",X"7C",X"00",X"00",X"06",X"FE",X"FE",X"86",X"00",X"00", + X"00",X"66",X"F2",X"BA",X"9E",X"8E",X"C6",X"62",X"00",X"7C",X"FE",X"92",X"92",X"92",X"C6",X"44", + X"00",X"18",X"FE",X"1E",X"1A",X"D8",X"F8",X"F8",X"00",X"9C",X"BE",X"B2",X"B2",X"B2",X"F6",X"F6", + X"00",X"4C",X"DE",X"92",X"92",X"92",X"FE",X"7C",X"00",X"E0",X"F0",X"98",X"8E",X"86",X"C2",X"E0", + X"00",X"6C",X"FE",X"92",X"92",X"92",X"FE",X"6C",X"00",X"7C",X"FE",X"92",X"92",X"92",X"F6",X"64", + X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"28",X"02",X"A4",X"25",X"A4",X"19",X"40",X"14", + X"00",X"00",X"00",X"18",X"18",X"04",X"03",X"02",X"00",X"00",X"00",X"18",X"18",X"20",X"C0",X"40", + X"02",X"03",X"04",X"18",X"18",X"00",X"00",X"00",X"40",X"C0",X"20",X"18",X"18",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"7E",X"D6",X"D0",X"D0",X"D0",X"D6",X"7E", + X"00",X"44",X"EE",X"BA",X"92",X"82",X"FE",X"FE",X"00",X"44",X"C6",X"82",X"82",X"82",X"FE",X"7C", + X"00",X"7C",X"FE",X"82",X"82",X"BA",X"FE",X"FE",X"00",X"C6",X"C6",X"92",X"92",X"92",X"FE",X"FE", + X"00",X"C0",X"C0",X"90",X"92",X"96",X"FE",X"FE",X"00",X"6C",X"EE",X"8A",X"8A",X"82",X"FE",X"7C", + X"00",X"FE",X"FE",X"D0",X"10",X"16",X"FE",X"FE",X"00",X"00",X"C6",X"FE",X"FE",X"FE",X"C6",X"00", + X"00",X"FC",X"FE",X"C2",X"06",X"0E",X"0C",X"08",X"00",X"82",X"C6",X"EE",X"38",X"92",X"FE",X"FE", + X"00",X"1E",X"0E",X"06",X"02",X"E2",X"FE",X"FE",X"00",X"FE",X"C6",X"60",X"30",X"60",X"C6",X"FE", + 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100644 index 00000000..578147b3 --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/rom/ROM_OBJ_1.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_OBJ_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_OBJ_1 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"7C",X"C6",X"C6",X"82",X"C6",X"C6",X"7C",X"00",X"00",X"06",X"FE",X"FE",X"86",X"00",X"00", + X"00",X"66",X"F2",X"BA",X"9E",X"8E",X"C6",X"62",X"00",X"7C",X"FE",X"92",X"92",X"92",X"C6",X"44", + X"00",X"18",X"FE",X"1E",X"1A",X"D8",X"F8",X"F8",X"00",X"9C",X"BE",X"B2",X"B2",X"B2",X"F6",X"F6", + X"00",X"4C",X"DE",X"92",X"92",X"92",X"FE",X"7C",X"00",X"E0",X"F0",X"98",X"8E",X"86",X"C2",X"E0", + X"00",X"6C",X"FE",X"92",X"92",X"92",X"FE",X"6C",X"00",X"7C",X"FE",X"92",X"92",X"92",X"F6",X"64", + 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index 00000000..a93b3707 --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/rom/ROM_PGM.vhd @@ -0,0 +1,1558 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM is +port ( + clk : in std_logic; + addr : in std_logic_vector(14 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM is + type rom is array(0 to 24575) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"F3",X"C3",X"69",X"00",X"FF",X"FF",X"FF",X"C3",X"3E",X"09",X"FF",X"FF",X"FF",X"FF",X"FF", + X"C3",X"1F",X"0A",X"FF",X"FF",X"FF",X"FF",X"FF",X"C3",X"2B",X"0A",X"FF",X"FF",X"FF",X"FF",X"FF", + X"C3",X"3E",X"0A",X"FF",X"FF",X"FF",X"FF",X"FF",X"C3",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF", + X"C3",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"C3",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + 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X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/rom/ROM_SND_0.vhd b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/rom/ROM_SND_0.vhd new file mode 100644 index 00000000..a32429c7 --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/rom/ROM_SND_0.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_SND_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_SND_0 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"F3",X"31",X"00",X"81",X"C3",X"5B",X"0A",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + 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100644 index 00000000..1ca42420 --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/rom/ROM_SND_1.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_SND_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_SND_1 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"0B",X"06",X"00",X"23",X"81",X"0B",X"07",X"00",X"25",X"81",X"01",X"03",X"03",X"81",X"F1",X"10", + X"19",X"01",X"01",X"01",X"01",X"01",X"00",X"1D",X"10",X"10",X"10",X"18",X"03",X"03",X"03",X"03", + X"03",X"03",X"1F",X"00",X"10",X"01",X"1B",X"09",X"07",X"06",X"FF",X"03",X"81",X"0B",X"06",X"00", + X"23",X"81",X"0B",X"07",X"00",X"25",X"81",X"01",X"03",X"03",X"81",X"F1",X"10",X"19",X"C8",X"C8", + X"64",X"01",X"00",X"FA",X"1D",X"0F",X"0F",X"0F",X"18",X"02",X"02",X"02",X"03",X"03",X"03",X"1B", + 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X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/scramble.vhd b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/scramble.vhd new file mode 100644 index 00000000..5ef588d6 --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/scramble.vhd @@ -0,0 +1,471 @@ +-- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity scramble is + port ( + -- + O_VIDEO_R : out std_logic_vector(3 downto 0); + O_VIDEO_G : out std_logic_vector(3 downto 0); + O_VIDEO_B : out std_logic_vector(3 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + -- + -- to audio board + -- + O_ADDR : out std_logic_vector(15 downto 0); + O_DATA : out std_logic_vector( 7 downto 0); + I_DATA : in std_logic_vector( 7 downto 0); + I_DATA_OE_L : in std_logic; + O_RD_L : out std_logic; + O_WR_L : out std_logic; + O_IOPC7 : out std_logic; + O_RESET_WD_L : out std_logic; + -- + ENA : in std_logic; + ENAB : in std_logic; + ENA_12 : in std_logic; + -- + RESET : in std_logic; -- active high + CLK : in std_logic + ); +end; + +architecture RTL of scramble is + + type array_4x8 is array (0 to 3) of std_logic_vector(7 downto 0); + -- timing + signal hcnt : std_logic_vector(8 downto 0) := "010000000"; -- 80 + signal vcnt : std_logic_vector(8 downto 0) := "011111000"; -- 0F8 + + signal reset_wd_l : std_logic; + + -- timing decode + signal do_hsync : boolean; + signal set_vblank : boolean; + signal vsync : std_logic; + signal hsync : std_logic; + signal vblank : std_logic; + signal hblank : std_logic; + -- + -- cpu + signal cpu_ena : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_wr_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_wait_l : std_logic; + signal cpu_int_l : std_logic; + signal cpu_nmi_l : std_logic; + signal cpu_busrq_l : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + + signal page_4to7_l : std_logic; + + signal wren : std_logic; + + signal objen_l : std_logic; + signal waen_l : std_logic; + + signal objramrd_l : std_logic; + signal vramrd_l : std_logic; + + signal select_l : std_logic; + signal objramwr_l : std_logic; + signal vramwr_l : std_logic; + + -- control reg + signal control_reg : std_logic_vector(7 downto 0); + signal intst_l : std_logic; + signal iopc7 : std_logic; + signal pout1 : std_logic; + signal starson : std_logic; + signal hcma : std_logic; + signal vcma : std_logic; + + signal pgm_rom_dout : array_4x8; + signal rom_dout : std_logic_vector(7 downto 0); + signal ram_dout : std_logic_vector(7 downto 0); + signal ram_ena : std_logic; + + signal vram_data : std_logic_vector(7 downto 0); + +begin + + O_HBLANK <= hblank; + O_VBLANK <= vblank; + + -- + -- video timing + -- + p_hvcnt : process + variable hcarry,vcarry : boolean; + begin + wait until rising_edge(CLK); + if (ENA = '1') then + hcarry := (hcnt = "111111111"); + if hcarry then + hcnt <= "010000000"; -- 080 + else + hcnt <= hcnt +"1"; + end if; + -- hcnt 8 on circuit is 256H_L + vcarry := (vcnt = "111111111"); + if do_hsync then + if vcarry then + vcnt <= "011111000"; -- 0F8 + else + vcnt <= vcnt +"1"; + end if; + end if; + end if; + end process; + + p_sync_comb : process(hcnt, vcnt) + begin + vsync <= not vcnt(8); + do_hsync <= (hcnt = "010101111"); -- 0AF + set_vblank <= (vcnt = "111101111"); -- 1EF + end process; + + p_sync : process + begin + wait until rising_edge(CLK); + -- Timing hardware is coded differently to the real hw + -- to avoid the use of multiple clocks. Result is identical. + if (ENA = '1') then + if (hcnt = "010000001") then -- 081 + hblank <= '1'; + elsif (hcnt = "011111111") then -- 0f9 + hblank <= '0'; + end if; + + if do_hsync then + hsync <= '1'; + elsif (hcnt = "011001111") then -- 0CF + hsync <= '0'; + end if; + + if do_hsync then + if set_vblank then -- 1EF + vblank <= '1'; + elsif (vcnt = "100001111") then -- 10F + vblank <= '0'; + end if; + end if; + end if; + end process; + + p_video_timing_reg : process + begin + wait until rising_edge(CLK); + -- match output delay in video module + if (ENA = '1') then + O_HSYNC <= HSYNC; + O_VSYNC <= VSYNC; + end if; + end process; + + p_cpu_ena : process(hcnt, ENA) + begin + -- cpu clocked on rising edge of 1h, late + cpu_ena <= ENA and hcnt(0); -- 1h + end process; + -- + -- video + -- + u_video : entity work.scramble_video + port map ( + -- + I_HCNT => hcnt, + I_VCNT => vcnt, + I_VBLANK => vblank, + I_VSYNC => vsync, + + I_VCMA => vcma, + I_HCMA => hcma, + -- + I_CPU_ADDR => cpu_addr, + I_CPU_DATA => cpu_data_out, + O_VRAM_DATA => vram_data, + -- note, looks like the real hardware cannot read from object ram + -- + I_VRAMWR_L => vramwr_l, + I_VRAMRD_L => vramrd_l, + I_OBJRAMWR_L => objramwr_l, + I_OBJRAMRD_L => objramrd_l, + I_OBJEN_L => objen_l, + -- + I_STARSON => starson, + I_POUT1 => pout1, + -- + O_VIDEO_R => O_VIDEO_R, + O_VIDEO_G => O_VIDEO_G, + O_VIDEO_B => O_VIDEO_B, + -- + ENA => ENA, + ENAB => ENAB, + ENA_12 => ENA_12, + CLK => CLK + ); + + -- other cpu signals + reset_wd_l <= not RESET; -- FIX + + p_cpu_wait : process(vblank, hblank, waen_l) + begin + -- this is done a bit differently, the original had a late + -- clock to the cpu, and as mreq came out a litle early it could assert + -- wait and then gate off the write strobe to vram/objram in time. + -- + -- we are a nice synchronous system therefore we need to do this combinatorially. + -- timing is still ok. + -- + if (vblank = '1') then + cpu_wait_l <='1'; + else + cpu_wait_l <= '1'; + if (hblank = '0') and (waen_l = '0') then + cpu_wait_l <= '0'; + end if; + end if; + end process; + wren <= cpu_wait_l; + + p_cpu_int : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + if (intst_l = '0') then + cpu_nmi_l <= '1'; + else + if do_hsync and set_vblank then + cpu_nmi_l <= '0'; + end if; + end if; + end if; + end process; + + u_cpu : entity work.T80sed + port map ( + RESET_n => reset_wd_l, + CLK_n => clk, + CLKEN => cpu_ena, + WAIT_n => cpu_wait_l, + INT_n => cpu_int_l, + NMI_n => cpu_nmi_l, + BUSRQ_n => cpu_busrq_l, + M1_n => open, + MREQ_n => cpu_mreq_l, + IORQ_n => open, + RD_n => cpu_rd_l, + WR_n => cpu_wr_l, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out + ); + -- + -- primary addr decode + -- + p_mem_decode : process(cpu_rfsh_l, cpu_rd_l, cpu_wr_l, cpu_mreq_l, cpu_addr) + begin + cpu_int_l <= '1'; + cpu_busrq_l <= '1'; + + page_4to7_l <= '1'; + if (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then + if (cpu_addr(15 downto 14) = "10") then page_4to7_l <= '0'; end if; + end if; + + end process; + + p_mem_decode2 : process(cpu_addr, page_4to7_l, cpu_rfsh_l, cpu_rd_l, cpu_wr_l, wren) + begin + waen_l <= '1'; + objen_l <= '1'; + if (page_4to7_l = '0') and (cpu_rfsh_l = '1') then + if (cpu_addr(13 downto 11) = "001") then waen_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "010") then objen_l <= '0'; end if; + end if; + + -- read decode + vramrd_l <= '1'; + objramrd_l <= '1'; + + if (page_4to7_l = '0') and (cpu_rd_l = '0') then + if (cpu_addr(13 downto 11) = "001") then vramrd_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "010") then objramrd_l <= '0'; end if; + end if; + + -- write decode + vramwr_l <= '1'; + objramwr_l <= '1'; + select_l <= '1'; + + if (page_4to7_l = '0') and (cpu_wr_l = '0') and (wren = '1') then + if (cpu_addr(13 downto 11) = "001") then vramwr_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "010") then objramwr_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "101") then select_l <= '0'; end if; -- control reg + end if; + end process; + + p_control_reg : process + variable addr : std_logic_vector(2 downto 0); + variable dec : std_logic_vector(7 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + addr := cpu_addr(2 downto 0); + dec := "00000000"; + if (select_l = '0') then + case addr(2 downto 0) is + when "000" => dec := "00000001"; + when "001" => dec := "00000010"; + when "010" => dec := "00000100"; + when "011" => dec := "00001000"; + when "100" => dec := "00010000"; + when "101" => dec := "00100000"; + when "110" => dec := "01000000"; + when "111" => dec := "10000000"; + when others => null; + end case; + end if; + if (reset_wd_l = '0') then + control_reg <= (others => '0'); + else + for i in 0 to 7 loop + if (dec(i) = '1') then + control_reg(i) <= cpu_data_out(0); + end if; + end loop; + end if; + end if; + end process; + + p_control_reg_assign : process(control_reg) + begin + intst_l <= control_reg(1); + iopc7 <= control_reg(2); + pout1 <= control_reg(3); + starson <= control_reg(4); + hcma <= control_reg(6); + vcma <= control_reg(7); + end process; + + pgm_rom : entity work.ROM_PGM + port map( + clk => CLK, + addr => cpu_addr(14 downto 0), + data => rom_dout + ); + + u_cpu_ram : work.dpram generic map (11,8) + port map + ( + clk_a_i => clk, + en_a_i => ena, + we_i => ram_ena and (not cpu_wr_l), + + addr_a_i => cpu_addr(10 downto 0), + data_a_i => cpu_data_out, + + clk_b_i => clk, + addr_b_i => cpu_addr(10 downto 0), + data_b_o => ram_dout + ); + + p_ram_ctrl : process(cpu_addr, page_4to7_l) + begin + ram_ena <= '0'; + if (page_4to7_l = '0') and (cpu_addr(13 downto 11) = "000") then + ram_ena <= '1'; + end if; + end process; + + p_cpu_data_in_mux : process(cpu_addr, cpu_rd_l, cpu_mreq_l, cpu_rfsh_l, ram_dout, rom_dout, vramrd_l, vram_data, I_DATA_OE_L, I_DATA ) + variable ram_addr : std_logic_vector(1 downto 0); + begin + ram_addr := "10"; + cpu_data_in <= (others => '0'); + if (vramrd_l = '0') then + cpu_data_in <= vram_data; + -- + elsif (I_DATA_OE_L = '0') then + cpu_data_in <= I_DATA; + -- + elsif (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then + if (cpu_addr(15) = '0') and (cpu_rd_l = '0') then + cpu_data_in <= rom_dout; + -- + elsif (cpu_addr(15 downto 14) = ram_addr) then + if (cpu_addr(13 downto 11) = "000") and (cpu_rd_l = '0') then + cpu_data_in <= ram_dout; + else + cpu_data_in <= x"FF"; + end if; + end if; + else + cpu_data_in <= x"FF"; + end if; + + end process; + + -- to audio + O_ADDR <= cpu_addr; + O_DATA <= cpu_data_out; + O_RD_L <= cpu_rd_l; + O_WR_L <= cpu_wr_l; + O_IOPC7 <= iopc7; + O_RESET_WD_L <= reset_wd_l; + +end RTL; diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/scramble_audio.vhd b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/scramble_audio.vhd new file mode 100644 index 00000000..274ba6ec --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/scramble_audio.vhd @@ -0,0 +1,788 @@ +-- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity scramble_audio is + port ( + -- + I_ADDR : in std_logic_vector(15 downto 0); + I_DATA : in std_logic_vector( 7 downto 0); + O_DATA : out std_logic_vector( 7 downto 0); + O_DATA_OE_L : out std_logic; + -- + I_RD_L : in std_logic; + I_WR_L : in std_logic; + I_IOPC7 : in std_logic; + -- + O_AUDIO : out std_logic_vector( 9 downto 0); + -- + I_1P_CTRL : in std_logic_vector( 6 downto 0); -- start, shoot1, shoot2, left,right,up,down + I_2P_CTRL : in std_logic_vector( 6 downto 0); -- start, shoot1, shoot2, left,right,up,down + I_SERVICE : in std_logic; + I_COIN1 : in std_logic; + I_COIN2 : in std_logic; + O_COIN_COUNTER : out std_logic; + -- + I_DIP : in std_logic_vector( 4 downto 0); + + -- + I_RESET_L : in std_logic; + ENA : in std_logic; -- 6 MHz + ENA_1_79 : in std_logic; -- 1.78975 MHz + CLK : in std_logic + ); +end; + +architecture RTL of scramble_audio is + + signal reset : std_logic; + signal cpu_ena : std_logic; + signal cpu_ena_gated : std_logic; + -- + signal cpu_m1_l : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_iorq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_wr_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_wait_l : std_logic; + signal cpu_int_l : std_logic; + signal cpu_nmi_l : std_logic; + signal cpu_busrq_l : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + -- + signal ram_cs : std_logic; + signal rom_oe : std_logic; + signal filter_load : std_logic; + signal filter_reg : std_logic_vector(11 downto 0); + -- + signal cpu_rom0_dout : std_logic_vectoR(7 downto 0); + signal cpu_rom1_dout : std_logic_vectoR(7 downto 0); + signal cpu_rom2_dout : std_logic_vectoR(7 downto 0); + signal rom_active : std_logic; + + signal rom_dout : std_logic_vector(7 downto 0); + signal ram_dout : std_logic_vector(7 downto 0); + -- + signal i8255_addr : std_logic_vector(1 downto 0); + signal i8255_1D_data : std_logic_vector(7 downto 0); + signal i8255_1D_data_oe_l : std_logic; + signal i8255_1D_cs_l : std_logic; + signal i8255_1D_pa_out : std_logic_vector(7 downto 0); + signal i8255_1D_pb_out : std_logic_vector(7 downto 0); + -- + signal i8255_1E_data : std_logic_vector(7 downto 0); + signal i8255_1E_data_oe_l : std_logic; + signal i8255_1E_cs_l : std_logic; + signal i8255_1E_pa : std_logic_vector(7 downto 0); + signal i8255_1E_pb : std_logic_vector(7 downto 0); + signal i8255_1E_pc : std_logic_vector(7 downto 0); + + -- security + signal net_1e10_i : std_logic; + signal net_1e12_i : std_logic; + signal xb : std_logic_vector(7 downto 0); + signal xbo : std_logic_vector(7 downto 0); + + signal audio_div_cnt : std_logic_vector( 8 downto 0) := (others => '0'); + signal ls90_op : std_logic_vector(3 downto 0); + signal ls90_clk : std_logic; + signal ls90_cnt : std_logic_vector( 3 downto 0) := (others => '0'); + -- ym2149 3C + signal ym2149_3C_dv : std_logic_vector(7 downto 0); + signal ym2149_3C_oe_l : std_logic; + signal ym2149_3C_bdir : std_logic; + signal ym2149_3C_bc2 : std_logic; + signal ym2149_3C_bc1 : std_logic; + signal ym2149_3C_audio : std_logic_vector(7 downto 0); + signal ym2149_3C_chan : std_logic_vector(1 downto 0); + signal ym2149_3C_chan_t1 : std_logic_vector(1 downto 0); + -- + -- ym2149 3D + signal ym2149_3D_dv : std_logic_vector(7 downto 0); + signal ym2149_3D_oe_l : std_logic; + signal ym2149_3D_bdir : std_logic; + signal ym2149_3D_bc2 : std_logic; + signal ym2149_3D_bc1 : std_logic; + signal ym2149_3D_audio : std_logic_vector(7 downto 0); + signal ym2149_3D_chan : std_logic_vector(1 downto 0); + signal ym2149_3D_chan_t1 : std_logic_vector(1 downto 0); + signal ym2149_3D_ioa_in : std_logic_vector(7 downto 0); + signal ym2149_3D_ioa_out : std_logic_vector(7 downto 0); + signal ym2149_3D_ioa_oe_l : std_logic; + signal ym2149_3D_iob_in : std_logic_vector(7 downto 0); + -- + signal ampm : std_logic; + signal sint : std_logic; + signal sint_t1 : std_logic; + -- + signal audio_3C_mix : std_logic_vector(9 downto 0); + signal audio_3C_final : std_logic_vector(9 downto 0); + signal audio_3D_mix : std_logic_vector(9 downto 0); + signal audio_3D_final : std_logic_vector(9 downto 0); + signal audio_final : std_logic_vector(10 downto 0); + + signal security_count : std_logic_vector(2 downto 0); + signal rd_l_t1 : std_logic; + -- filters + signal ym2149_3C_k : std_logic_vector(16 downto 0); + signal ym2149_3D_k : std_logic_vector(16 downto 0); + signal audio_in_m_out_3C : std_logic_vector(17 downto 0); + signal audio_in_m_out_3D : std_logic_vector(17 downto 0); + signal audio_mult_3C : std_logic_vector(35 downto 0); + signal audio_mult_3D : std_logic_vector(35 downto 0); + + signal rom0_cs, rom1_cs, rom2_cs : std_logic; + + + + type array_4of17 is array (3 downto 0) of std_logic_vector(16 downto 0); + constant K_Filter : array_4of17 := ('0' & x"00A3", + '0' & x"00C6", + '0' & x"039D", + '1' & x"0000" ); + + type filter_pipe is array (3 downto 0) of std_logic_vector(17 downto 0); + signal ym2149_3C_audio_pipe : filter_pipe; + signal ym2149_3D_audio_pipe : filter_pipe; + -- LP filter out = in.k + out_t1.(1-k) + -- + -- = (in-out_t1).k + out_t1 + -- + -- using + -- -(Ts.2.PI.Fc) + -- k = 1-e + -- + -- sampling freq = 1.79 MHz + -- + -- cut off freqs bit 0 1 + -- + --0.267uf ~ 713 Hz 1 1 0.00249996 x 00A3 + --0.220uf ~ 865 Hz 1 0 0.00303210 x 00C6 + --0.047uf ~ 4050 Hz 0 1 0.01411753 x 039D + -- 0 0 x10000 + +begin + -- Super Cobra + --0000-1fff ROM + --8000-83ff RAM + + cpu_ena <= '1'; -- run at audio clock speed + -- other cpu signals + cpu_busrq_l <= '1'; + cpu_nmi_l <= '1'; + cpu_wait_l <= '1'; + -- + cpu_ena_gated <= ENA_1_79 and cpu_ena; + u_cpu : entity work.T80sed + port map ( + RESET_n => I_RESET_L, + CLK_n => CLK, + CLKEN => cpu_ena_gated, + WAIT_n => cpu_wait_l, + INT_n => cpu_int_l, + NMI_n => cpu_nmi_l, + BUSRQ_n => cpu_busrq_l, + M1_n => cpu_m1_l, + MREQ_n => cpu_mreq_l, + IORQ_n => cpu_iorq_l, + RD_n => cpu_rd_l, + WR_n => cpu_wr_l, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out + ); + + p_cpu_int : process(CLK, I_RESET_L) + begin + if (I_RESET_L = '0') then + cpu_int_l <= '1'; + sint_t1 <= '0'; + elsif rising_edge(CLK) then + if (ENA_1_79 = '1') then + sint_t1 <= sint; + + if (cpu_m1_l = '0') and (cpu_iorq_l = '0') then + cpu_int_l <= '1'; + elsif (sint = '0') and (sint_t1 = '1') then + cpu_int_l <= '0'; + end if; + end if; + end if; + end process; + + p_mem_decode_comb : process(cpu_rfsh_l, cpu_wr_l, cpu_rd_l, cpu_mreq_l, cpu_addr) + variable decode : std_logic; + begin + decode := '0'; + if (cpu_rfsh_l = '1') and (cpu_mreq_l = '0') and (cpu_addr(15) = '1') then + decode := '1'; + end if; + filter_load <= decode and cpu_addr(12) and (not cpu_wr_l); + ram_cs <= decode and (not cpu_addr(12)); + rom_oe <= '0'; + if (cpu_addr(15) = '0') and (cpu_mreq_l = '0') and (cpu_rd_l = '0') then + rom_oe <= '1'; + end if; + end process; + + u_rom_5c : entity work.ROM_SND_0 + port map ( + CLK => CLK, + ADDR => cpu_addr(10 downto 0), + DATA => cpu_rom0_dout + ); + + u_rom_5d : entity work.ROM_SND_1 + port map ( + CLK => CLK, + ADDR => cpu_addr(10 downto 0), + DATA => cpu_rom1_dout + ); + + p_rom_mux : process(cpu_rom0_dout, cpu_rom1_dout, cpu_rom2_dout, cpu_addr, rom_oe) + variable rom_oe_decode : std_logic; + variable cpu_rom0_dout_s : std_logic_vector(7 downto 0); + begin +-- if not I_HWSEL_FROGGER then + cpu_rom0_dout_s := cpu_rom0_dout; + -- else -- swap bits 0 and 1 +-- cpu_rom0_dout_s := cpu_rom0_dout(7 downto 2) & cpu_rom0_dout(0) & cpu_rom0_dout(1); +-- end if; + + rom_dout <= (others => '0'); + rom_oe_decode := '0'; + case cpu_addr(13 downto 11) is + when "000" => rom_dout <= cpu_rom0_dout_s; rom_oe_decode := '1'; + when "001" => rom_dout <= cpu_rom1_dout; rom_oe_decode := '1'; + -- when "010" => rom_dout <= cpu_rom2_dout; rom_oe_decode := '1'; + when others => null; + end case; + + rom_active <= '0'; + if (rom_oe = '1') then + rom_active <= rom_oe_decode; + end if; + end process; + + + u_ram_6c_6d : work.dpram generic map (10,8) + port map + ( + addr_a_i => cpu_addr(9 downto 0), + data_a_i => cpu_data_out, + clk_b_i => clk, + addr_b_i => cpu_addr(9 downto 0), + data_b_o => ram_dout, + we_i => ram_cs and (not cpu_wr_l), + en_a_i => ENA_1_79, + clk_a_i => clk + ); + + p_cpu_data_mux : process(rom_dout, rom_active, ram_dout, ym2149_3C_oe_l, ym2149_3C_dv, ym2149_3D_oe_l, ym2149_3D_dv, ram_cs, cpu_wr_l) + begin + if (rom_active = '1') then + cpu_data_in <= rom_dout; + elsif (ram_cs = '1') and (cpu_wr_l = '1') then + cpu_data_in <= ram_dout; + elsif (ym2149_3C_oe_l = '0') then + cpu_data_in <= ym2149_3C_dv; + elsif (ym2149_3D_oe_l = '0') then + cpu_data_in <= ym2149_3D_dv; + else + cpu_data_in <= (others => '1'); -- float high + end if; + end process; + + p_filter_reg : process + begin + wait until rising_edge(CLK); + if (ENA_1_79 = '1') then + if (filter_load = '1') then + filter_reg <= cpu_addr(11 downto 0); + end if; + end if; + end process; + + p_8255_decode : process(I_RESET_L, I_ADDR) + begin + reset <= not I_RESET_L; + i8255_1D_cs_l <= '1'; + i8255_1E_cs_l <= '1'; + + -- the interface one + if (I_ADDR(13 downto 11) = "100") and (I_ADDR(15) = '1') then + i8255_1D_cs_l <= '0'; + end if; + + -- the button one + if (I_ADDR(13 downto 11) = "011") and (I_ADDR(15) = '1') then + i8255_1E_cs_l <= '0'; + end if; + i8255_addr <= I_ADDR(1 downto 0); + end process; + + p_ym_decode : process(cpu_rd_l, cpu_wr_l, cpu_iorq_l, cpu_addr) + variable rd_3c : std_logic; + variable wr_3c : std_logic; + variable ad_3c : std_logic; + -- + variable rd_3d : std_logic; + variable wr_3d : std_logic; + variable ad_3d : std_logic; + begin + + --bdir bc2 bc1 + -- 0 0 0 nop + -- 0 0 1 addr latch < WR_L AV4 / AV6 + -- 0 1 0 nop + -- 0 1 1 data read < RD_L AV5 / AV7 + + -- 1 0 0 addr latch + -- 1 0 1 nop + -- 1 1 0 data write < WR_L AV5 / AV7 + -- 1 1 1 addr latch + + + rd_3c := (not cpu_rd_l) and (not cpu_iorq_l) and cpu_addr(5); + wr_3c := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(5); + ad_3c := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(4); + + ym2149_3C_bdir <= wr_3c; + ym2149_3C_bc2 <= rd_3c or wr_3c; + ym2149_3C_bc1 <= rd_3c or ad_3c; + + + rd_3d := (not cpu_rd_l) and (not cpu_iorq_l) and cpu_addr(7); + wr_3d := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(7); + ad_3d := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(6); + + ym2149_3D_bdir <= wr_3d; + ym2149_3D_bc2 <= rd_3d or wr_3d; + ym2149_3D_bc1 <= rd_3d or ad_3d; + + end process; + + i8255_1E_pa(7) <= I_COIN2;--coin1 + i8255_1E_pa(6) <= I_COIN1;--coin2 + i8255_1E_pa(5) <= I_1P_CTRL(3); -- left1 + i8255_1E_pa(4) <= I_1P_CTRL(2); -- right1 + i8255_1E_pa(3) <= I_1P_CTRL(4); -- down1 + i8255_1E_pa(2) <= I_1P_CTRL(1); -- up1 + i8255_1E_pa(1) <= '1';--unused + i8255_1E_pa(0) <= I_SERVICE;--unused Test Retract + + i8255_1E_pb(7) <= '1';--unused + i8255_1E_pb(6) <= '1';--unused + i8255_1E_pb(5) <= I_2P_CTRL(3); -- left2 + i8255_1E_pb(4) <= I_2P_CTRL(2); -- right2 + i8255_1E_pb(3) <= I_2P_CTRL(0); -- down2 + i8255_1E_pb(2) <= I_2P_CTRL(1); -- up2 + i8255_1E_pb(1) <= I_DIP(0);--Table + i8255_1E_pb(0) <= I_DIP(1);--Rocket Number + + i8255_1E_pc(7) <= '1';--unused + i8255_1E_pc(6) <= I_2P_CTRL(6); -- 2 Start + i8255_1E_pc(5) <= '1';--unused + i8255_1E_pc(4) <= '1';--unused + i8255_1E_pc(3) <= I_DIP(4);--coining + i8255_1E_pc(2) <= I_DIP(3);--coining + i8255_1E_pc(1) <= I_DIP(2);--Free Play + i8255_1E_pc(0) <= I_1P_CTRL(6); -- start1 + + --O_COIN_COUNTER <= not I_IOPC7; -- open drain actually + + -- + -- PIA CHIPS + -- + u_i8255_1D : entity work.I82C55 -- bus interface + port map ( + I_ADDR => i8255_addr, + I_DATA => I_DATA, + O_DATA => i8255_1D_data, + O_DATA_OE_L => i8255_1D_data_oe_l, + + I_CS_L => i8255_1D_cs_l, + I_RD_L => I_RD_L, + I_WR_L => I_WR_L, + + I_PA => i8255_1D_pa_out, + O_PA => i8255_1D_pa_out, + O_PA_OE_L => open, + + I_PB => i8255_1D_pb_out, + O_PB => i8255_1D_pb_out, + O_PB_OE_L => open, + + I_PC => xbo, + O_PC => xb, + O_PC_OE_L => open, + + RESET => reset, + ENA => ENA, + CLK => CLK + ); + + u_i8255_1E : entity work.I82C55 -- push button + port map ( + I_ADDR => i8255_addr, + I_DATA => I_DATA, + O_DATA => i8255_1E_data, + O_DATA_OE_L => i8255_1E_data_oe_l, + + I_CS_L => i8255_1E_cs_l, + I_RD_L => I_RD_L, + I_WR_L => I_WR_L, + + I_PA => i8255_1E_pa, + O_PA => open, + O_PA_OE_L => open, + + I_PB => i8255_1E_pb, + O_PB => open, + O_PB_OE_L => open, + + I_PC => i8255_1E_pc, + O_PC => open, + O_PC_OE_L => open, + + RESET => reset, + ENA => ENA, + CLK => CLK + ); + + p_i8255_1d_bus_control : process(i8255_1D_pa_out, i8255_1D_pb_out, ym2149_3D_ioa_out, ym2149_3D_ioa_oe_l) + begin + if (ym2149_3D_ioa_oe_l = '0') then + ym2149_3D_ioa_in <= ym2149_3D_ioa_out; + else + ym2149_3D_ioa_in <= i8255_1D_pa_out; + end if; + + ampm <= i8255_1D_pb_out(4); -- amp mute + sint <= i8255_1D_pb_out(3); -- set int + end process; + + p_drive_cpubus : process(i8255_1D_data, i8255_1D_data_oe_l, i8255_1E_data, i8255_1E_data_oe_l) + begin + O_DATA_OE_L <= '1'; + O_DATA <= (others => '0'); + -- + if (i8255_1D_data_oe_l = '0') then + -- + O_DATA_OE_L <= '0'; + O_DATA <= i8255_1D_data; + elsif (i8255_1E_data_oe_l = '0') then + -- + O_DATA_OE_L <= '0'; + O_DATA <= i8255_1E_data; + end if; + end process; + -- + -- AUDIO CHIPS + -- + p_audio_clockgen : process + begin + wait until rising_edge(CLK); + if (ENA_1_79 = '1') then + audio_div_cnt <= audio_div_cnt - "1"; + ls90_clk <= not audio_div_cnt(8); + + if (audio_div_cnt(8 downto 0) = "000000000") then + if (ls90_cnt = x"9") then + ls90_cnt <= x"0"; + else + ls90_cnt <= ls90_cnt + "1"; + end if; + end if; + + ls90_op <= "0000"; + case ls90_cnt is --ls90 outputs DCBA + when x"0" => ls90_op <= "0000"; + when x"1" => ls90_op <= "0010"; + when x"2" => ls90_op <= "0100"; + when x"3" => ls90_op <= "0110"; + when x"4" => ls90_op <= "1000"; + when x"5" => ls90_op <= "0001"; + when x"6" => ls90_op <= "0011"; + when x"7" => ls90_op <= "0101"; + when x"8" => ls90_op <= "0111"; + when x"9" => ls90_op <= "1001"; + when others => ls90_op <= "0000"; + end case; + end if; + end process; + + p_ym2149_3d_iob_in : process(ls90_op, ls90_clk) + begin + ym2149_3D_iob_in <= ls90_op(0) & ls90_op(3) & ls90_op(2) & ls90_clk & "1110"; + end process; + + u_ym2149_3C : entity work.YM2149 + port map ( + -- data bus + I_DA => cpu_data_out, + O_DA => ym2149_3C_dv, + O_DA_OE_L => ym2149_3C_oe_l, + -- control + I_A9_L => '0', + I_A8 => '1', + I_BDIR => ym2149_3C_bdir, + I_BC2 => ym2149_3C_bc2, + I_BC1 => ym2149_3C_bc1, + I_SEL_L => '1', + + O_AUDIO => ym2149_3C_audio, + O_CHAN => ym2149_3C_chan, + -- port a + I_IOA => "11111111", + O_IOA => open, + O_IOA_OE_L => open, + -- port b + I_IOB => "11111111", + O_IOB => open, + O_IOB_OE_L => open, + + ENA => ENA_1_79, + RESET_L => I_RESET_L, + CLK => CLK + ); + + u_ym2149_3D : entity work.YM2149 + port map ( + -- data bus + I_DA => cpu_data_out, + O_DA => ym2149_3D_dv, + O_DA_OE_L => ym2149_3D_oe_l, + -- control + I_A9_L => '0', + I_A8 => '1', + I_BDIR => ym2149_3D_bdir, + I_BC2 => ym2149_3D_bc2, + I_BC1 => ym2149_3D_bc1, + I_SEL_L => '1', + + O_AUDIO => ym2149_3D_audio, + O_CHAN => ym2149_3D_chan, + -- port a + I_IOA => ym2149_3D_ioa_in, + O_IOA => ym2149_3D_ioa_out, + O_IOA_OE_L => ym2149_3D_ioa_oe_l, + -- port b + I_IOB => ym2149_3D_iob_in, + O_IOB => open, + O_IOB_OE_L => open, + + ENA => ENA_1_79, + RESET_L => I_RESET_L, + CLK => CLK + ); + + p_filter_coef : process + begin + wait until rising_edge(CLK); + if (ENA_1_79 = '1') then + case ym2149_3C_chan is -- -1 as reg here + when "00" => -- chan 3 + ym2149_3C_k <= (others => '0'); + when "11" => -- chan 2 + ym2149_3C_k <= K_FILTER(conv_integer(filter_reg(5 downto 4))); + when "10" => -- chan 1 + ym2149_3C_k <= K_FILTER(conv_integer(filter_reg(3 downto 2))); + when "01" => -- chan 0 + ym2149_3C_k <= K_FILTER(conv_integer(filter_reg(1 downto 0))); + when others => null; + end case; + + case ym2149_3D_chan is -- -1 as reg here + when "00" => -- chan 3 + ym2149_3D_k <= (others => '0'); + when "11" => -- chan 2 + ym2149_3D_k <= K_FILTER(conv_integer(filter_reg(11 downto 10))); + when "10" => -- chan 1 + ym2149_3D_k <= K_FILTER(conv_integer(filter_reg( 9 downto 8))); + when "01" => -- chan 0 + ym2149_3D_k <= K_FILTER(conv_integer(filter_reg( 7 downto 6))); + when others => null; + end case; + end if; + end process; + + + p_ym2149_audio_process : process(ym2149_3C_audio, ym2149_3C_audio_pipe, ym2149_3D_audio, ym2149_3D_audio_pipe) + begin + audio_in_m_out_3C <= (('0' & ym2149_3C_audio & "000000000"))- ym2149_3C_audio_pipe(3); -- signed + audio_in_m_out_3D <= (('0' & ym2149_3D_audio & "000000000"))- ym2149_3D_audio_pipe(3); -- signed + end process; + + mult_3C : work.MULT18X18 + port map + ( + P => audio_mult_3C,-- 35..0 -- audio 8bit on 32..25 33 sign bit, + A => audio_in_m_out_3C, --17..0 + B(17) => '0', + B(16 downto 0) => ym2149_3C_k + ); + + mult_3D : work.MULT18X18 + port map + ( + P => audio_mult_3D,-- 35..0 -- audio 8bit on 32..25 33 sign bit, + A => audio_in_m_out_3D, --17..0 + B(17) => '0', + B(16 downto 0) => ym2149_3D_k + ); + + p_ym2149_audio_pipe : process(I_RESET_L, CLK) + begin + if (I_RESET_L = '0') then + ym2149_3C_audio_pipe <= (others => (others => '0')); + ym2149_3D_audio_pipe <= (others => (others => '0')); + elsif rising_edge(CLK) then +-- audio_mult_3C <= audio_in_m_out_3C * ym2149_3C_k; +-- audio_mult_3D <= audio_in_m_out_3D * ym2149_3D_k; + if (ENA_1_79 = '1') then + -- we need some holding registers anyway, so lets just make it a shift and save a mux + ym2149_3C_audio_pipe(3 downto 1) <= ym2149_3C_audio_pipe(2 downto 0); + ym2149_3C_audio_pipe(0) <= audio_mult_3C(33 downto 16) + ym2149_3C_audio_pipe(3); -- bit 33 sign + + ym2149_3D_audio_pipe(3 downto 1) <= ym2149_3D_audio_pipe(2 downto 0); + ym2149_3D_audio_pipe(0) <= audio_mult_3D(33 downto 16) + ym2149_3D_audio_pipe(3); -- bit 33 sign + end if; + end if; + end process; + + p_ym2149_audio_mix : process + begin + wait until rising_edge(CLK); + if (ENA_1_79 = '1') then + ym2149_3C_chan_t1 <= ym2149_3C_chan; + ym2149_3D_chan_t1 <= ym2149_3D_chan; + + if (ym2149_3C_chan_t1 = "11") then + audio_3C_mix <= (others => '0'); + audio_3C_final <= audio_3C_mix; + else + audio_3C_mix <= audio_3C_mix + ("00" & ym2149_3C_audio_pipe(0)(16 downto 9)); + end if; + + if (ym2149_3D_chan_t1(1 downto 0) = "11") then + audio_3D_mix <= (others => '0'); + audio_3D_final <= audio_3D_mix; + else + audio_3D_mix <= audio_3D_mix + ("00" & ym2149_3D_audio_pipe(0)(16 downto 9)); + end if; + + audio_final <= ('0' & audio_3C_final) + ('0' & audio_3D_final); + end if; + end process; + + p_audio_out : process(CLK, I_RESET_L) + begin + if (I_RESET_L = '0') then + O_AUDIO <= (others => '0'); + elsif rising_edge(CLK) then + if (ENA_1_79 = '1') then + if (ampm = '1') then + O_AUDIO <= (others => '0'); + else + if (audio_final(10) = '1') then + O_AUDIO <= (others => '1'); + else + O_AUDIO <= audio_final(9 downto 0); + end if; + end if; + end if; + end if; + end process; + + p_security_6J : process(xb) + begin + -- chip K10A PAL16L8 + -- equations from Mark @ http://www.leopardcats.com/ + xbo(3 downto 0) <= xb(3 downto 0); + xbo(4) <= not(xb(0) or xb(1) or xb(2) or xb(3)); + xbo(5) <= not((not xb(2) and not xb(0)) or (not xb(2) and not xb(1)) or (not xb(3) and not xb(0)) or (not xb(3) and not xb(1))); + + xbo(6) <= not(not xb(0) and not xb(3)); + xbo(7) <= not((not xb(1)) or xb(2)); + end process; + + p_security_count : process(CLK, I_RESET_L) + begin + if (I_RESET_L = '0') then + security_count <= "000"; + elsif rising_edge(CLK) then + rd_l_t1 <= i_rd_l; + if (I_ADDR = x"8102") and (I_RD_L = '0') and (rd_l_t1 = '1') then + security_count <= security_count + "1"; + end if; + end if; + end process; + + p_security_2B : process(security_count) + begin + -- I am not sure what this chip does yet, but this gets us past the initial check for now. + case security_count is + when "000" => net_1e10_i <= '0'; net_1e12_i <= '1'; + when "001" => net_1e10_i <= '0'; net_1e12_i <= '1'; + when "010" => net_1e10_i <= '1'; net_1e12_i <= '0'; + when "011" => net_1e10_i <= '1'; net_1e12_i <= '1'; + when "100" => net_1e10_i <= '1'; net_1e12_i <= '1'; + when "101" => net_1e10_i <= '1'; net_1e12_i <= '1'; + when "110" => net_1e10_i <= '1'; net_1e12_i <= '1'; + when "111" => net_1e10_i <= '1'; net_1e12_i <= '1'; + when others => null; + end case; + end process; + +end RTL; diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/scramble_top.vhd b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/scramble_top.vhd new file mode 100644 index 00000000..201ac3e4 --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/scramble_top.vhd @@ -0,0 +1,154 @@ +-- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity scramble_top is +port ( + O_VIDEO_R : out std_logic_vector(3 downto 0); + O_VIDEO_G : out std_logic_vector(3 downto 0); + O_VIDEO_B : out std_logic_vector(3 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + + O_AUDIO : out std_logic_vector(9 downto 0); + + ip_dip_switch : in std_logic_vector(4 downto 0); + ip_1p : std_logic_vector(6 downto 0); + ip_2p : std_logic_vector(6 downto 0); + ip_service : std_logic; + ip_coin1 : std_logic; + ip_coin2 : std_logic; + + RESET : in std_logic; + clk : in std_logic; -- 25 + ena_12 : in std_logic; -- 6.25 x 2 + ena_6 : in std_logic; -- 6.25 (inverted) + ena_6b : in std_logic; -- 6.25 + ena_1_79 : in std_logic -- 1.786 +); +end; + +architecture RTL of scramble_top is + +-- ties to audio board +signal audio_addr : std_logic_vector(15 downto 0); +signal audio_data_out : std_logic_vector(7 downto 0); +signal audio_data_in : std_logic_vector(7 downto 0); +signal audio_data_oe_l : std_logic; +signal audio_rd_l : std_logic; +signal audio_wr_l : std_logic; +signal audio_iopc7 : std_logic; +signal audio_reset_l : std_logic; + +begin + +u_scobra : entity work.scramble +port map ( + -- + O_VIDEO_R => O_VIDEO_R, + O_VIDEO_G => O_VIDEO_G, + O_VIDEO_B => O_VIDEO_B, + O_HSYNC => O_HSYNC, + O_VSYNC => O_VSYNC, + O_HBLANK => O_HBLANK, + O_VBLANK => O_VBLANK, + -- + -- to audio board + -- + O_ADDR => audio_addr, + O_DATA => audio_data_out, + I_DATA => audio_data_in, + I_DATA_OE_L => audio_data_oe_l, + O_RD_L => audio_rd_l, + O_WR_L => audio_wr_l, + O_IOPC7 => audio_iopc7, + O_RESET_WD_L => audio_reset_l, + -- + ENA => ena_6, + ENAB => ena_6b, + ENA_12 => ena_12, + -- + RESET => reset, + CLK => clk +); + +-- +-- +-- audio subsystem +-- +u_audio : entity work.scramble_audio +port map ( + -- + I_ADDR => audio_addr, + I_DATA => audio_data_out, + O_DATA => audio_data_in, + O_DATA_OE_L => audio_data_oe_l, + -- + I_RD_L => audio_rd_l, + I_WR_L => audio_wr_l, + I_IOPC7 => audio_iopc7, + -- + O_AUDIO => O_AUDIO, + -- + I_1P_CTRL => ip_1p, + I_2P_CTRL => ip_2p, + I_SERVICE => ip_service, + I_COIN1 => ip_coin1, + I_COIN2 => ip_coin2, + O_COIN_COUNTER => open, + -- + I_DIP => ip_dip_switch, + -- + I_RESET_L => audio_reset_l, + ENA => ena_6, + ENA_1_79 => ena_1_79, + CLK => clk +); + +end RTL; diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/scramble_video.vhd b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/scramble_video.vhd new file mode 100644 index 00000000..df1147b8 --- /dev/null +++ b/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/scramble_video.vhd @@ -0,0 +1,727 @@ +-- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity scramble_video is + port ( + -- + I_HCNT : in std_logic_vector(8 downto 0); + I_VCNT : in std_logic_vector(8 downto 0); + I_VBLANK : in std_logic; + I_VSYNC : in std_logic; + + I_VCMA : in std_logic; + I_HCMA : in std_logic; + -- + I_CPU_ADDR : in std_logic_vector(15 downto 0); + I_CPU_DATA : in std_logic_vector(7 downto 0); + O_VRAM_DATA : out std_logic_vector(7 downto 0); + -- note, looks like the real hardware cannot read from object ram + -- + I_VRAMWR_L : in std_logic; + I_VRAMRD_L : in std_logic; + I_OBJRAMWR_L : in std_logic; + I_OBJRAMRD_L : in std_logic; + I_OBJEN_L : in std_logic; + -- + I_STARSON : in std_logic; + I_POUT1 : in std_logic; + -- + O_VIDEO_R : out std_logic_vector(3 downto 0); + O_VIDEO_G : out std_logic_vector(3 downto 0); + O_VIDEO_B : out std_logic_vector(3 downto 0); + -- + ENA : in std_logic; + ENAB : in std_logic; + ENA_12 : in std_logic; + CLK : in std_logic + ); +end; + +-- chars stars vidout? shell/missile +-- +-- 220R B 100 B 390R B 100R R +-- 470R B 150 B 100R G +-- 220R G 100 G blue ? +-- 470R G 150 G +-- 1K G 100 R +-- 220R R 150 R +-- 470R R +-- 1K R +architecture RTL of scramble_video is + + type array_3x5 is array (2 downto 0) of std_logic_vector(4 downto 0); + -- timing + signal ld : std_logic; + signal h256_l : std_logic; + signal h256 : std_logic; + signal cblank_s : std_logic; + signal hcmp1_s : std_logic; + signal hcmp2_s : std_logic; + signal hcmp1 : std_logic; + signal hcmp2 : std_logic; + signal cblank_l : std_logic; + signal h256_l_s : std_logic; + signal hcnt_f : std_logic_vector(7 downto 0); + signal vcnt_f : std_logic_vector(7 downto 0); + + -- load strobes + signal vpl_load : std_logic; + signal col_load : std_logic; + signal objdata_load : std_logic; + signal missile_load : std_logic; + signal missile_reg_l : std_logic; + + signal cntr_clr : std_logic; + signal cntr_load : std_logic; + signal sld_l : std_logic; + + -- video ram + signal vram_addr_sum : std_logic_vector(8 downto 0); -- extra bit for debug + signal msld_l : std_logic; + signal vram_addr_reg : std_logic_vector(7 downto 0); + signal vram_addr_xor : std_logic_vector(3 downto 0); + signal vram_addr : std_logic_vector(9 downto 0); + signal vram_dout : std_logic_vector(7 downto 0); + signal ldout : std_logic; + + -- object ram + signal obj_addr : std_logic_vector(7 downto 0); + signal hpla : std_logic_vector(7 downto 0); + signal objdata : std_logic_vector(7 downto 0); + + signal obj_rom_addr : std_logic_vector(12 downto 0); + signal obj_rom_0_dout : std_logic_vector(7 downto 0); + signal obj_rom_1_dout : std_logic_vector(7 downto 0); + -- + signal col_reg : std_logic_vector(2 downto 0); + signal cd : std_logic_vector(2 downto 0); + + signal shift_reg_1 : std_logic_vector(7 downto 0); + signal shift_reg_0 : std_logic_vector(7 downto 0); + signal shift_op : std_logic_vector(1 downto 0); + signal shift_sel : std_logic_vector(1 downto 0); + signal gr : std_logic_vector(1 downto 0); + signal gc : std_logic_vector(2 downto 0); + + signal vid : std_logic_vector(1 downto 0); + signal col : std_logic_vector(2 downto 0); + + signal obj_video_out_reg : std_logic_vector(4 downto 0); + signal vidout_l : std_logic; + signal obj_lut_out : std_logic_vector(7 downto 0); + + signal cntr_addr : std_logic_vector(7 downto 0); + signal cntr_addr_xor : std_logic_vector(10 downto 0); + signal sprite_sel : std_logic; + signal sprite_ram_ip : std_logic_vector(7 downto 0); + signal sprite_ram_waddr : std_logic_vector(10 downto 0); + signal sprite_ram_op : std_logic_vector(7 downto 0); + -- shell + signal shell_cnt : std_logic_vector(7 downto 0); + signal shell_ena : std_logic; + signal shell : std_logic; + signal shell_reg : std_logic; + -- stars + signal star_reg_1 : std_logic; + signal star_reg_2 : std_logic; + signal star_cnt_div : std_logic_vector(22 downto 0); + signal star_cnt : std_logic_vector(1 downto 0); + signal star_shift : std_logic_vector(16 downto 0); + signal star_shift_t1 : std_logic_vector(16 downto 0); + signal star_on : std_logic; + signal star_out_reg : std_logic; + -- Blue background + signal pout1_reg : std_logic; + + signal rom0_cs, rom1_cs : std_logic; + + +begin + p_hcnt_decode : process(I_HCNT) + begin + ld <= '0'; + if (I_HCNT(2 downto 0) = "111") then + ld <= '1'; + end if; + h256_l <= I_HCNT(8); + h256 <= not I_HCNT(8); + + end process; + + p_timing_decode : process(h256, h256_l, I_HCMA, I_VBLANK) + begin + cblank_s <= not (I_VBLANK or h256); -- active low + hcmp1_s <= h256_l and I_HCMA; + end process; + + p_reg : process + begin + wait until rising_edge(CLK); + + if (ENA = '1') then + if (ld = '1') then + hcmp1 <= hcmp1_s; + hcmp2 <= hcmp2_s; + cblank_l <= cblank_s; + h256_l_s <= h256_l; + cd <= col_reg; + end if; + end if; + end process; + + p_load_decode : process(ld, I_HCNT, h256) + variable obj_load : std_logic; + begin + vpl_load <= '0'; + obj_load := '0'; + col_load <= '0'; + + if (I_HCNT(2 downto 0) = "001") then vpl_load <= '1'; end if; -- 1 clock later + if (I_HCNT(2 downto 0) = "011") then obj_load := '1'; end if; -- 1 later + if (I_HCNT(2 downto 0) = "101") then col_load <= '1'; end if; -- 1 later + + objdata_load <= obj_load and h256 and (not I_HCNT(3)); + missile_load <= obj_load and h256 and ( I_HCNT(3)); + + cntr_clr <= ld and (not h256) and (not I_HCNT(3)); + cntr_load <= ld and ( h256) and (not I_HCNT(3)); + + end process; + + p_hv_flip : process(I_HCNT, I_VCNT, I_VCMA, hcmp1_s) + begin + for i in 0 to 7 loop + vcnt_f(i) <= I_VCNT(i) xor I_VCMA; + hcnt_f(i) <= I_HCNT(i) xor hcmp1_s; + end loop; + end process; + + p_video_addr_calc : process(vcnt_f, hpla) + begin + vram_addr_sum <= ('0' & vcnt_f(7 downto 0)) + ('0' & hpla(7 downto 0)); + end process; + + p_msld : process(vram_addr_sum) + begin + msld_l <= '1'; + if (vram_addr_sum(7 downto 0) = "11111111") then + msld_l <= '0'; + end if; + end process; + + p_video_addr_reg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + if (I_VBLANK = '1') then -- was async + vram_addr_reg <= x"00"; + elsif (vpl_load = '1') then -- vpl_l + vram_addr_reg <= vram_addr_sum(7 downto 0); + end if; + end if; + end process; + + p_vram_xor : process(vram_addr_reg, objdata, h256) + variable flip : std_logic; + begin + flip := objdata(7) and h256; + for i in 0 to 3 loop + vram_addr_xor(i) <= vram_addr_reg(i) xor flip; + end loop; + end process; + + p_vram_addr : process(vram_addr_reg, cblank_s, ld, I_CPU_ADDR, vram_addr_xor, hcnt_f) + variable match : std_logic; + begin + match := '0'; + if (vram_addr_reg(7 downto 4) = "1111") then + match := '1'; + end if; + + if (cblank_s = '0') then + ldout <= match and ld; -- blanking, sprites + else + ldout <= ld; + end if; + + if (cblank_s = '0') then -- blanking, sprites + --vram_cs <= (not I_VRAMWR_L) or (not I_VRAMRD_L); + vram_addr <= I_CPU_ADDR(9 downto 0); -- let the cpu in + else + --vram_cs <= '1'; + vram_addr <= vram_addr_reg(7 downto 4) & vram_addr_xor(3) & hcnt_f(7 downto 3); + end if; + end process; + + u_vram : work.dpram generic map (10,8) + port map + ( + clk_a_i => clk, + en_a_i => ena, + we_i => not I_VRAMWR_L, + + addr_a_i => vram_addr, + data_a_i => I_CPU_DATA, -- only cpu can write + + clk_b_i => clk, + addr_b_i => vram_addr, + data_b_o => vram_dout + ); + + O_VRAM_DATA <= vram_dout; + + p_object_ram_addr : process(h256, I_HCMA, objdata, I_HCNT, hcnt_f, I_CPU_ADDR, I_OBJEN_L) + begin + -- I believe the object ram can only be written during vblank + + if (h256 = '0') then + hcmp2_s <= I_HCMA; + else + hcmp2_s <= objdata(6); + end if; + + if (I_OBJEN_L = '0') then + obj_addr <= I_CPU_ADDR(7 downto 0); + else + obj_addr(7) <= '0'; + obj_addr(6) <= h256; + + -- A + if (h256 = '0') then -- normal + obj_addr(5) <= hcnt_f(7); --128h'; + else -- sprite + obj_addr(5) <= hcnt_f(3) and I_HCNT(1);-- 8h' and 2h; + end if; + + obj_addr(4 downto 2) <= hcnt_f(6 downto 4); + + if (h256 = '0') then -- normal + obj_addr(1) <= hcnt_f(3); --8h' + obj_addr(0) <= I_HCNT(2); --4h + else + obj_addr(1) <= I_HCNT(2); --4h + obj_addr(0) <= I_HCNT(1); --2h + end if; + + end if; + end process; + + u_object_ram : work.dpram generic map (8,8) + port map + ( + clk_a_i => clk, + en_a_i => ena, + we_i => not I_OBJRAMWR_L, + + addr_a_i => obj_addr, + data_a_i => I_CPU_DATA, -- only cpu can write + + clk_b_i => clk, + addr_b_i => obj_addr, + data_b_o => hpla + ); + + p_objdata_regs : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + if (col_load = '1') then -- colour load + col_reg <= hpla(2 downto 0); + end if; + + if (objdata_load = '1') then -- sprite load + objdata <= hpla; + end if; + + if (I_VBLANK = '1') then -- was async + missile_reg_l <= '1'; + elsif (missile_load = '1') then + missile_reg_l <= msld_l; + end if; + end if; + end process; + + p_obj_rom_addr : process(h256, vram_addr_xor, vram_dout, objdata, I_HCNT) + begin + obj_rom_addr( 2 downto 0) <= vram_addr_xor(2 downto 0); + if (h256 = '0') then + -- a + obj_rom_addr(10 downto 3) <= vram_dout; -- background objects + else + obj_rom_addr(10 downto 3) <= objdata(5 downto 0) & vram_addr_xor(3) & (objdata(6) xor I_HCNT(3)); -- sprites + end if; + obj_rom_addr(12 downto 11) <= objdata(7 downto 6); + end process; + + obj_rom0 : entity work.ROM_OBJ_0 + port map( + clk => CLK, + addr => obj_rom_addr, + data => obj_rom_0_dout + ); + + obj_rom1 : entity work.ROM_OBJ_1 + port map( + clk => CLK, + addr => obj_rom_addr, + data => obj_rom_1_dout + ); + + p_obj_rom_shift : process + variable obj_rom_0_dout_s : std_logic_vector(7 downto 0); + begin + wait until rising_edge (CLK); + obj_rom_0_dout_s := obj_rom_0_dout; + + if (ENA = '1') then + case shift_sel is + when "00" => null; -- do nothing + + when "01" => shift_reg_1 <= '0' & shift_reg_1(7 downto 1); -- right + shift_reg_0 <= '0' & shift_reg_0(7 downto 1); + + when "10" => shift_reg_1 <= shift_reg_1(6 downto 0) & '0'; -- left + shift_reg_0 <= shift_reg_0(6 downto 0) & '0'; + + when "11" => shift_reg_1 <= obj_rom_1_dout (7 downto 0); -- load + shift_reg_0 <= obj_rom_0_dout_s(7 downto 0); + when others => null; + end case; + end if; + end process; + + p_obj_rom_shift_sel : process(hcmp2, ldout, shift_reg_1, shift_reg_0) + begin + if (hcmp2 = '0') then + + shift_sel(1) <= '1'; + shift_sel(0) <= ldout; + shift_op(1) <= shift_reg_1(7); + shift_op(0) <= shift_reg_0(7); + else + + shift_sel(1) <= ldout; + shift_sel(0) <= '1'; + shift_op(1) <= shift_reg_1(0); + shift_op(0) <= shift_reg_0(0); + end if; + end process; + + p_video_out_logic : process(shift_op, cd, gr, gc) + variable vidon : std_logic; + begin + vidon := shift_op(0) or shift_op(1); + + if (gr(1 downto 0) = "00") then + vid(1 downto 0) <= shift_op(1 downto 0); + else + vid(1 downto 0) <= gr(1 downto 0); + end if; + + if (gc(2 downto 0) = "000") and (vidon = '1') then + col(2 downto 0) <= cd(2 downto 0); + else + col(2 downto 0) <= gc(2 downto 0); + end if; + end process; + + p_shell_ld : process(ld, h256, I_HCNT, missile_reg_l) + begin + sld_l <= '1'; + if (ld = '1') and (h256 = '1') and (I_HCNT(3) = '1') then + if (missile_reg_l = '0') and (I_HCNT(6 downto 4) /= "111") then + sld_l <= '0'; + end if; + end if; + + end process; + + p_shell_reg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + + if (sld_l = '0') then + shell_cnt <= hpla; + elsif (cblank_l = '1') then + shell_cnt <= shell_cnt + "1"; + else + shell_cnt <= shell_cnt; + end if; + + if (sld_l = '0') then + shell_ena <= '1'; + elsif (shell = '1') then + shell_ena <= '0'; + end if; + end if; + end process; + + p_shell_op : process(shell_cnt, shell_ena) + begin + -- note how T input is from QD on the bottom counter + -- we get a rc from xF8 to XFF + -- so the shell is set at count xFA (rc and bit 1) + shell <= '0'; + if (shell_cnt = x"F8") then -- minus 2 as delay wrong + shell <= shell_ena; + end if; + end process; + + p_cntr_cnt : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + if (cntr_clr = '1') and (h256_l_s = '0') then -- async + cntr_addr <= (others => '0'); + elsif (cntr_load = '1') then + cntr_addr <= hpla(7 downto 0); + else + cntr_addr <= cntr_addr + "1"; + end if; + end if; + end process; + + p_cntr_addr : process(cntr_addr, hcmp1) + begin + cntr_addr_xor(10 downto 8) <= (others => '0'); + for i in 0 to 7 loop + cntr_addr_xor(i) <= cntr_addr(i) xor hcmp1; + end loop; + end process; + + p_sprite_sel : process(h256_l_s, cntr_addr_xor) + begin + sprite_sel <= '0'; + if (h256_l_s = '0') and (cntr_addr_xor(7 downto 4) /= "0000") then + sprite_sel <= '1'; + end if; + end process; + + p_sprite_write : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + -- delay 1 clock + sprite_ram_ip <= (others => '0'); + if (sprite_sel = '1') then + sprite_ram_ip(4 downto 2) <= col(2 downto 0); + sprite_ram_ip(1 downto 0) <= vid(1 downto 0); + end if; + + sprite_ram_waddr <= cntr_addr_xor; + end if; + end process; + + u_sprite_ram : work.dpram generic map (11,8) + port map + ( + clk_a_i => clk, + en_a_i => ena, + we_i => '1', + + addr_a_i => sprite_ram_waddr, + data_a_i => sprite_ram_ip, + + clk_b_i => clk, + addr_b_i => cntr_addr_xor, + data_b_o => sprite_ram_op + ); + + gc(2 downto 0) <= sprite_ram_op(4 downto 2); + gr(1 downto 0) <= sprite_ram_op(1 downto 0); + + p_video_out_reg : process + variable vidout_l_int : std_logic; + begin + wait until rising_edge(CLK); + -- register all objects to match increased video delay + if (ENA = '1') then + star_shift_t1 <= star_shift; + + if (cblank_l = '0') then + -- logic around the clr workes out as a sync reset + obj_video_out_reg <= (others => '0'); + shell_reg <= '0'; + star_out_reg <= '0'; + pout1_reg <= '0'; + else + + obj_video_out_reg(4 downto 2) <= col(2 downto 0); + obj_video_out_reg(1 downto 0) <= vid(1 downto 0); + vidout_l <= not(vid(1) or vid(0)); + -- probably wider than the original, we must be a whole 6MHz clock here or the scan-doubler will loose it. + shell_reg <= shell; + + star_out_reg <= '0'; + if (star_shift(7 downto 0) = x"FF") and (star_on = '1') then + star_out_reg <= (vcnt_f(0) xor hcnt_f(3)) and (not star_shift(16)); + end if; + + pout1_reg <= I_POUT1; + + end if; + end if; + end process; + + col_rom : entity work.ROM_LUT + port map( + clk => CLK, + addr => obj_video_out_reg(4 downto 0), + data => obj_lut_out + ); + + p_col_rom_ce : process + variable video : array_3x5; + begin + wait until rising_edge(CLK); + if (ENA = '1') then + video(0)(4) := '0'; + video(1)(4) := '0'; + video(2)(4) := '0'; + video(0)(3) := '0'; -- b + video(1)(3) := '0'; -- g + video(2)(3) := '0'; -- r + + if (vidout_l = '0') then -- cs_l on col rom + + video(0)(2 downto 0) := obj_lut_out(7 downto 6) & '0'; + video(1)(2 downto 0) := obj_lut_out(5 downto 3); + video(2)(2 downto 0) := obj_lut_out(2 downto 0); + else + video(0)(2 downto 0) := "000"; + video(1)(2 downto 0) := "000"; + video(2)(2 downto 0) := "000"; + end if; + -- + -- end of direct assigns + -- + + video(1) := video(1) + ("00" & shell_reg & "00"); + video(2) := video(2) + ("00" & shell_reg & "00"); + + -- add stars, background and video + if (star_out_reg = '1') and (vidout_l = '1') then + video(0) := video(0) + ( '0' & star_shift_t1(13 downto 12) & "00"); + video(1) := video(1) + ( '0' & star_shift_t1(11 downto 10) & "00"); + video(2) := video(2) + ( '0' & star_shift_t1( 9 downto 8) & "00"); + end if; + + if (pout1_reg = '1') and (vidout_l = '1') then + video(0) := video(0) + ("00011"); + end if; + -- check for clip + for i in 0 to 2 loop + if video(i)(4) = '1' or video(i)(3) = '1' then + video(i)(2 downto 0) := (others => '1'); + end if; + end loop; + + O_VIDEO_B <= video(0)(2 downto 0) & video(0)(2); + O_VIDEO_G <= video(1)(2 downto 0) & video(1)(2); + O_VIDEO_R <= video(2)(2 downto 0) & video(2)(2); + end if; + end process; + + p_stars_timer : process + begin + wait until rising_edge(CLK); + -- 555 period 0.8316 seconds + -- ~ 4DF 666 + if (ENA = '1') then + if (star_cnt_div(22 downto 17) = "100111") then + star_cnt_div <= (others => '0'); + star_cnt <= star_cnt + "1"; + else + star_cnt_div <= star_cnt_div + "1"; + end if; + end if; + end process; + + p_stars_demux : process(star_cnt, I_VCNT, star_shift) + begin + case star_cnt is + when "00" => star_on <= star_shift(8); + when "01" => star_on <= star_shift(10); + when "10" => star_on <= I_VCNT(1); + when "11" => star_on <= '1'; + when others => null; + end case; + end process; + + p_stars : process + variable star_ena : std_logic; + variable star_shift_ena : std_logic; + variable fb : std_logic; + variable star_clear : std_logic; + begin + wait until rising_edge(CLK); + -- stars clocked off 12 MHz clock + star_ena := ENA_12 and (not I_VSYNC) and h256_l_s; + + if (ENA = '1') and (I_VSYNC = '1') then + star_reg_1 <= '0'; + star_reg_2 <= '0'; + elsif (star_ena = '1') then + star_reg_1 <= '1'; + star_reg_2 <= star_reg_1; + end if; + + star_shift_ena := (star_reg_2 or I_HCMA) and star_ena; + + star_clear := I_STARSON and (not I_VBLANK); + + fb := (not star_shift(16)) xor star_shift(4); + if (star_clear = '0') then + star_shift <= (others => '0'); + elsif (star_shift_ena = '1') then + star_shift(16 downto 0) <= star_shift(15 downto 0) & fb; + end if; + end process; + +end RTL; diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/README.txt b/Arcade_MiST/Scramble Hardware/MoonWar_MiST/README.txt index a401d408..70efb2f3 100644 --- a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/README.txt +++ b/Arcade_MiST/Scramble Hardware/MoonWar_MiST/README.txt @@ -19,7 +19,10 @@ ToDo: Controls(Spinner) -- ESC : Coin -- F2 : Start 2 players -- F1 : Start 1 player --- SPACE : Fire+Bomb +-- SPACE : Fire +-- ALT L : Thrust +-- CTRL L : Shield +-- SHIFT L : Hyperflip -- UP,DOWN,LEFT,RIGHT arrows : Movements -- diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/scramble_audio.vhd b/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/scramble_audio.vhd index a70613fa..70172211 100644 --- a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/scramble_audio.vhd +++ b/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/scramble_audio.vhd @@ -179,8 +179,8 @@ architecture RTL of scramble_audio is signal audio_mult_3D : std_logic_vector(35 downto 0); signal rom0_cs, rom1_cs, rom2_cs : std_logic; - signal I_1P_DAIL : std_logic_vector(4 downto 0) := (others => '1'); - signal I_2P_DAIL : std_logic_vector(4 downto 0) := (others => '1'); + signal I_1P_DAIL : std_logic_vector(4 downto 0) := (others => '0'); + signal I_2P_DAIL : std_logic_vector(4 downto 0) := (others => '0'); type array_4of17 is array (3 downto 0) of std_logic_vector(16 downto 0); @@ -432,7 +432,7 @@ port map( i8255_1E_pa(7) <= I_COIN1;--coin1 i8255_1E_pa(6) <= I_COIN2;--coin2 i8255_1E_pa(5) <= I_2P_CTRL(4); -- button 3 shield - i8255_1E_pa(4 downto 0) <= I_1P_DAIL(4 downto 0);-- or I_2P_DAIL; -- controls + i8255_1E_pa(4 downto 0) <= not I_1P_DAIL(4 downto 0);-- or I_2P_DAIL; -- controls i8255_1E_pb(7) <= I_1P_CTRL(2); -- button 1 fire i8255_1E_pb(6) <= I_1P_CTRL(3); -- button 2 thrust diff --git a/Arcade_MiST/Scramble Hardware/Moonwar.jpg b/Arcade_MiST/Scramble Hardware/Moonwar.jpg new file mode 100644 index 00000000..583d361d Binary files /dev/null and b/Arcade_MiST/Scramble Hardware/Moonwar.jpg differ diff --git a/Arcade_MiST/Scramble Hardware/Super Cobra.jpg b/Arcade_MiST/Scramble Hardware/Super Cobra.jpg new file mode 100644 index 00000000..9ef873c9 Binary files /dev/null and b/Arcade_MiST/Scramble Hardware/Super Cobra.jpg differ diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/Release/SCobra.rbf b/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/Release/SCobra.rbf index 0fdeee7f..c84956b5 100644 Binary files a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/Release/SCobra.rbf and b/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/Release/SCobra.rbf differ diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/SCobra.qsf b/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/SCobra.qsf index a63ed4fb..9a9a0c61 100644 --- a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/SCobra.qsf +++ b/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/SCobra.qsf @@ -45,30 +45,6 @@ set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/SCobra_Mist.sv -set_global_assignment -name VHDL_FILE rtl/scramble_top.vhd -set_global_assignment -name VHDL_FILE rtl/scramble.vhd -set_global_assignment -name VHDL_FILE rtl/scramble_audio.vhd -set_global_assignment -name VHDL_FILE rtl/scramble_video.vhd -set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd -set_global_assignment -name VHDL_FILE rtl/rom/ROM_SND_2.vhd -set_global_assignment -name VHDL_FILE rtl/rom/ROM_SND_1.vhd -set_global_assignment -name VHDL_FILE rtl/rom/ROM_SND_0.vhd -set_global_assignment -name VHDL_FILE rtl/rom/ROM_PGM.vhd -set_global_assignment -name VHDL_FILE rtl/rom/ROM_OBJ_1.vhd -set_global_assignment -name VHDL_FILE rtl/rom/ROM_OBJ_0.vhd -set_global_assignment -name VHDL_FILE rtl/rom/ROM_LUT.vhd -set_global_assignment -name VERILOG_FILE rtl/pll.v -set_global_assignment -name VHDL_FILE rtl/MULT18X18.vhd -set_global_assignment -name VHDL_FILE rtl/i82c55.vhd -set_global_assignment -name VHDL_FILE rtl/dpram.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80sed.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd -set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip # Pin & Location Assignments # ========================== @@ -167,4 +143,28 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - # end ENTITY(SCobra_Mist) # ----------------------- +set_global_assignment -name SYSTEMVERILOG_FILE rtl/SCobra_Mist.sv +set_global_assignment -name VHDL_FILE rtl/scramble_top.vhd +set_global_assignment -name VHDL_FILE rtl/scramble.vhd +set_global_assignment -name VHDL_FILE rtl/scramble_audio.vhd +set_global_assignment -name VHDL_FILE rtl/scramble_video.vhd +set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd +set_global_assignment -name VHDL_FILE rtl/rom/ROM_PGM.vhd +set_global_assignment -name VHDL_FILE rtl/rom/ROM_OBJ_1.vhd +set_global_assignment -name VHDL_FILE rtl/rom/ROM_OBJ_0.vhd +set_global_assignment -name VHDL_FILE rtl/rom/ROM_SND_2.vhd +set_global_assignment -name VHDL_FILE rtl/rom/ROM_SND_1.vhd +set_global_assignment -name VHDL_FILE rtl/rom/ROM_SND_0.vhd +set_global_assignment -name VHDL_FILE rtl/rom/ROM_LUT.vhd +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name VHDL_FILE rtl/MULT18X18.vhd +set_global_assignment -name VHDL_FILE rtl/i82c55.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd +set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/SCobra_Mist.sv b/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/SCobra_Mist.sv index e25557df..fdd4547e 100644 --- a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/SCobra_Mist.sv +++ b/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/SCobra_Mist.sv @@ -155,10 +155,10 @@ user_io( .status (status ) ); -dac #(10)dac( +dac #(16)dac( .clk_i(clk_sys), .res_n_i(1), - .dac_i(audio), + .dac_i({audio, audio[9:5]}), .dac_o(AUDIO_L) ); // Rotated Normal diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/scramble_audio.vhd b/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/scramble_audio.vhd index df84fa5f..eb1d25d1 100644 --- a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/scramble_audio.vhd +++ b/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/scramble_audio.vhd @@ -263,46 +263,55 @@ begin p_mem_decode_comb : process(cpu_rfsh_l, cpu_wr_l, cpu_rd_l, cpu_mreq_l, cpu_addr) variable decode : std_logic; begin - decode := '0'; - if (cpu_rfsh_l = '1') and (cpu_mreq_l = '0') and (cpu_addr(15) = '1') then - decode := '1'; - end if; - - filter_load <= decode and cpu_addr(12) and (not cpu_wr_l); - ram_cs <= decode and (not cpu_addr(12)); - + decode := '0'; + if (cpu_rfsh_l = '1') and (cpu_mreq_l = '0') and (cpu_addr(15) = '1') then + decode := '1'; + end if; + filter_load <= decode and cpu_addr(12) and (not cpu_wr_l); + ram_cs <= decode and (not cpu_addr(12)); rom_oe <= '0'; - if (cpu_addr(15) = '0') and (cpu_mreq_l = '0') and (cpu_rd_l = '0') then - rom_oe <= '1'; - end if; - + if (cpu_addr(15) = '0') and (cpu_mreq_l = '0') and (cpu_rd_l = '0') then + rom_oe <= '1'; + end if; end process; - - u_rom_5c : entity work.ROM_SND_0 - port map( - clk => CLK, - addr => cpu_addr(10 downto 0), - data => cpu_rom0_dout - ); - - u_rom_5d : entity work.ROM_SND_1 - port map( - clk => CLK, - addr => cpu_addr(10 downto 0), - data => cpu_rom1_dout - ); + + u_rom_5c : entity work.ROM_SND_0 + port map ( + CLK => CLK, + ADDR => cpu_addr(10 downto 0), + DATA => cpu_rom0_dout + ); + + u_rom_5d : entity work.ROM_SND_1 + port map ( + CLK => CLK, + ADDR => cpu_addr(10 downto 0), + DATA => cpu_rom1_dout + ); + + u_rom_5e : entity work.ROM_SND_2 + port map ( + CLK => CLK, + ADDR => cpu_addr(10 downto 0), + DATA => cpu_rom2_dout + ); p_rom_mux : process(cpu_rom0_dout, cpu_rom1_dout, cpu_rom2_dout, cpu_addr, rom_oe) variable rom_oe_decode : std_logic; variable cpu_rom0_dout_s : std_logic_vector(7 downto 0); begin - cpu_rom0_dout_s := cpu_rom0_dout; +-- if not I_HWSEL_FROGGER then + cpu_rom0_dout_s := cpu_rom0_dout; + -- else -- swap bits 0 and 1 +-- cpu_rom0_dout_s := cpu_rom0_dout(7 downto 2) & cpu_rom0_dout(0) & cpu_rom0_dout(1); +-- end if; rom_dout <= (others => '0'); rom_oe_decode := '0'; case cpu_addr(13 downto 11) is when "000" => rom_dout <= cpu_rom0_dout_s; rom_oe_decode := '1'; when "001" => rom_dout <= cpu_rom1_dout; rom_oe_decode := '1'; + when "010" => rom_dout <= cpu_rom2_dout; rom_oe_decode := '1'; when others => null; end case; diff --git a/Arcade_MiST/Scramble Hardware/Tazz Mania.jpeg b/Arcade_MiST/Scramble Hardware/Tazz Mania.jpeg new file mode 100644 index 00000000..60fdc217 Binary files /dev/null and b/Arcade_MiST/Scramble Hardware/Tazz Mania.jpeg differ