diff --git a/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/PKWARS_MiST.qpf b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/PKWARS_MiST.qpf
new file mode 100644
index 00000000..1061b579
--- /dev/null
+++ b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/PKWARS_MiST.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
+# Date created = 21:10:59 May 30, 2020
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "21:10:59 May 30, 2020"
+
+# Revisions
+
+PROJECT_REVISION = "PKWARS_MiST"
diff --git a/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/PKWARS_MiST.qsf b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/PKWARS_MiST.qsf
new file mode 100644
index 00000000..7f99554f
--- /dev/null
+++ b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/PKWARS_MiST.qsf
@@ -0,0 +1,245 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
+# Date created = 01:56:03 May 31, 2020
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# PKWARS_MiST_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.2
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:48:06 MAY 24,2017"
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/PKWARS_MiST.sv
+set_global_assignment -name VERILOG_FILE rtl/FPGA_PKWARS.v
+set_global_assignment -name VERILOG_FILE rtl/PKWARS_VIDEO.v
+set_global_assignment -name VERILOG_FILE rtl/PKWARS_SPRITE.v
+set_global_assignment -name VERILOG_FILE rtl/PKWARS_SND.v
+set_global_assignment -name VERILOG_FILE rtl/PKWARS_ROMARB.v
+set_global_assignment -name VERILOG_FILE rtl/PKWARS_CLKGEN.v
+set_global_assignment -name VERILOG_FILE rtl/PKWARS_HVGEN.v
+set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep_mod.vhd
+set_global_assignment -name VHDL_FILE rtl/col.vhd
+set_global_assignment -name VERILOG_FILE rtl/mems.v
+set_global_assignment -name VERILOG_FILE rtl/z80ip.v
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
+set_global_assignment -name VERILOG_FILE rtl/pll.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
+set_global_assignment -name VERILOG_FILE rtl/DPRAM1024.v
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_90 -to SPI_SS4
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PIN_49 -to SDRAM_A[0]
+set_location_assignment PIN_44 -to SDRAM_A[1]
+set_location_assignment PIN_42 -to SDRAM_A[2]
+set_location_assignment PIN_39 -to SDRAM_A[3]
+set_location_assignment PIN_4 -to SDRAM_A[4]
+set_location_assignment PIN_6 -to SDRAM_A[5]
+set_location_assignment PIN_8 -to SDRAM_A[6]
+set_location_assignment PIN_10 -to SDRAM_A[7]
+set_location_assignment PIN_11 -to SDRAM_A[8]
+set_location_assignment PIN_28 -to SDRAM_A[9]
+set_location_assignment PIN_50 -to SDRAM_A[10]
+set_location_assignment PIN_30 -to SDRAM_A[11]
+set_location_assignment PIN_32 -to SDRAM_A[12]
+set_location_assignment PIN_83 -to SDRAM_DQ[0]
+set_location_assignment PIN_79 -to SDRAM_DQ[1]
+set_location_assignment PIN_77 -to SDRAM_DQ[2]
+set_location_assignment PIN_76 -to SDRAM_DQ[3]
+set_location_assignment PIN_72 -to SDRAM_DQ[4]
+set_location_assignment PIN_71 -to SDRAM_DQ[5]
+set_location_assignment PIN_69 -to SDRAM_DQ[6]
+set_location_assignment PIN_68 -to SDRAM_DQ[7]
+set_location_assignment PIN_86 -to SDRAM_DQ[8]
+set_location_assignment PIN_87 -to SDRAM_DQ[9]
+set_location_assignment PIN_98 -to SDRAM_DQ[10]
+set_location_assignment PIN_99 -to SDRAM_DQ[11]
+set_location_assignment PIN_100 -to SDRAM_DQ[12]
+set_location_assignment PIN_101 -to SDRAM_DQ[13]
+set_location_assignment PIN_103 -to SDRAM_DQ[14]
+set_location_assignment PIN_104 -to SDRAM_DQ[15]
+set_location_assignment PIN_58 -to SDRAM_BA[0]
+set_location_assignment PIN_51 -to SDRAM_BA[1]
+set_location_assignment PIN_85 -to SDRAM_DQMH
+set_location_assignment PIN_67 -to SDRAM_DQML
+set_location_assignment PIN_60 -to SDRAM_nRAS
+set_location_assignment PIN_64 -to SDRAM_nCAS
+set_location_assignment PIN_66 -to SDRAM_nWE
+set_location_assignment PIN_59 -to SDRAM_nCS
+set_location_assignment PIN_33 -to SDRAM_CKE
+set_location_assignment PIN_43 -to SDRAM_CLK
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name TOP_LEVEL_ENTITY PKWARS_MiST
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# SignalTap II Assignments
+# ========================
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/nk.stp
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# -------------------------
+# start ENTITY(PKWARS_MiST)
+
+ # Pin & Location Assignments
+ # ==========================
+ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
+ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
+ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
+ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
+ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
+ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
+ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
+ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
+ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
+ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
+ set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
+ set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
+
+ # Fitter Assignments
+ # ==================
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
+ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
+ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
+ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
+ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
+
+ # start DESIGN_PARTITION(Top)
+ # ---------------------------
+
+ # Incremental Compilation Assignments
+ # ===================================
+ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+ # end DESIGN_PARTITION(Top)
+ # -------------------------
+
+# end ENTITY(PKWARS_MiST)
+# -----------------------
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/clean.bat b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/clean.bat
new file mode 100644
index 00000000..b4ae3f11
--- /dev/null
+++ b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/clean.bat
@@ -0,0 +1,41 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+del /s *~
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+rmdir /s /q hc_output
+rmdir /s /q .qsys_edit
+rmdir /s /q hps_isw_handoff
+rmdir /s /q sys\.qsys_edit
+rmdir /s /q sys\vip
+cd sys
+for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
+cd ..
+for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
+del build_id.v
+del c5_pin_model_dump.txt
+del PLLJ_PLLSPE_INFO.txt
+del /s *.qws
+del /s *.ppf
+del /s *.ddb
+del /s *.csv
+del /s *.cmp
+del /s *.sip
+del /s *.spd
+del /s *.bsf
+del /s *.f
+del /s *.sopcinfo
+del /s *.xml
+del *.cdf
+del /s new_rtl_netlist
+del /s old_rtl_netlist
+del sys\vip.qip
+del sys\sysmem.qip
+del sys\sdram.sv
+del sys\ddram.sv
+pause
diff --git a/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/meta/PKWARS.mra b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/meta/PKWARS.mra
new file mode 100644
index 00000000..8b8ccad3
--- /dev/null
+++ b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/meta/PKWARS.mra
@@ -0,0 +1,24 @@
+
+ PKWARS
+ 0216
+ 202001010000
+ 1985
+ Sega
+ยด PKWARS
+ Action
+ pkunwar
+
+
+
+ FF
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/DPRAM1024.v b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/DPRAM1024.v
new file mode 100644
index 00000000..bcb52785
--- /dev/null
+++ b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/DPRAM1024.v
@@ -0,0 +1,244 @@
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram
+
+// ============================================================
+// File Name: DPRAM1024.v
+// Megafunction Name(s):
+// altsyncram
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.4 Build 182 03/12/2014 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2014 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module DPRAM1024 (
+ address_a,
+ address_b,
+ clock_a,
+ clock_b,
+ data_a,
+ data_b,
+ wren_a,
+ wren_b,
+ q_a,
+ q_b);
+
+ input [9:0] address_a;
+ input [9:0] address_b;
+ input clock_a;
+ input clock_b;
+ input [7:0] data_a;
+ input [7:0] data_b;
+ input wren_a;
+ input wren_b;
+ output [7:0] q_a;
+ output [7:0] q_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri1 clock_a;
+ tri0 wren_a;
+ tri0 wren_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire [7:0] sub_wire0;
+ wire [7:0] sub_wire1;
+ wire [7:0] q_a = sub_wire0[7:0];
+ wire [7:0] q_b = sub_wire1[7:0];
+
+ altsyncram altsyncram_component (
+ .clock0 (clock_a),
+ .wren_a (wren_a),
+ .address_b (address_b),
+ .clock1 (clock_b),
+ .data_b (data_b),
+ .wren_b (wren_b),
+ .address_a (address_a),
+ .data_a (data_a),
+ .q_a (sub_wire0),
+ .q_b (sub_wire1),
+ .aclr0 (1'b0),
+ .aclr1 (1'b0),
+ .addressstall_a (1'b0),
+ .addressstall_b (1'b0),
+ .byteena_a (1'b1),
+ .byteena_b (1'b1),
+ .clocken0 (1'b1),
+ .clocken1 (1'b1),
+ .clocken2 (1'b1),
+ .clocken3 (1'b1),
+ .eccstatus (),
+ .rden_a (1'b1),
+ .rden_b (1'b1));
+ defparam
+ altsyncram_component.address_reg_b = "CLOCK1",
+ altsyncram_component.clock_enable_input_a = "BYPASS",
+ altsyncram_component.clock_enable_input_b = "BYPASS",
+ altsyncram_component.clock_enable_output_a = "BYPASS",
+ altsyncram_component.clock_enable_output_b = "BYPASS",
+ altsyncram_component.indata_reg_b = "CLOCK1",
+ altsyncram_component.intended_device_family = "Cyclone V",
+ altsyncram_component.lpm_type = "altsyncram",
+ altsyncram_component.numwords_a = 1024,
+ altsyncram_component.numwords_b = 1024,
+ altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
+ altsyncram_component.outdata_aclr_a = "NONE",
+ altsyncram_component.outdata_aclr_b = "NONE",
+ altsyncram_component.outdata_reg_a = "CLOCK0",
+ altsyncram_component.outdata_reg_b = "CLOCK1",
+ altsyncram_component.power_up_uninitialized = "FALSE",
+ altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
+ altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
+ altsyncram_component.widthad_a = 10,
+ altsyncram_component.widthad_b = 10,
+ altsyncram_component.width_a = 8,
+ altsyncram_component.width_b = 8,
+ altsyncram_component.width_byteena_a = 1,
+ altsyncram_component.width_byteena_b = 1,
+ altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "5"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: REGrren NUMERIC "0"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
+// Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
+// Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
+// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
+// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
+// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
+// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]"
+// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
+// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]"
+// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
+// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
+// Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
+// Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
+// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
+// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
+// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/FPGA_PKWARS.v b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/FPGA_PKWARS.v
new file mode 100644
index 00000000..b866d1f2
--- /dev/null
+++ b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/FPGA_PKWARS.v
@@ -0,0 +1,233 @@
+/************************************************************************
+ "FPGA Penguin-Kun Wars" - Penguin-Kun Wars board compatible circuit
+
+ Copyright (c) 2012,20 MiSTer-X
+*************************************************************************/
+module FPGA_PKWARS
+(
+ input clk48M,
+ input RESET,
+
+ input EXCITE, // Excite Mode (Double the CPU clock)
+
+ input [7:0] CTR1,
+ input [7:0] CTR2,
+ input [7:0] DSW,
+
+ input [8:0] PH,
+ input [8:0] PV,
+
+ output PCLK,
+ output [11:0] POUT,
+
+ output [15:0] SND,
+
+ output [15:0] cpu_rom_addr,
+ input [7:0] cpu_rom_do,
+ output [13:0] gfx_rom_addr,
+ input [31:0] gfx_rom_do
+);
+
+wire VBLK = (PV == 9'd194);
+
+wire VCLKx4, VCLK;
+wire VRAMCL, CLK24M, CLK12M, CLK6M, CLK3M;
+PKWARS_CLKGEN clkgen
+(
+ clk48M,
+ VCLKx4, VCLK,
+ VRAMCL, PCLK,
+ CLK24M, CLK12M, CLK6M, CLK3M
+);
+
+
+wire [13:0] BGCAD, SPCAD;
+wire [31:0] BGCDT, SPCDT;
+//wire [4:0] PALAD;
+//ire [7:0] PALDT;
+wire [15:0] CPUAD;
+
+wire [1:0] PHASE;
+
+PKWARS_ROMS roms
+(
+ clk48M, VCLKx4, VCLK, PHASE,
+ BGCAD, BGCDT,
+ SPCAD, SPCDT,
+ gfx_rom_addr,gfx_rom_do
+);
+wire SPCFT = (PHASE==0)|(PHASE==2);
+wire CPUCLx2 = EXCITE ? CLK12M : CLK6M;
+
+wire [9:0] BGVAD;
+wire [15:0] BGVDT;
+wire [10:0] SPAAD;
+wire [7:0] SPADT;
+
+PKWARS_VIDEO video
+(
+ RESET, VCLKx4, VCLK,
+ PH, PV, POUT,
+ BGVAD, BGVDT, BGCAD, BGCDT,
+ SPAAD, SPADT, SPCAD, SPCDT, SPCFT
+);
+
+reg CPUCL;
+always @( posedge CPUCLx2 ) CPUCL <= ~CPUCL;
+
+wire [7:0] CPUID, CPUOD;
+wire CPURD, CPUWR;
+
+reg CPUIRQ, pVBLK;
+wire eVBLK = (VBLK^pVBLK) & VBLK;
+wire IRQFETCH = (CPURD&(CPUAD==16'h38))|RESET;
+always @( posedge CPUCL ) begin
+ pVBLK <= VBLK;
+ if (IRQFETCH) CPUIRQ <= 0;
+ else begin
+ if (eVBLK) CPUIRQ <= 1;
+ end
+end
+
+Z80IP cpu( RESET, CPUCL, CPUAD, CPUID, CPUOD, CPURD, CPUWR, CPUIRQ );
+
+wire RAMDV, SNDDV, VIDDV;
+wire [7:0] RAMDT, SNDDT, VIDDT;
+
+wire CPRDV = (~CPUAD[15])|(CPUAD[15:13]==3'b111);
+assign cpu_rom_addr = CPUAD;
+
+
+DSEL4D_8B cpudsel(
+ CPUID,
+ CPRDV, cpu_rom_do,
+ RAMDV, RAMDT,
+ VIDDV, VIDDT,
+ SNDDV, SNDDT
+);
+
+PKWARS_WRAM wram( CPUCLx2, CPUAD, CPUOD, CPUWR, CPURD, RAMDT, RAMDV );
+PKWARS_VRAM vram( CPUCLx2, CPUAD, CPUOD, CPUWR, CPURD, VIDDT, VIDDV, VRAMCL, SPAAD, SPADT, BGVAD, BGVDT, eVBLK );
+
+
+PKWARS_SND snd( CPUCLx2, CPUAD, CPUOD, CPUWR, CPURD, SNDDT, SNDDV, RESET, CLK3M, CTR1, CTR2, DSW, VBLK, SND );
+
+
+endmodule
+
+
+module PKWARS_WRAM
+(
+ input CPUCL,
+ input [15:0] CPUAD,
+ input [7:0] CPUOD,
+ input CPUWR,
+ input CPURD,
+ output reg [7:0] RAMDT,
+ output RAMDV
+);
+
+wire DV = (CPUAD[15:12]==4'hC);
+
+wire [10:0] AD = CPUAD[10:0];
+reg [7:0] ramcore[0:2047];
+
+always @( posedge CPUCL ) begin
+ if (DV) begin
+ if (CPUWR) ramcore[AD] <= CPUOD;
+ RAMDT <= ramcore[AD];
+ end
+end
+
+assign RAMDV = DV & CPURD;
+
+endmodule
+
+
+module PKWARS_VRAM
+(
+ input CPUCL,
+ input [15:0] CPUAD,
+ input [7:0] CPUOD,
+ input CPUWR,
+ input CPURD,
+
+ output [7:0] VIDDT,
+ output VIDDV,
+
+ input VIDCL,
+
+ input [10:0] SPAAD,
+ output [7:0] SPADT,
+
+ input [9:0] BGVAD,
+ output [15:0] BGVDT,
+
+ input eVBLK
+);
+
+wire VRDV = (CPUAD[15:12]==4'h8);
+wire SPDV = VRDV & (~CPUAD[11]);
+wire BGDV = VRDV & CPUAD[11];
+
+wire [7:0] SPDT, BGDT, dum;
+
+VDPRAM400x2 bgvram(
+ CPUCL, CPUAD[10:0], BGDV & CPUWR, CPUOD, BGDT,
+ VIDCL, BGVAD, BGVDT
+);
+
+wire DMACL = CPUCL;
+reg [1:0] DMAPH = 0;
+reg [10:0] DMAAD = 0;
+reg DMAWR = 0;
+wire [7:0] DMADT;
+always @(posedge DMACL) begin
+ case (DMAPH)
+ 0: begin DMAWR <= 0; DMAAD <= 0; DMAPH <= eVBLK ? (DMAPH+1) : DMAPH; end
+ 1: begin DMAWR <= 1; DMAPH <= DMAPH+1; end
+ 2: begin DMAWR <= 0; DMAAD <= DMAAD+1; DMAPH <= (DMAAD==11'h7FF) ? (DMAPH+1) : (DMAPH-1); end
+ 3: if (~eVBLK) begin DMAWR <= 0; DMAPH <= DMAPH+1; end
+ default: ;
+ endcase
+end
+
+DPRAM800 sparam0(
+ CPUCL, CPUAD[10:0], SPDV & CPUWR, CPUOD, SPDT,
+ ~DMACL, DMAAD, 1'b0, 8'h0, DMADT
+);
+
+DPRAM800 sparam(
+ ~DMACL, DMAAD, DMAWR, DMADT, dum,
+ VIDCL, SPAAD, 1'b0, 8'h0, SPADT
+);
+
+assign VIDDT = BGDV ? BGDT : SPDT;
+assign VIDDV = (SPDV|BGDV) & CPURD;
+
+endmodule
+
+
+module DSEL4D_8B
+(
+ output [7:0] out,
+
+ input en0,
+ input [7:0] dt0,
+ input en1,
+ input [7:0] dt1,
+ input en2,
+ input [7:0] dt2,
+ input en3,
+ input [7:0] dt3
+);
+
+assign out = en0 ? dt0 :
+ en1 ? dt1 :
+ en2 ? dt2 :
+ en3 ? dt3 :
+ 8'h00;
+
+endmodule
+
+
diff --git a/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/PKWARS_CLKGEN.v b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/PKWARS_CLKGEN.v
new file mode 100644
index 00000000..23a5f358
--- /dev/null
+++ b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/PKWARS_CLKGEN.v
@@ -0,0 +1,35 @@
+// Copyright (c) 2012 MiSTer-X
+
+module PKWARS_CLKGEN
+(
+ input MCLK, // 48MHz
+
+ output VCLKx4,
+ output VCLK,
+
+ output VRAMCL,
+ output PCLK,
+
+ output CLK24M,
+ output CLK12M,
+ output CLK6M,
+ output CLK3M
+);
+
+reg [3:0] CLKDIV;
+always @( posedge MCLK ) CLKDIV <= CLKDIV+1;
+
+assign VCLKx4 = CLKDIV[0]; // 24MHz
+assign VCLK = CLKDIV[2]; // 6MHz
+
+assign CLK24M = CLKDIV[0];
+assign CLK12M = CLKDIV[1];
+assign CLK6M = CLKDIV[2];
+assign CLK3M = CLKDIV[3];
+
+assign VRAMCL = ~VCLKx4;
+assign PCLK = ~VCLK;
+
+endmodule
+
+
diff --git a/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/PKWARS_HVGEN.v b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/PKWARS_HVGEN.v
new file mode 100644
index 00000000..d0d2b93b
--- /dev/null
+++ b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/PKWARS_HVGEN.v
@@ -0,0 +1,58 @@
+// Copyright (c) 2020 MiSTer-X
+
+module PKWARS_HVGEN
+(
+ output [8:0] HPOS,
+ output [8:0] VPOS,
+ input PCLK,
+ input [11:0] iRGB,
+
+ input [8:0] HOFFS,
+ input [8:0] VOFFS,
+
+ output reg [11:0] oRGB,
+ output reg HBLK = 1,
+ output reg VBLK = 1,
+ output reg HSYN = 1,
+ output reg VSYN = 1
+);
+
+reg [8:0] hcnt = 0;
+reg [8:0] vcnt = 0;
+
+assign HPOS = hcnt-5'd16;
+assign VPOS = vcnt-5'd24;
+
+wire [8:0] HS_B = 287+(HOFFS*2);
+wire [8:0] HS_E = 31+(HS_B);
+wire [8:0] HS_N = 447+(HOFFS*2);
+
+wire [8:0] VS_B = 219+(VOFFS*4);
+wire [8:0] VS_E = 7+(VS_B);
+wire [8:0] VS_N = 478+(VOFFS*4);
+
+always @(posedge PCLK) begin
+ case (hcnt)
+ 15: begin HBLK <= 0; hcnt <= hcnt+1'd1; end
+ 272: begin HBLK <= 1; hcnt <= hcnt+1'd1; end
+ 511: begin hcnt <= 0;
+ case (vcnt)
+ 215: begin VBLK <= 1; vcnt <= vcnt+1'd1; end
+ 23: begin VBLK <= 0; vcnt <= vcnt+1'd1; end
+ default: vcnt <= vcnt+1'd1;
+ endcase
+ end
+ default: hcnt <= hcnt+1'd1;
+ endcase
+
+ if (hcnt==HS_B) begin HSYN <= 0; end
+ if (hcnt==HS_E) begin HSYN <= 1; hcnt <= HS_N; end
+
+ if (vcnt==VS_B) begin VSYN <= 0; end
+ if (vcnt==VS_E) begin VSYN <= 1; vcnt <= VS_N; end
+
+ oRGB <= (HBLK|VBLK) ? 12'h0 : iRGB;
+end
+
+endmodule
+
diff --git a/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/PKWARS_MiST.sv b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/PKWARS_MiST.sv
new file mode 100644
index 00000000..f87a3647
--- /dev/null
+++ b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/PKWARS_MiST.sv
@@ -0,0 +1,286 @@
+module PKWARS_MiST (
+ output LED,
+ output [5:0] VGA_R,
+ output [5:0] VGA_G,
+ output [5:0] VGA_B,
+ output VGA_HS,
+ output VGA_VS,
+ output AUDIO_L,
+ output AUDIO_R,
+ input SPI_SCK,
+ output SPI_DO,
+ input SPI_DI,
+ input SPI_SS2,
+ input SPI_SS3,
+ input CONF_DATA0,
+ input CLOCK_27,
+ output [12:0] SDRAM_A,
+ inout [15:0] SDRAM_DQ,
+ output SDRAM_DQML,
+ output SDRAM_DQMH,
+ output SDRAM_nWE,
+ output SDRAM_nCAS,
+ output SDRAM_nRAS,
+ output SDRAM_nCS,
+ output [1:0] SDRAM_BA,
+ output SDRAM_CLK,
+ output SDRAM_CKE
+);
+
+`include "rtl\build_id.v"
+
+localparam CONF_STR = {
+ "PKUNWAR;ROM;",
+ "O2,Rotate Controls,Off,On;",
+ "O34,Scanlines,None,CRT 25%,CRT 50%,CRT 75%;",
+ "O5,Blend,Off,On;",
+ "O6,Service,Off,On;",
+ "O8,Excite Mode,Off,On;",
+ "OOS,Analog Video H-Pos,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31;",
+ "OTV,Analog Video V-Pos,0,1,2,3,4,5,6,7;",
+ "T0,Reset;",
+ "V,v1.00.",`BUILD_DATE
+};
+
+assign LED = ~ioctl_downl;
+assign AUDIO_R = AUDIO_L;
+assign SDRAM_CLK = clk_sd;
+assign SDRAM_CKE = 1;
+
+wire CLOCK_48, pll_locked, clk_sd;
+pll pll(
+ .inclk0(CLOCK_27),
+ .c0(CLOCK_48),
+ .c1(clk_sd),
+ .locked(pll_locked)
+ );
+
+wire [31:0] status;
+wire [1:0] buttons;
+wire [1:0] switches;
+wire [7:0] joystick_0;
+wire [7:0] joystick_1;
+wire scandoublerD;
+wire ypbpr;
+wire [15:0] audio;
+wire hs, vs, hb, vb;
+wire blankn = ~(hb | vb);
+wire [3:0] r, g, b;
+wire key_strobe;
+wire key_pressed;
+wire [7:0] key_code;
+
+wire ioctl_downl;
+wire [7:0] ioctl_index;
+wire ioctl_wr;
+wire [24:0] ioctl_addr;
+wire [7:0] ioctl_dout;
+
+/*
+ROM Structure
+cpu 64k pkwar.01r pkwar.02r FFFF pkwar.03r
+gfx 64k pkwar.01y pkwar.02y pkwar.03y pkwar.04y
+col 32b
+*/
+
+data_io data_io(
+ .clk_sys ( CLOCK_48 ),
+ .SPI_SCK ( SPI_SCK ),
+ .SPI_SS2 ( SPI_SS2 ),
+ .SPI_DI ( SPI_DI ),
+ .ioctl_download( ioctl_downl ),
+ .ioctl_index ( ioctl_index ),
+ .ioctl_wr ( ioctl_wr ),
+ .ioctl_addr ( ioctl_addr ),
+ .ioctl_dout ( ioctl_dout )
+);
+
+
+wire [15:0] cpu_rom_addr;
+wire [15:0] cpu_rom_do;
+
+wire [13:0] gfx_rom_addr;
+wire [31:0] gfx_rom_do;
+
+
+wire [24:0] bg_ioctl_addr = ioctl_addr - 17'h8000;
+
+reg port1_req, port2_req;
+sdram sdram(
+ .*,
+ .init_n ( pll_locked ),
+ .clk ( clk_sd ),
+
+ .port1_req ( port1_req ),
+ .port1_ack ( ),
+ .port1_a ( ioctl_addr[23:1] ),
+ .port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
+ .port1_we ( ioctl_downl ),
+ .port1_d ( {ioctl_dout, ioctl_dout} ),
+ .port1_q ( ),
+
+ .cpu1_addr ( ioctl_downl ? 16'hffff : cpu_rom_addr[15:1] ),
+ .cpu1_q ( cpu_rom_do ),
+ .cpu2_addr ( 16'hffff ),
+ .cpu2_q ( ),
+
+ // port2 for sprite graphics
+ .port2_req ( port2_req ),
+ .port2_ack ( ),
+ .port2_a ( {bg_ioctl_addr[13:0], bg_ioctl_addr[15]} ), // merge sprite roms to 32-bit wide words
+ .port2_ds ( {bg_ioctl_addr[14], ~bg_ioctl_addr[14]} ),
+ .port2_we ( ioctl_downl ),
+ .port2_d ( {ioctl_dout, ioctl_dout} ),
+ .port2_q ( ),
+
+ .sp_addr ( ioctl_downl ? 16'hffff : gfx_rom_addr ),
+ .sp_q ( gfx_rom_do )
+);
+
+// ROM download controller
+always @(posedge CLOCK_48) begin
+ reg ioctl_wr_last = 0;
+
+ ioctl_wr_last <= ioctl_wr;
+ if (ioctl_downl) begin
+ if (~ioctl_wr_last && ioctl_wr) begin
+ port1_req <= ~port1_req;
+ port2_req <= ~port2_req;
+ end
+ end
+end
+
+reg reset = 1;
+reg rom_loaded = 0;
+always @(posedge CLOCK_48) begin
+ reg ioctl_downlD;
+ ioctl_downlD <= ioctl_downl;
+ if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
+ reset <= status[0] | buttons[1] | ~rom_loaded;
+end
+
+wire PCLK;
+wire [8:0] HPOS,VPOS;
+wire [11:0] POUT;
+
+FPGA_PKWARS FPGA_PKWARS(
+ .clk48M(CLOCK_48),
+ .RESET(reset),
+ .EXCITE(status[8]), // Excite Mode (Double the CPU clock)
+ .CTR1(~{1'b0,status[6], btn_one_player, 2'b00, m_fire, m_right, m_left }),
+ .CTR2(~{~btn_coin, 1'b0, btn_two_players, 2'b00, m_fire, m_right, m_left }),
+ .DSW(8'b11111111),
+ .PH(HPOS),
+ .PV(VPOS),
+ .PCLK(PCLK),
+ .POUT(oPIX),
+ .SND(audio),
+ .cpu_rom_addr(cpu_rom_addr),
+ .cpu_rom_do(cpu_rom_addr[0] ? cpu_rom_do[15:8] : cpu_rom_do[7:0]),
+ .gfx_rom_addr(gfx_rom_addr),
+ .gfx_rom_do(gfx_rom_do)
+);
+
+wire [11:0] oPIX;
+wire [4:0] HOFFS = status[28:24];
+wire [2:0] VOFFS = status[31:29];
+PKWARS_HVGEN PKWARS_HVGEN(
+ .HPOS(HPOS),
+ .VPOS(VPOS),
+ .PCLK(PCLK),
+ .iRGB(oPIX),
+ .HOFFS(HOFFS),
+ .VOFFS(VOFFS),
+ .oRGB({b,g,r}),
+ .HBLK(hb),
+ .VBLK(vb),
+ .HSYN(hs),
+ .VSYN(vs)
+);
+
+mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(11)) mist_video(
+ .clk_sys ( CLOCK_48 ),
+ .SPI_SCK ( SPI_SCK ),
+ .SPI_SS3 ( SPI_SS3 ),
+ .SPI_DI ( SPI_DI ),
+ .R ( blankn ? r : 0 ),
+ .G ( blankn ? g : 0 ),
+ .B ( blankn ? b : 0 ),
+ .HSync ( hs ),
+ .VSync ( vs ),
+ .VGA_R ( VGA_R ),
+ .VGA_G ( VGA_G ),
+ .VGA_B ( VGA_B ),
+ .VGA_VS ( VGA_VS ),
+ .VGA_HS ( VGA_HS ),
+ .rotate ( {1'b1,status[2]} ),
+ .ce_divider ( 1'b1 ),
+ .blend ( status[5] ),
+ .scandoubler_disable( scandoublerD ),
+ .scanlines ( status[4:3] ),
+ .ypbpr ( ypbpr )
+ );
+
+user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io(
+ .clk_sys (CLOCK_48 ),
+ .conf_str (CONF_STR ),
+ .SPI_CLK (SPI_SCK ),
+ .SPI_SS_IO (CONF_DATA0 ),
+ .SPI_MISO (SPI_DO ),
+ .SPI_MOSI (SPI_DI ),
+ .buttons (buttons ),
+ .switches (switches ),
+ .scandoubler_disable (scandoublerD ),
+ .ypbpr (ypbpr ),
+ .key_strobe (key_strobe ),
+ .key_pressed (key_pressed ),
+ .key_code (key_code ),
+ .joystick_0 (joystick_0 ),
+ .joystick_1 (joystick_1 ),
+ .status (status )
+ );
+
+dac #(.C_bits(16))dac(
+ .clk_i(CLOCK_48),
+ .res_n_i(1),
+ .dac_i(audio),
+ .dac_o(AUDIO_L)
+ );
+// Rotated Normal
+//wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
+//wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
+wire m_left = status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
+wire m_right = status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
+wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4];
+//wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5];
+
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_left = 0;
+reg btn_right = 0;
+reg btn_down = 0;
+reg btn_up = 0;
+reg btn_fire1 = 0;
+reg btn_fire2 = 0;
+//reg btn_fire3 = 0;
+reg btn_coin = 0;
+
+always @(posedge CLOCK_48) begin
+ if(key_strobe) begin
+ case(key_code)
+ 'h75: btn_up <= key_pressed; // up
+ 'h72: btn_down <= key_pressed; // down
+ 'h6B: btn_left <= key_pressed; // left
+ 'h74: btn_right <= key_pressed; // right
+ 'h76: btn_coin <= key_pressed; // ESC
+ 'h05: btn_one_player <= key_pressed; // F1
+ 'h06: btn_two_players <= key_pressed; // F2
+// 'h14: btn_fire3 <= key_pressed; // ctrl
+ 'h11: btn_fire2 <= key_pressed; // alt
+ 'h29: btn_fire1 <= key_pressed; // Space
+ endcase
+ end
+end
+
+
+endmodule
diff --git a/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/PKWARS_ROMARB.v b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/PKWARS_ROMARB.v
new file mode 100644
index 00000000..491812b4
--- /dev/null
+++ b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/PKWARS_ROMARB.v
@@ -0,0 +1,34 @@
+// Copyright (c) 2012,20 MiSTer-X
+
+module PKWARS_ROMS
+(
+ input CLKx2,
+ input CLK,
+ input VCLK,
+
+ output reg [1:0] PHASE,
+ input [13:0]BGCAD,
+ output reg [31:0]BGCDT,
+
+ input [13:0]SPCAD,
+ output reg [31:0]SPCDT,
+ output [13:0]gfx_rom_addr,
+ input [31:0]gfx_rom_do
+);
+
+
+always @( negedge CLK ) PHASE <= PHASE+1;
+
+reg sd;
+
+wire [13:0] AD = sd ? SPCAD : BGCAD;
+
+assign gfx_rom_addr = AD;
+
+always @( negedge CLKx2 ) begin
+ if (sd) SPCDT <= gfx_rom_do;
+ else BGCDT <= gfx_rom_do;
+ sd <= ~sd;
+end
+
+endmodule
diff --git a/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/PKWARS_SND.v b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/PKWARS_SND.v
new file mode 100644
index 00000000..a6721203
--- /dev/null
+++ b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/PKWARS_SND.v
@@ -0,0 +1,131 @@
+// Copyright (c) 2012 MiSTer-X
+
+module PKWARS_SND
+(
+ input CPUCL,
+ input [15:0] CPUAD,
+ input [7:0] CPUOD,
+ input CPUWR,
+ input CPURD,
+ output [7:0] SNDDT,
+ output SNDDV,
+
+ input RESET,
+ input CLK3M,
+ input [7:0] CTR1,
+ input [7:0] CTR2,
+ input [7:0] DSW,
+ input VBLK,
+
+ output [15:0] SNDOUT
+);
+
+wire DV = (CPUAD[15:12]==4'hA);
+assign SNDDV = CPURD & DV;
+
+reg PSGCL;
+always @( posedge CLK3M ) PSGCL <= ~PSGCL;
+
+wire [7:0] IN0 = {~VBLK,CTR1[6:0]};
+wire [7:0] IN1 = CTR2;
+
+PKWARS_PSG psgs(
+ CPUCL, PSGCL,
+ CPUAD[1:0], DV, CPUWR, CPUOD, SNDDT,
+ RESET, CPURD,
+ IN0, IN1, DSW,
+ SNDOUT
+);
+
+endmodule
+
+module PKWARS_PSG
+(
+ input AXSCLK,
+ input CLK,
+ input [1:0] ADR,
+ input CS,
+ input WR,
+ input [7:0] ID,
+ output [7:0] OD,
+
+ input RESET,
+ input RD,
+
+ input [7:0] IN0,
+ input [7:0] IN1,
+ input [7:0] DSW,
+
+ output [15:0] SNDOUT
+);
+
+wire [7:0] IN2 = 8'hFF;
+wire [7:0] OD0, OD1;
+
+wire [9:0] S0, S1;
+
+PSG psg1(RESET, AXSCLK, CLK, ~ADR[0], CS & (~ADR[1]), WR, RD, ID, OD0, S0, IN0, IN1);
+PSG psg2(RESET, AXSCLK, CLK, ~ADR[0], CS & ( ADR[1]), WR, RD, ID, OD1, S1, IN2, DSW);
+
+wire [12:0] SMIX = S0+S1;
+wire [11:0] SCLP = SMIX[11:0]|{12{SMIX[12]}};
+assign SNDOUT = {SCLP,4'h0};
+
+assign OD = ADR[1] ? OD1 : OD0;
+
+endmodule
+
+
+module PSG
+(
+ input RST,
+ input ACLK,
+ input CLK,
+
+ input AS,
+ input CS,
+ input WR,
+ input RD,
+
+ input [7:0] ID,
+ output [7:0] OD,
+
+ output [9:0] SO,
+
+ input [7:0] IA,
+ input [7:0] IB
+);
+
+wire [7:0] Sx;
+wire [1:0] Sc;
+reg [7:0] SA,SB,SC;
+always @(negedge CLK or posedge RST) begin
+ if (RST) begin
+ SA <= 0;
+ SB <= 0;
+ SC <= 0;
+ end
+ else case (Sc)
+ 2'd0: SA <= Sx;
+ 2'd1: SB <= Sx;
+ 2'd2: SC <= Sx;
+ default:;
+ endcase
+end
+
+wire bd = CS & (WR|AS);
+wire bc = CS & ((~WR)|AS);
+
+YM2149m sg
+(
+ .I_DA(ID),.O_DA(OD),.I_A9_L(~CS),.I_BC1(bc),.I_BDIR(bd),
+ .I_A8(1'b1),.I_BC2(1'b1),.I_SEL_L(1'b1),
+ .O_AUDIO(Sx),.O_CHAN(Sc),
+ .I_IOA(IA),.I_IOB(IB),
+ .ENA(1'b1),.RESET_L(~RST),.CLK(CLK),.ACLK(ACLK)
+);
+
+assign SO = SA+SB+SC;
+
+endmodule
+
diff --git a/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/PKWARS_SPRITE.v b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/PKWARS_SPRITE.v
new file mode 100644
index 00000000..4b9dfd5f
--- /dev/null
+++ b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/PKWARS_SPRITE.v
@@ -0,0 +1,222 @@
+// Copyright (c) 2012,20 MiSTer-X
+
+module PKWARS_SP
+(
+ input VCLKx4,
+ input VCLK,
+
+ input [8:0] PH,
+ input [8:0] PV,
+
+ output [10:0] SPAAD,
+ input [7:0] SPADT,
+
+ output [13:0] SPCAD,
+ input [31:0] SPCDT,
+ input SPCFT,
+
+ output [3:0] SPOUT
+);
+
+wire WPEN;
+wire [8:0] WPAD;
+wire [7:0] WPIX;
+
+reg [7:0] POUT;
+wire [3:0] OTHP = (POUT[3:0]==1) ? POUT[7:4] : POUT[3:0];
+
+wire [8:0] WP = {1'b0,WPAD[7:0]};
+
+
+wire [7:0] PO;
+wire [9:0] rad = {~PV[0], PH};
+reg [9:0] pad = 1;
+always @(posedge VCLK) begin
+ if (pad!=rad) begin
+ pad <= rad;
+ POUT <= PO;
+ end
+end
+
+LineDBuf ldbuf(
+ VCLKx4, rad, PO, (pad==rad),
+ ~VCLKx4, { PV[0], WP}, WPIX, WPEN
+);
+
+PKWARS_SPENG eng (
+ VCLKx4, PH, PV,
+ SPAAD, SPADT,
+ SPCAD, SPCDT, SPCFT,
+ WPAD, WPIX, WPEN
+);
+
+assign SPOUT = OTHP;
+
+endmodule
+
+
+module PKWARS_SPENG
+(
+ input VCLKx4,
+
+ input [8:0] PH,
+ input [8:0] PV,
+
+ output [10:0] SPAAD,
+ input [7:0] SPADT,
+
+ output [13:0] SPCAD,
+ input [31:0] SPCDT,
+ input SPCFT,
+
+ output [8:0] WPAD,
+ output [7:0] WPIX,
+ output WPEN
+);
+
+reg [5:0] SPRNO;
+reg [1:0] SPRIX;
+assign SPAAD = {SPRNO, 3'h0, SPRIX};
+
+reg [7:0] PTNO;
+reg [7:0] ATTR;
+wire [3:0] PALNO = ATTR[7:4];
+wire FLIPH = PTNO[0];
+wire FLIPV = PTNO[1];
+wire XPOSH = 1'b0;
+wire DSABL = ATTR[3];
+
+reg [7:0] YPOS;
+reg [7:0] NV;
+wire [7:0] HV = NV-YPOS;
+wire [3:0] LV = {4{FLIPV}}^(HV[3:0]);
+wire YHIT = (HV[7:4]==4'b1111) & (~DSABL);
+
+reg [7:0] XPOS;
+reg [4:0] WP;
+wire [3:0] WOFS = {4{FLIPH}}^(WP[3:0]);
+assign WPAD = {1'b0,XPOS}-{XPOSH,8'h0}+WOFS-1;
+assign WPEN = ~(WP[4]|(WPIX[3:0]==0));
+
+reg CRS;
+wire [8:0] PATNO = {ATTR[2:0],PTNO[7:2]};
+assign SPCAD = {PATNO, LV[3], CRS, LV[2:0]};
+
+function [3:0] XOUT;
+input [2:0] N;
+input [31:0] CDT;
+ case(N)
+ 0: XOUT = CDT[7:4];
+ 1: XOUT = CDT[3:0];
+ 2: XOUT = CDT[15:12];
+ 3: XOUT = CDT[11:8];
+ 4: XOUT = CDT[23:20];
+ 5: XOUT = CDT[19:16];
+ 6: XOUT = CDT[31:28];
+ 7: XOUT = CDT[27:24];
+ endcase
+endfunction
+reg [31:0] CDT0, CDT1;
+assign WPIX = {PALNO, XOUT(WP[2:0],WP[3] ? CDT1 : CDT0)};
+
+
+`define WAIT 0
+`define FETCH0 1
+`define FETCH1 2
+`define FETCH2 3
+`define FETCH3 4
+`define FETCH4 5
+`define DRAW 6
+`define NEXT 7
+
+reg [2:0] STATE;
+always @( posedge VCLKx4 ) begin
+ case (STATE)
+
+ `WAIT: begin
+ WP <= 16;
+ if (~PH[8]) begin
+ NV <= PV+17;
+ SPRNO <= 0;
+ SPRIX <= 2;
+ STATE <= `FETCH0;
+ end
+ end
+
+ `FETCH0: begin
+ YPOS <= SPADT;
+ SPRIX <= 3;
+ STATE <= `FETCH1;
+ end
+ `FETCH1: begin
+ ATTR = SPADT; /* ATTR must block assign */
+ SPRIX <= 0;
+ STATE <= YHIT ? `FETCH2 : `NEXT;
+ end
+
+ `FETCH2: begin
+ PTNO <= SPADT;
+ SPRIX <= 1;
+ STATE <= `FETCH3;
+ end
+ `FETCH3: begin
+ if (SPCFT) begin // Wait for CHRROM fetch cycle
+ XPOS <= SPADT;
+ CRS <= 0;
+ STATE <= `FETCH4;
+ end
+ end
+ `FETCH4: begin
+ if (SPCFT) begin // Fetch CHRROM data (16pixels)
+ if (~CRS) begin
+ CDT0 <= SPCDT;
+ CRS <= 1;
+ end
+ else begin
+ CDT1 <= SPCDT;
+ WP <= 0;
+ STATE <= `DRAW;
+ end
+ end
+ end
+
+ `DRAW: begin
+ WP <= WP+1;
+ if (WP[4]) STATE <= `NEXT;
+ end
+
+ `NEXT: begin
+ CDT0 <= 0; CDT1 <= 0;
+ SPRNO <= SPRNO+1;
+ SPRIX <= 2;
+ STATE <= (SPRNO==63) ? `WAIT : `FETCH0;
+ end
+
+ endcase
+end
+
+endmodule
+
+
+module LineDBuf
+(
+ input rC,
+ input [9:0] rA,
+ output [7:0] rD,
+ input rE,
+
+ input wC,
+ input [9:0] wA,
+ input [7:0] wD,
+ input wE
+);
+
+DPRAM1024 mem(
+ rA, wA,
+ rC, wC,
+ 0, wD,
+ rE, wE,
+ rD
+);
+
+endmodule
diff --git a/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/PKWARS_VIDEO.v b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/PKWARS_VIDEO.v
new file mode 100644
index 00000000..3efb2f85
--- /dev/null
+++ b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/PKWARS_VIDEO.v
@@ -0,0 +1,127 @@
+// Copyright (c) 2012,20 MiSTer-X
+
+module PKWARS_VIDEO
+(
+ input RESET,
+ input VCLKx4,
+ input VCLK,
+
+ input [8:0] PH,
+ input [8:0] PV,
+
+ output [11:0] POUT,
+
+ output [9:0] BGVAD, // BG
+ input [15:0] BGVDT,
+ output [13:0] BGCAD,
+ input [31:0] BGCDT,
+
+ output [10:0] SPAAD, // Sprite
+ input [7:0] SPADT,
+ output [13:0] SPCAD,
+ input [31:0] SPCDT,
+ input SPCFT
+);
+
+
+
+// BackGround Scanline Generator
+wire [4:0] BGOUT;
+PKWARS_BG BG(
+ VCLK,
+ PH, PV,
+ BGVAD, BGVDT,
+ BGCAD, BGCDT,
+ BGOUT
+);
+
+// Sprite Scanline Generator
+wire [3:0] SPOUT;
+PKWARS_SP SP(
+ VCLKx4, VCLK,
+ PH, PV,
+ SPAAD, SPADT,
+ SPCAD, SPCDT, SPCFT,
+ SPOUT
+);
+
+// Plane Mixer
+wire [4:0] PALDS = {PV[3],PH[7:4]};
+
+wire BGHPR = (BGOUT[4])&(BGOUT[3:0]!=0);
+wire [4:0] BGCOL = {1'b1,BGOUT[3:0]};
+
+wire SPOPQ = (SPOUT!=0);
+wire [4:0] SPCOL = {1'b0,SPOUT};
+
+assign PALAD = //DBGPD ? PALDS :
+ BGHPR ? BGCOL :
+ SPOPQ ? SPCOL :
+ BGCOL ;
+
+// Color Palette
+wire [3:0] ro = {PALDT[3:2],PALDT[1:0]};
+wire [3:0] go = {PALDT[5:4],PALDT[1:0]};
+wire [3:0] bo = {PALDT[7:6],PALDT[1:0]};
+
+assign POUT = {bo,go,ro};
+
+wire [4:0] PALAD;
+wire [7:0] PALDT;
+
+col col(
+ .clk(VCLKx4),
+ .addr(PALAD),
+ .data(PALDT)
+);
+
+endmodule
+
+
+// BackGround Scanline Generator
+module PKWARS_BG
+(
+ input VCLK,
+
+ input [8:0] PH, // CRTC
+ input [8:0] PV,
+
+ output [9:0] BGVAD, // VRAM
+ input [15:0] BGVDT,
+
+ output reg [13:0] BGCAD, // CHR-ROM
+ input [31:0] BGCDT,
+
+ output [4:0] BGOUT // OUTPUT
+);
+
+wire [8:0] POSH = PH+2;
+wire [8:0] POSV = PV+32;
+
+reg [4:0] PALET;
+wire [10:0] CHRNO = BGVDT[10:0];
+wire [3:0] PIXEL = POSH[0] ? BGCDT[3:0] : BGCDT[7:4];
+
+reg [8:0] POUT;
+always @( posedge VCLK ) begin
+ BGCAD <= {CHRNO,POSV[2:0]};
+ PALET <= {BGVDT[11],BGVDT[15:12]};
+ case(POSH[2:0])
+ 1: POUT <= {PALET,BGCDT[7:4] };
+ 2: POUT <= {PALET,BGCDT[3:0] };
+ 3: POUT <= {PALET,BGCDT[15:12]};
+ 4: POUT <= {PALET,BGCDT[11:8] };
+ 5: POUT <= {PALET,BGCDT[23:20]};
+ 6: POUT <= {PALET,BGCDT[19:16]};
+ 7: POUT <= {PALET,BGCDT[31:28]};
+ 0: POUT <= {PALET,BGCDT[27:24]};
+ endcase
+end
+
+wire [3:0] OTHP = (POUT[3:0]==1) ? POUT[7:4] : POUT[3:0];
+
+assign BGVAD = {POSV[7:3],POSH[7:3]};
+assign BGOUT = {POUT[8],OTHP};
+
+endmodule
+
diff --git a/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/YM2149_linmix_sep_mod.vhd b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/YM2149_linmix_sep_mod.vhd
new file mode 100644
index 00000000..19fb1e60
--- /dev/null
+++ b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/YM2149_linmix_sep_mod.vhd
@@ -0,0 +1,576 @@
+-- changes for seperate audio outputs and enable now enables cpu access as well
+--
+-- A simulation model of YM2149 (AY-3-8910 with bells on)
+
+-- Copyright (c) MikeJ - Jan 2005
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- You are responsible for any legal issues arising from your use of this code.
+--
+-- The latest version of this file can be found at: www.fpgaarcade.com
+--
+-- Email support@fpgaarcade.com
+--
+-- Revision list
+--
+-- version 001 initial release
+--
+-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA
+--
+-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V)
+-- vol 15 .. 0
+-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132
+-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order
+-- to produced all the required values.
+-- (The first part of the curve is a bit steeper and the last bit is more linear than expected)
+--
+-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only
+-- accurate for designs where the outputs are buffered and not simply wired together.
+-- The ouput level is more complex in that case and requires a larger table.
+
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
+
+entity YM2149m is
+ port (
+ -- data bus
+ I_DA : in std_logic_vector(7 downto 0);
+ O_DA : out std_logic_vector(7 downto 0);
+ O_DA_OE_L : out std_logic;
+ -- control
+ I_A9_L : in std_logic;
+ I_A8 : in std_logic;
+ I_BDIR : in std_logic;
+ I_BC2 : in std_logic;
+ I_BC1 : in std_logic;
+ I_SEL_L : in std_logic;
+
+ O_AUDIO : out std_logic_vector(7 downto 0);
+ O_CHAN : out std_logic_vector(1 downto 0);
+ -- port a
+ I_IOA : in std_logic_vector(7 downto 0);
+ O_IOA : out std_logic_vector(7 downto 0);
+ O_IOA_OE_L : out std_logic;
+ -- port b
+ I_IOB : in std_logic_vector(7 downto 0);
+ O_IOB : out std_logic_vector(7 downto 0);
+ O_IOB_OE_L : out std_logic;
+
+ ENA : in std_logic; -- clock enable for higher speed operation
+ RESET_L : in std_logic;
+ CLK : in std_logic; -- note 6 Mhz
+
+ ACLK : in std_logic -- (Modified by MiSTer-X)
+);
+end;
+
+architecture RTL of YM2149m is
+ type array_16x8 is array (0 to 15) of std_logic_vector( 7 downto 0);
+ type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0);
+
+ signal cnt_div : std_logic_vector(3 downto 0) := (others => '0');
+ signal cnt_div_t1 : std_logic_vector(3 downto 0);
+ signal noise_div : std_logic := '0';
+ signal ena_div : std_logic;
+ signal ena_div_noise : std_logic;
+ signal poly17 : std_logic_vector(16 downto 0) := (others => '0');
+
+ -- registers
+ signal addr : std_logic_vector(7 downto 0);
+ signal busctrl_addr : std_logic;
+ signal busctrl_we : std_logic;
+ signal busctrl_re : std_logic;
+
+ signal reg : array_16x8;
+ signal env_reset : std_logic;
+ signal ioa_inreg : std_logic_vector(7 downto 0);
+ signal iob_inreg : std_logic_vector(7 downto 0);
+
+ signal noise_gen_cnt : std_logic_vector(4 downto 0);
+ signal noise_gen_op : std_logic;
+ signal tone_gen_cnt : array_3x12 := (others => (others => '0'));
+ signal tone_gen_op : std_logic_vector(3 downto 1) := "000";
+
+ signal env_gen_cnt : std_logic_vector(15 downto 0);
+ signal env_ena : std_logic;
+ signal env_hold : std_logic;
+ signal env_inc : std_logic;
+ signal env_vol : std_logic_vector(4 downto 0);
+
+ signal tone_ena_l : std_logic;
+ signal tone_src : std_logic;
+ signal noise_ena_l : std_logic;
+ signal chan_vol : std_logic_vector(4 downto 0);
+
+ signal dac_amp : std_logic_vector(7 downto 0);
+begin
+ -- cpu i/f
+ p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8)
+ variable cs : std_logic;
+ variable sel : std_logic_vector(2 downto 0);
+ begin
+ -- BDIR BC2 BC1 MODE
+ -- 0 0 0 inactive
+ -- 0 0 1 address
+ -- 0 1 0 inactive
+ -- 0 1 1 read
+ -- 1 0 0 address
+ -- 1 0 1 inactive
+ -- 1 1 0 write
+ -- 1 1 1 read
+ busctrl_addr <= '0';
+ busctrl_we <= '0';
+ busctrl_re <= '0';
+
+ cs := '0';
+ if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then
+ cs := '1';
+ end if;
+
+ sel := (I_BDIR & I_BC2 & I_BC1);
+ case sel is
+ when "000" => null;
+ when "001" => busctrl_addr <= '1';
+ when "010" => null;
+ when "011" => busctrl_re <= cs;
+ when "100" => busctrl_addr <= '1';
+ when "101" => null;
+ when "110" => busctrl_we <= cs;
+ when "111" => busctrl_addr <= '1';
+ when others => null;
+ end case;
+ end process;
+
+ p_oe : process(busctrl_re)
+ begin
+ -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns
+ O_DA_OE_L <= not (busctrl_re);
+ end process;
+
+ --
+ -- CLOCKED
+ --
+ p_waddr : process(RESET_L, ACLK)
+ begin
+ -- looks like registers are latches in real chip, but the address is caught at the end of the address state.
+ if (RESET_L = '0') then
+ addr <= (others => '0');
+ elsif rising_edge(ACLK) then
+ if (ENA = '1') then
+ if (busctrl_addr = '1') then
+ addr <= I_DA;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ p_wdata : process(RESET_L, ACLK)
+ begin
+ if (RESET_L = '0') then
+ reg <= (others => (others => '0'));
+ env_reset <= '1';
+ elsif rising_edge(ACLK) then
+ if (ENA = '1') then
+ env_reset <= '0';
+ if (busctrl_we = '1') then
+ case addr(3 downto 0) is
+ when x"0" => reg(0) <= I_DA;
+ when x"1" => reg(1) <= I_DA;
+ when x"2" => reg(2) <= I_DA;
+ when x"3" => reg(3) <= I_DA;
+ when x"4" => reg(4) <= I_DA;
+ when x"5" => reg(5) <= I_DA;
+ when x"6" => reg(6) <= I_DA;
+ when x"7" => reg(7) <= I_DA;
+ when x"8" => reg(8) <= I_DA;
+ when x"9" => reg(9) <= I_DA;
+ when x"A" => reg(10) <= I_DA;
+ when x"B" => reg(11) <= I_DA;
+ when x"C" => reg(12) <= I_DA;
+ when x"D" => reg(13) <= I_DA; env_reset <= '1';
+ when x"E" => reg(14) <= I_DA;
+ when x"F" => reg(15) <= I_DA;
+ when others => null;
+ end case;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ p_rdata : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg)
+ begin
+ O_DA <= (others => '0'); -- 'X'
+ if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator
+ case addr(3 downto 0) is
+ when x"0" => O_DA <= reg(0) ;
+ when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ;
+ when x"2" => O_DA <= reg(2) ;
+ when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ;
+ when x"4" => O_DA <= reg(4) ;
+ when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ;
+ when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ;
+ when x"7" => O_DA <= reg(7) ;
+ when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ;
+ when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ;
+ when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ;
+ when x"B" => O_DA <= reg(11);
+ when x"C" => O_DA <= reg(12);
+ when x"D" => O_DA <= "0000" & reg(13)(3 downto 0);
+ when x"E" => if (reg(7)(6) = '0') then -- input
+ O_DA <= ioa_inreg;
+ else
+ O_DA <= reg(14); -- read output reg
+ end if;
+ when x"F" => if (Reg(7)(7) = '0') then
+ O_DA <= iob_inreg;
+ else
+ O_DA <= reg(15);
+ end if;
+ when others => null;
+ end case;
+ end if;
+ end process;
+ --
+ p_divider : process
+ begin
+ wait until rising_edge(CLK);
+ -- / 8 when SEL is high and /16 when SEL is low
+ if (ENA = '1') then
+ ena_div <= '0';
+ ena_div_noise <= '0';
+ if (cnt_div = "0000") then
+ cnt_div <= (not I_SEL_L) & "111";
+ ena_div <= '1';
+
+ noise_div <= not noise_div;
+ if (noise_div = '1') then
+ ena_div_noise <= '1';
+ end if;
+ else
+ cnt_div <= cnt_div - "1";
+ end if;
+ end if;
+ end process;
+
+ p_noise_gen : process
+ variable noise_gen_comp : std_logic_vector(4 downto 0);
+ variable poly17_zero : std_logic;
+ begin
+ wait until rising_edge(CLK);
+ if (reg(6)(4 downto 0) = "00000") then
+ noise_gen_comp := "00000";
+ else
+ noise_gen_comp := (reg(6)(4 downto 0) - "1");
+ end if;
+
+ poly17_zero := '0';
+ if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
+
+ if (ENA = '1') then
+ if (ena_div_noise = '1') then -- divider ena
+
+ if (noise_gen_cnt >= noise_gen_comp) then
+ noise_gen_cnt <= "00000";
+ poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1);
+ else
+ noise_gen_cnt <= (noise_gen_cnt + "1");
+ end if;
+ end if;
+ end if;
+ end process;
+ noise_gen_op <= poly17(0);
+
+ p_tone_gens : process
+ variable tone_gen_freq : array_3x12;
+ variable tone_gen_comp : array_3x12;
+ begin
+ wait until rising_edge(CLK);
+ -- looks like real chips count up - we need to get the Exact behaviour ..
+ tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0);
+ tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2);
+ tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4);
+ -- period 0 = period 1
+ for i in 1 to 3 loop
+ if (tone_gen_freq(i) = x"000") then
+ tone_gen_comp(i) := x"000";
+ else
+ tone_gen_comp(i) := (tone_gen_freq(i) - "1");
+ end if;
+ end loop;
+
+ if (ENA = '1') then
+ for i in 1 to 3 loop
+ if (ena_div = '1') then -- divider ena
+
+ if (tone_gen_cnt(i) >= tone_gen_comp(i)) then
+ tone_gen_cnt(i) <= x"000";
+ tone_gen_op(i) <= not tone_gen_op(i);
+ else
+ tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1");
+ end if;
+ end if;
+ end loop;
+ end if;
+ end process;
+
+ p_envelope_freq : process
+ variable env_gen_freq : std_logic_vector(15 downto 0);
+ variable env_gen_comp : std_logic_vector(15 downto 0);
+ begin
+ wait until rising_edge(CLK);
+ env_gen_freq := reg(12) & reg(11);
+ -- envelope freqs 1 and 0 are the same.
+ if (env_gen_freq = x"0000") then
+ env_gen_comp := x"0000";
+ else
+ env_gen_comp := (env_gen_freq - "1");
+ end if;
+
+ if (ENA = '1') then
+ env_ena <= '0';
+ if (ena_div = '1') then -- divider ena
+ if (env_gen_cnt >= env_gen_comp) then
+ env_gen_cnt <= x"0000";
+ env_ena <= '1';
+ else
+ env_gen_cnt <= (env_gen_cnt + "1");
+ end if;
+ end if;
+ end if;
+ end process;
+
+ p_envelope_shape : process(env_reset, reg, CLK)
+ variable is_bot : boolean;
+ variable is_bot_p1 : boolean;
+ variable is_top_m1 : boolean;
+ variable is_top : boolean;
+ begin
+ -- envelope shapes
+ -- C AtAlH
+ -- 0 0 x x \___
+ --
+ -- 0 1 x x /___
+ --
+ -- 1 0 0 0 \\\\
+ --
+ -- 1 0 0 1 \___
+ --
+ -- 1 0 1 0 \/\/
+ -- ___
+ -- 1 0 1 1 \
+ --
+ -- 1 1 0 0 ////
+ -- ___
+ -- 1 1 0 1 /
+ --
+ -- 1 1 1 0 /\/\
+ --
+ -- 1 1 1 1 /___
+ if (env_reset = '1') then
+ -- load initial state
+ if (reg(13)(2) = '0') then -- attack
+ env_vol <= "11111";
+ env_inc <= '0'; -- -1
+ else
+ env_vol <= "00000";
+ env_inc <= '1'; -- +1
+ end if;
+ env_hold <= '0';
+
+ elsif rising_edge(CLK) then
+ is_bot := (env_vol = "00000");
+ is_bot_p1 := (env_vol = "00001");
+ is_top_m1 := (env_vol = "11110");
+ is_top := (env_vol = "11111");
+
+ if (ENA = '1') then
+ if (env_ena = '1') then
+ if (env_hold = '0') then
+ if (env_inc = '1') then
+ env_vol <= (env_vol + "00001");
+ else
+ env_vol <= (env_vol + "11111");
+ end if;
+ end if;
+
+ -- envelope shape control.
+ if (reg(13)(3) = '0') then
+ if (env_inc = '0') then -- down
+ if is_bot_p1 then env_hold <= '1'; end if;
+ else
+ if is_top then env_hold <= '1'; end if;
+ end if;
+ else
+ if (reg(13)(0) = '1') then -- hold = 1
+ if (env_inc = '0') then -- down
+ if (reg(13)(1) = '1') then -- alt
+ if is_bot then env_hold <= '1'; end if;
+ else
+ if is_bot_p1 then env_hold <= '1'; end if;
+ end if;
+ else
+ if (reg(13)(1) = '1') then -- alt
+ if is_top then env_hold <= '1'; end if;
+ else
+ if is_top_m1 then env_hold <= '1'; end if;
+ end if;
+ end if;
+
+ elsif (reg(13)(1) = '1') then -- alternate
+ if (env_inc = '0') then -- down
+ if is_bot_p1 then env_hold <= '1'; end if;
+ if is_bot then env_hold <= '0'; env_inc <= '1'; end if;
+ else
+ if is_top_m1 then env_hold <= '1'; end if;
+ if is_top then env_hold <= '0'; env_inc <= '0'; end if;
+ end if;
+ end if;
+
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ p_chan_mixer : process(cnt_div, reg, tone_gen_op)
+ begin
+ tone_ena_l <= '1'; tone_src <= '1';
+ noise_ena_l <= '1'; chan_vol <= "00000";
+ case cnt_div(1 downto 0) is
+ when "00" =>
+ tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0);
+ noise_ena_l <= reg(7)(3);
+ when "01" =>
+ tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0);
+ noise_ena_l <= reg(7)(4);
+ when "10" =>
+ tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0);
+ noise_ena_l <= reg(7)(5);
+ when "11" => null; -- tone gen outputs become valid on this clock
+ when others => null;
+ end case;
+ end process;
+
+ p_op_mixer : process
+ variable chan_mixed : std_logic;
+ variable chan_amp : std_logic_vector(4 downto 0);
+ begin
+ wait until rising_edge(CLK);
+ if (ENA = '1') then
+
+ chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op);
+
+ chan_amp := (others => '0');
+ if (chan_mixed = '1') then
+ if (chan_vol(4) = '0') then
+ if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet
+ chan_amp := "00000";
+ else
+ chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone)
+ end if;
+ else
+ chan_amp := env_vol(4 downto 0);
+ end if;
+ end if;
+
+ dac_amp <= x"00";
+ case chan_amp is
+ when "11111" => dac_amp <= x"FF";
+ when "11110" => dac_amp <= x"D9";
+ when "11101" => dac_amp <= x"BA";
+ when "11100" => dac_amp <= x"9F";
+ when "11011" => dac_amp <= x"88";
+ when "11010" => dac_amp <= x"74";
+ when "11001" => dac_amp <= x"63";
+ when "11000" => dac_amp <= x"54";
+ when "10111" => dac_amp <= x"48";
+ when "10110" => dac_amp <= x"3D";
+ when "10101" => dac_amp <= x"34";
+ when "10100" => dac_amp <= x"2C";
+ when "10011" => dac_amp <= x"25";
+ when "10010" => dac_amp <= x"1F";
+ when "10001" => dac_amp <= x"1A";
+ when "10000" => dac_amp <= x"16";
+ when "01111" => dac_amp <= x"13";
+ when "01110" => dac_amp <= x"10";
+ when "01101" => dac_amp <= x"0D";
+ when "01100" => dac_amp <= x"0B";
+ when "01011" => dac_amp <= x"09";
+ when "01010" => dac_amp <= x"08";
+ when "01001" => dac_amp <= x"07";
+ when "01000" => dac_amp <= x"06";
+ when "00111" => dac_amp <= x"05";
+ when "00110" => dac_amp <= x"04";
+ when "00101" => dac_amp <= x"03";
+ when "00100" => dac_amp <= x"03";
+ when "00011" => dac_amp <= x"02";
+ when "00010" => dac_amp <= x"02";
+ when "00001" => dac_amp <= x"01";
+ when "00000" => dac_amp <= x"00";
+ when others => null;
+ end case;
+
+ cnt_div_t1 <= cnt_div;
+ end if;
+ end process;
+
+ p_audio_output : process(RESET_L, CLK)
+ begin
+ if (RESET_L = '0') then
+ O_AUDIO <= (others => '0');
+ O_CHAN <= (others => '0');
+ elsif rising_edge(CLK) then
+
+ if (ENA = '1') then
+ O_AUDIO <= dac_amp(7 downto 0);
+ O_CHAN <= cnt_div_t1(1 downto 0);
+ end if;
+ end if;
+ end process;
+
+ p_io_ports : process(reg)
+ begin
+ O_IOA <= reg(14);
+ O_IOA_OE_L <= not reg(7)(6);
+ O_IOB <= reg(15);
+ O_IOB_OE_L <= not reg(7)(7);
+ end process;
+
+ p_io_ports_inreg : process
+ begin
+ wait until rising_edge(CLK);
+ if (ENA = '1') then -- resync
+ ioa_inreg <= I_IOA;
+ iob_inreg <= I_IOB;
+ end if;
+ end process;
+end architecture RTL;
diff --git a/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/build_id.tcl b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/build_id.tcl
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+ # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+ set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+ set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+ # Create a Verilog file for output
+ set outputFileName "rtl/build_id.v"
+ set outputFile [open $outputFileName "w"]
+
+ # Output the Verilog source
+ puts $outputFile "`define BUILD_DATE \"$buildDate\""
+ puts $outputFile "`define BUILD_TIME \"$buildTime\""
+ close $outputFile
+
+ # Send confirmation message to the Messages window
+ post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+ post_message "Date: $buildDate"
+ post_message "Time: $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/col.vhd b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/col.vhd
new file mode 100644
index 00000000..51a9a094
--- /dev/null
+++ b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/col.vhd
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity col is
+port (
+ clk : in std_logic;
+ addr : in std_logic_vector(4 downto 0);
+ data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of col is
+ type rom is array(0 to 31) of std_logic_vector(7 downto 0);
+ signal rom_data: rom := (
+ X"00",X"AF",X"83",X"D2",X"1A",X"0F",X"8F",X"DB",X"24",X"32",X"3F",X"2C",X"00",X"57",X"AA",X"FF",
+ X"00",X"C6",X"00",X"B4",X"24",X"26",X"7B",X"0F",X"5F",X"8F",X"1B",X"2F",X"3E",X"A8",X"AB",X"FF");
+begin
+process(clk)
+begin
+ if rising_edge(clk) then
+ data <= rom_data(to_integer(unsigned(addr)));
+ end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/dpram.vhd b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/dpram.vhd
new file mode 100644
index 00000000..284194c5
--- /dev/null
+++ b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/dpram.vhd
@@ -0,0 +1,81 @@
+-- -----------------------------------------------------------------------
+--
+-- Syntiac's generic VHDL support files.
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+--
+-- Modified April 2016 by Dar (darfpga@aol.fr)
+-- http://darfpga.blogspot.fr
+-- Remove address register when writing
+--
+-- -----------------------------------------------------------------------
+--
+-- dpram.vhd
+--
+-- -----------------------------------------------------------------------
+--
+-- generic ram.
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+entity dpram is
+ generic (
+ dWidth : integer := 8;
+ aWidth : integer := 10
+ );
+ port (
+ clk_a : in std_logic;
+ we_a : in std_logic := '0';
+ addr_a : in std_logic_vector((aWidth-1) downto 0);
+ d_a : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
+ q_a : out std_logic_vector((dWidth-1) downto 0);
+
+ clk_b : in std_logic;
+ we_b : in std_logic := '0';
+ addr_b : in std_logic_vector((aWidth-1) downto 0);
+ d_b : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
+ q_b : out std_logic_vector((dWidth-1) downto 0)
+ );
+end entity;
+
+-- -----------------------------------------------------------------------
+
+architecture rtl of dpram is
+ subtype addressRange is integer range 0 to ((2**aWidth)-1);
+ type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
+ signal ram: ramDef;
+ signal addr_a_reg: std_logic_vector((aWidth-1) downto 0);
+ signal addr_b_reg: std_logic_vector((aWidth-1) downto 0);
+begin
+
+-- -----------------------------------------------------------------------
+ process(clk_a)
+ begin
+ if rising_edge(clk_a) then
+ if we_a = '1' then
+ ram(to_integer(unsigned(addr_a))) <= d_a;
+ end if;
+ q_a <= ram(to_integer(unsigned(addr_a)));
+ end if;
+ end process;
+
+ process(clk_b)
+ begin
+ if rising_edge(clk_b) then
+ if we_b = '1' then
+ ram(to_integer(unsigned(addr_b))) <= d_b;
+ end if;
+ q_b <= ram(to_integer(unsigned(addr_b)));
+ end if;
+ end process;
+
+end architecture;
+
diff --git a/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/mems.v b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/mems.v
new file mode 100644
index 00000000..a0cba17b
--- /dev/null
+++ b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/mems.v
@@ -0,0 +1,137 @@
+// Copyright (c) 2012,20 MiSTer-X
+
+module DLROM #(parameter AW,parameter DW)
+(
+ input CL0,
+ input [(AW-1):0] AD0,
+ output reg [(DW-1):0] DO0,
+
+ input CL1,
+ input [(AW-1):0] AD1,
+ input [(DW-1):0] DI1,
+ input WE1
+);
+
+reg [(DW-1):0] core[0:((2**AW)-1)];
+
+always @(posedge CL0) DO0 <= core[AD0];
+always @(posedge CL1) if (WE1) core[AD1] <= DI1;
+
+endmodule
+
+
+module VDPRAM400x2
+(
+ input CL0,
+ input [10:0] AD0,
+ input WR0,
+ input [7:0] WD0,
+ output [7:0] RD0,
+
+ input CL1,
+ input [9:0] AD1,
+ output [15:0] RD1
+);
+
+reg A10;
+always @( posedge CL0 ) A10 <= AD0[10];
+
+wire [7:0] RD00, RD01;
+DPRAM400 LS( CL0, AD0[9:0], WR0 & (~AD0[10]), WD0, RD00, CL1, AD1, 1'b0, 8'h0, RD1[ 7:0] );
+DPRAM400 HS( CL0, AD0[9:0], WR0 & ( AD0[10]), WD0, RD01, CL1, AD1, 1'b0, 8'h0, RD1[15:8] );
+
+assign RD0 = A10 ? RD01 : RD00;
+
+endmodule
+
+
+module DPRAM800
+(
+ input CL0,
+ input [10:0] AD0,
+ input WE0,
+ input [7:0] WD0,
+ output reg [7:0] RD0,
+
+ input CL1,
+ input [10:0] AD1,
+ input WE1,
+ input [7:0] WD1,
+ output reg [7:0] RD1
+);
+
+reg [7:0] core[0:2047];
+
+always @( posedge CL0 ) begin
+ if (WE0) core[AD0] <= WD0;
+ RD0 <= core[AD0];
+end
+
+always @( posedge CL1 ) begin
+ if (WE1) core[AD1] <= WD1;
+ RD1 <= core[AD1];
+end
+
+endmodule
+
+
+module DPRAM400
+(
+ input CL0,
+ input [9:0] AD0,
+ input WE0,
+ input [7:0] WD0,
+ output reg [7:0] RD0,
+
+ input CL1,
+ input [9:0] AD1,
+ input WE1,
+ input [7:0] WD1,
+ output reg [7:0] RD1
+);
+
+reg [7:0] core[0:1023];
+
+always @( posedge CL0 ) begin
+ if (WE0) core[AD0] <= WD0;
+ RD0 <= core[AD0];
+end
+
+always @( posedge CL1 ) begin
+ if (WE1) core[AD1] <= WD1;
+ RD1 <= core[AD1];
+end
+
+endmodule
+
+/*
+module DPRAM200
+(
+ input CL0,
+ input [8:0] AD0,
+ input WE0,
+ input [7:0] WD0,
+ output reg [7:0] RD0,
+
+ input CL1,
+ input [8:0] AD1,
+ input WE1,
+ input [7:0] WD1,
+ output reg [7:0] RD1
+);
+
+reg [7:0] core[0:511];
+
+always @( posedge CL0 ) begin
+ if (WE0) core[AD0] <= WD0;
+ RD0 <= core[AD0];
+end
+
+always @( posedge CL1 ) begin
+ if (WE1) core[AD1] <= WD1;
+ RD1 <= core[AD1];
+end
+
+endmodule
+*/
+
diff --git a/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/pll.v b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/pll.v
new file mode 100644
index 00000000..99e38b86
--- /dev/null
+++ b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/pll.v
@@ -0,0 +1,337 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: pll.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.4 Build 182 03/12/2014 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2014 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll (
+ inclk0,
+ c0,
+ c1,
+ locked);
+
+ input inclk0;
+ output c0;
+ output c1;
+ output locked;
+
+ wire [4:0] sub_wire0;
+ wire sub_wire2;
+ wire [0:0] sub_wire6 = 1'h0;
+ wire [0:0] sub_wire3 = sub_wire0[0:0];
+ wire [1:1] sub_wire1 = sub_wire0[1:1];
+ wire c1 = sub_wire1;
+ wire locked = sub_wire2;
+ wire c0 = sub_wire3;
+ wire sub_wire4 = inclk0;
+ wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
+
+ altpll altpll_component (
+ .inclk (sub_wire5),
+ .clk (sub_wire0),
+ .locked (sub_wire2),
+ .activeclock (),
+ .areset (1'b0),
+ .clkbad (),
+ .clkena ({6{1'b1}}),
+ .clkloss (),
+ .clkswitch (1'b0),
+ .configupdate (1'b0),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena ({4{1'b1}}),
+ .fbin (1'b1),
+ .fbmimicbidir (),
+ .fbout (),
+ .fref (),
+ .icdrclk (),
+ .pfdena (1'b1),
+ .phasecounterselect ({4{1'b1}}),
+ .phasedone (),
+ .phasestep (1'b1),
+ .phaseupdown (1'b1),
+ .pllena (1'b1),
+ .scanaclr (1'b0),
+ .scanclk (1'b0),
+ .scanclkena (1'b1),
+ .scandata (1'b0),
+ .scandataout (),
+ .scandone (),
+ .scanread (1'b0),
+ .scanwrite (1'b0),
+ .sclkout0 (),
+ .sclkout1 (),
+ .vcooverrange (),
+ .vcounderrange ());
+ defparam
+ altpll_component.bandwidth_type = "AUTO",
+ altpll_component.clk0_divide_by = 9,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 16,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.clk1_divide_by = 3,
+ altpll_component.clk1_duty_cycle = 50,
+ altpll_component.clk1_multiply_by = 8,
+ altpll_component.clk1_phase_shift = "0",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.inclk0_input_frequency = 37037,
+ altpll_component.intended_device_family = "Cyclone III",
+ altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.pll_type = "AUTO",
+ altpll_component.port_activeclock = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_UNUSED",
+ altpll_component.port_clkbad0 = "PORT_UNUSED",
+ altpll_component.port_clkbad1 = "PORT_UNUSED",
+ altpll_component.port_clkloss = "PORT_UNUSED",
+ altpll_component.port_clkswitch = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_fbin = "PORT_UNUSED",
+ altpll_component.port_inclk0 = "PORT_USED",
+ altpll_component.port_inclk1 = "PORT_UNUSED",
+ altpll_component.port_locked = "PORT_USED",
+ altpll_component.port_pfdena = "PORT_UNUSED",
+ altpll_component.port_phasecounterselect = "PORT_UNUSED",
+ altpll_component.port_phasedone = "PORT_UNUSED",
+ altpll_component.port_phasestep = "PORT_UNUSED",
+ altpll_component.port_phaseupdown = "PORT_UNUSED",
+ altpll_component.port_pllena = "PORT_UNUSED",
+ altpll_component.port_scanaclr = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_UNUSED",
+ altpll_component.port_scanclkena = "PORT_UNUSED",
+ altpll_component.port_scandata = "PORT_UNUSED",
+ altpll_component.port_scandataout = "PORT_UNUSED",
+ altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanread = "PORT_UNUSED",
+ altpll_component.port_scanwrite = "PORT_UNUSED",
+ altpll_component.port_clk0 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_USED",
+ altpll_component.port_clk2 = "PORT_UNUSED",
+ altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk4 = "PORT_UNUSED",
+ altpll_component.port_clk5 = "PORT_UNUSED",
+ altpll_component.port_clkena0 = "PORT_UNUSED",
+ altpll_component.port_clkena1 = "PORT_UNUSED",
+ altpll_component.port_clkena2 = "PORT_UNUSED",
+ altpll_component.port_clkena3 = "PORT_UNUSED",
+ altpll_component.port_clkena4 = "PORT_UNUSED",
+ altpll_component.port_clkena5 = "PORT_UNUSED",
+ altpll_component.port_extclk0 = "PORT_UNUSED",
+ altpll_component.port_extclk1 = "PORT_UNUSED",
+ altpll_component.port_extclk2 = "PORT_UNUSED",
+ altpll_component.port_extclk3 = "PORT_UNUSED",
+ altpll_component.self_reset_on_loss_lock = "OFF",
+ altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "72.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "16"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "8"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "72.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/sdram.sv b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/sdram.sv
new file mode 100644
index 00000000..41f5b7a8
--- /dev/null
+++ b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/sdram.sv
@@ -0,0 +1,348 @@
+//
+// sdram.v
+//
+// sdram controller implementation for the MiST board
+// https://github.com/mist-devel/mist-board
+//
+// Copyright (c) 2013 Till Harbaum
+// Copyright (c) 2019 Gyorgy Szombathelyi
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see .
+//
+
+module sdram (
+
+ // interface to the MT48LC16M16 chip
+ inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
+ output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
+ output reg SDRAM_DQML, // two byte masks
+ output reg SDRAM_DQMH, // two byte masks
+ output reg [1:0] SDRAM_BA, // two banks
+ output SDRAM_nCS, // a single chip select
+ output SDRAM_nWE, // write enable
+ output SDRAM_nRAS, // row address select
+ output SDRAM_nCAS, // columns address select
+
+ // cpu/chipset interface
+ input init_n, // init signal after FPGA config to initialize RAM
+ input clk, // sdram clock
+
+ input port1_req,
+ output reg port1_ack,
+ input port1_we,
+ input [23:1] port1_a,
+ input [1:0] port1_ds,
+ input [15:0] port1_d,
+ output reg [15:0] port1_q,
+
+ input [16:1] cpu1_addr,
+ output reg [15:0] cpu1_q,
+ input [16:1] cpu2_addr,
+ output reg [15:0] cpu2_q,
+
+ input port2_req,
+ output reg port2_ack,
+ input port2_we,
+ input [23:1] port2_a,
+ input [1:0] port2_ds,
+ input [15:0] port2_d,
+ output reg [31:0] port2_q,
+
+ input [16:2] sp_addr,
+ output reg [31:0] sp_q
+);
+
+localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
+localparam BURST_LENGTH = 3'b001; // 000=1, 001=2, 010=4, 011=8
+localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
+localparam CAS_LATENCY = 3'd2; // 2/3 allowed
+localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
+localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
+
+localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
+
+// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz
+localparam RFRSH_CYCLES = 10'd842;
+
+// ---------------------------------------------------------------------
+// ------------------------ cycle state machine ------------------------
+// ---------------------------------------------------------------------
+
+/*
+ SDRAM state machine for 2 bank interleaved access
+ 1 word burst, CL2
+cmd issued registered
+ 0 RAS0 cas1 - data0 read burst terminated
+ 1 ras0
+ 2 data1 returned
+ 3 CAS0 data1 returned
+ 4 RAS1 cas0
+ 5 ras1
+ 6 CAS1 data0 returned
+*/
+
+localparam STATE_RAS0 = 3'd0; // first state in cycle
+localparam STATE_RAS1 = 3'd4; // Second ACTIVE command after RAS0 + tRRD (15ns)
+localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3
+localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6
+localparam STATE_READ0 = 3'd0;// STATE_CAS0 + CAS_LATENCY + 2'd2; // 7
+localparam STATE_READ1 = 3'd3;
+localparam STATE_DS1b = 3'd0;
+localparam STATE_READ1b = 3'd4;
+localparam STATE_LAST = 3'd6;
+
+reg [2:0] t;
+
+always @(posedge clk) begin
+ t <= t + 1'd1;
+ if (t == STATE_LAST) t <= STATE_RAS0;
+end
+
+// ---------------------------------------------------------------------
+// --------------------------- startup/reset ---------------------------
+// ---------------------------------------------------------------------
+
+// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
+// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
+reg [4:0] reset;
+reg init = 1'b1;
+always @(posedge clk, negedge init_n) begin
+ if(!init_n) begin
+ reset <= 5'h1f;
+ init <= 1'b1;
+ end else begin
+ if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
+ init <= !(reset == 0);
+ end
+end
+
+// ---------------------------------------------------------------------
+// ------------------ generate ram control signals ---------------------
+// ---------------------------------------------------------------------
+
+// all possible commands
+localparam CMD_INHIBIT = 4'b1111;
+localparam CMD_NOP = 4'b0111;
+localparam CMD_ACTIVE = 4'b0011;
+localparam CMD_READ = 4'b0101;
+localparam CMD_WRITE = 4'b0100;
+localparam CMD_BURST_TERMINATE = 4'b0110;
+localparam CMD_PRECHARGE = 4'b0010;
+localparam CMD_AUTO_REFRESH = 4'b0001;
+localparam CMD_LOAD_MODE = 4'b0000;
+
+reg [3:0] sd_cmd; // current command sent to sd ram
+reg [15:0] sd_din;
+// drive control signals according to current command
+assign SDRAM_nCS = sd_cmd[3];
+assign SDRAM_nRAS = sd_cmd[2];
+assign SDRAM_nCAS = sd_cmd[1];
+assign SDRAM_nWE = sd_cmd[0];
+
+reg [24:1] addr_latch[2];
+reg [24:1] addr_latch_next[2];
+reg [16:1] addr_last[2];
+reg [16:2] addr_last2[2];
+reg [15:0] din_latch[2];
+reg [1:0] oe_latch;
+reg [1:0] we_latch;
+reg [1:0] ds[2];
+
+reg port1_state;
+reg port2_state;
+
+localparam PORT_NONE = 2'd0;
+localparam PORT_CPU1 = 2'd1;
+localparam PORT_CPU2 = 2'd2;
+localparam PORT_SP = 2'd1;
+localparam PORT_REQ = 2'd3;
+
+reg [1:0] next_port[2];
+reg [1:0] port[2];
+
+reg refresh;
+reg [10:0] refresh_cnt;
+wire need_refresh = (refresh_cnt >= RFRSH_CYCLES);
+
+// PORT1: bank 0,1
+always @(*) begin
+ if (refresh) begin
+ next_port[0] = PORT_NONE;
+ addr_latch_next[0] = addr_latch[0];
+ end else if (port1_req ^ port1_state) begin
+ next_port[0] = PORT_REQ;
+ addr_latch_next[0] = { 1'b0, port1_a };
+ end else if (cpu1_addr != addr_last[PORT_CPU1]) begin
+ next_port[0] = PORT_CPU1;
+ addr_latch_next[0] = { 8'd0, cpu1_addr };
+ end else if (cpu2_addr != addr_last[PORT_CPU2]) begin
+ next_port[0] = PORT_CPU2;
+ addr_latch_next[0] = { 8'd0, cpu2_addr };
+ end else begin
+ next_port[0] = PORT_NONE;
+ addr_latch_next[0] = addr_latch[0];
+ end
+end
+
+// PORT1: bank 2,3
+always @(*) begin
+ if (port2_req ^ port2_state) begin
+ next_port[1] = PORT_REQ;
+ addr_latch_next[1] = { 1'b1, port2_a };
+ end else if (sp_addr != addr_last2[PORT_SP]) begin
+ next_port[1] = PORT_SP;
+ addr_latch_next[1] = { 1'b1, 7'd0, sp_addr, 1'b0 };
+ end else begin
+ next_port[1] = PORT_NONE;
+ addr_latch_next[1] = addr_latch[1];
+ end
+end
+
+always @(posedge clk) begin
+
+ // permanently latch ram data to reduce delays
+ sd_din <= SDRAM_DQ;
+ SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
+ { SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
+ sd_cmd <= CMD_NOP; // default: idle
+ refresh_cnt <= refresh_cnt + 1'd1;
+
+ if(init) begin
+ // initialization takes place at the end of the reset phase
+ if(t == STATE_RAS0) begin
+
+ if(reset == 15) begin
+ sd_cmd <= CMD_PRECHARGE;
+ SDRAM_A[10] <= 1'b1; // precharge all banks
+ end
+
+ if(reset == 10 || reset == 8) begin
+ sd_cmd <= CMD_AUTO_REFRESH;
+ end
+
+ if(reset == 2) begin
+ sd_cmd <= CMD_LOAD_MODE;
+ SDRAM_A <= MODE;
+ SDRAM_BA <= 2'b00;
+ end
+ end
+ end else begin
+ // RAS phase
+ // bank 0,1
+ if(t == STATE_RAS0) begin
+ addr_latch[0] <= addr_latch_next[0];
+ port[0] <= next_port[0];
+ { oe_latch[0], we_latch[0] } <= 2'b00;
+
+ if (next_port[0] != PORT_NONE) begin
+ sd_cmd <= CMD_ACTIVE;
+ SDRAM_A <= addr_latch_next[0][22:10];
+ SDRAM_BA <= addr_latch_next[0][24:23];
+ addr_last[next_port[0]] <= addr_latch_next[0][16:1];
+ if (next_port[0] == PORT_REQ) begin
+ { oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
+ ds[0] <= port1_ds;
+ din_latch[0] <= port1_d;
+ port1_state <= port1_req;
+ end else begin
+ { oe_latch[0], we_latch[0] } <= 2'b10;
+ ds[0] <= 2'b11;
+ end
+ end
+ end
+
+ // bank 2,3
+ if(t == STATE_RAS1) begin
+ refresh <= 1'b0;
+ addr_latch[1] <= addr_latch_next[1];
+ { oe_latch[1], we_latch[1] } <= 2'b00;
+ port[1] <= next_port[1];
+
+ if (next_port[1] != PORT_NONE) begin
+ sd_cmd <= CMD_ACTIVE;
+ SDRAM_A <= addr_latch_next[1][22:10];
+ SDRAM_BA <= addr_latch_next[1][24:23];
+ addr_last2[next_port[1]] <= addr_latch_next[1][16:2];
+ if (next_port[1] == PORT_REQ) begin
+ { oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we };
+ ds[1] <= port2_ds;
+ din_latch[1] <= port2_d;
+ port2_state <= port2_req;
+ end else begin
+ { oe_latch[1], we_latch[1] } <= 2'b10;
+ ds[1] <= 2'b11;
+ end
+ end
+
+ if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
+ refresh <= 1'b1;
+ refresh_cnt <= 0;
+ sd_cmd <= CMD_AUTO_REFRESH;
+ end
+ end
+
+ // CAS phase
+ if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
+ sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
+ { SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
+ if (we_latch[0]) begin
+ SDRAM_DQ <= din_latch[0];
+ port1_ack <= port1_req;
+ end
+ SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge
+ SDRAM_BA <= addr_latch[0][24:23];
+ end
+
+ if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
+ sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
+ { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
+ if (we_latch[1]) begin
+ SDRAM_DQ <= din_latch[1];
+ port2_ack <= port2_req;
+ end
+ SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge
+ SDRAM_BA <= addr_latch[1][24:23];
+ end
+
+ // Data returned
+ if(t == STATE_READ0 && oe_latch[0]) begin
+ case(port[0])
+ PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
+ PORT_CPU1: begin cpu1_q <= sd_din; end
+ PORT_CPU2: begin cpu2_q <= sd_din; end
+ default: ;
+ endcase;
+ end
+
+ if(t == STATE_READ1 && oe_latch[1]) begin
+ case(port[1])
+ PORT_REQ: port2_q[15:0] <= sd_din;
+ PORT_SP : sp_q[15:0] <= sd_din;
+ default: ;
+ endcase;
+ end
+
+ if(t == STATE_DS1b && oe_latch[1]) { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
+
+ if(t == STATE_READ1b && oe_latch[1]) begin
+ case(port[1])
+ PORT_REQ: begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end
+ PORT_SP : begin sp_q[31:16] <= sd_din; end
+ default: ;
+ endcase;
+ end
+ end
+end
+
+endmodule
diff --git a/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/z80ip.v b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/z80ip.v
new file mode 100644
index 00000000..3d9eff03
--- /dev/null
+++ b/Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/z80ip.v
@@ -0,0 +1,48 @@
+// Copyright (c) 2012 MiSTer-X
+
+module Z80IP
+(
+ input reset_in,
+ input clk,
+ output [15:0] adr,
+ input [7:0] data_in,
+ output [7:0] data_out,
+ output rd,
+ output wr,
+ input intreq
+);
+
+wire nmireq = 0;
+
+wire i_mreq, i_iorq, i_rd, i_wr, i_rfsh;
+
+T80s cpu(
+ .CLK(clk),
+ .RESET_n(~reset_in),
+ .INT_n(~intreq),
+ .NMI_n(~nmireq),
+ .MREQ_n(i_mreq),
+ .IORQ_n(i_iorq),
+ .RFSH_n(i_rfsh),
+ .RD_n(i_rd),
+ .WR_n(i_wr),
+ .A(adr),
+ .DI(data_in),
+ .DO(data_out),
+ .WAIT_n(1'b1),
+ .BUSRQ_n(1'b1),
+ .BUSAK_n(),
+ .HALT_n(),
+ .M1_n()
+);
+
+wire mreq = (~i_mreq) & (i_rfsh);
+wire iorq = ~i_iorq;
+wire rdr = ~i_rd;
+wire wrr = ~i_wr;
+
+assign rd = mreq & rdr;
+assign wr = mreq & wrr;
+
+endmodule
+