From fa65ff3c9f5ed9ea59167b2f8f55a67e94c936c0 Mon Sep 17 00:00:00 2001 From: Marcel Date: Mon, 22 Jul 2019 20:50:03 +0200 Subject: [PATCH] remove one DAC --- .../OricInFPGA_MiST/rtl/OricAtmos_MiST.sv | 28 +++------ Computer_MiST/OricInFPGA_MiST/rtl/ay8912.vhd | 41 +++++++------ .../OricInFPGA_MiST/rtl/oricatmos.vhd | 13 ++-- Computer_MiST/OricInFPGA_MiST/rtl/pll.v | 60 +++++-------------- 4 files changed, 56 insertions(+), 86 deletions(-) diff --git a/Computer_MiST/OricInFPGA_MiST/rtl/OricAtmos_MiST.sv b/Computer_MiST/OricInFPGA_MiST/rtl/OricAtmos_MiST.sv index b388328f..a568ea11 100644 --- a/Computer_MiST/OricInFPGA_MiST/rtl/OricAtmos_MiST.sv +++ b/Computer_MiST/OricInFPGA_MiST/rtl/OricAtmos_MiST.sv @@ -25,22 +25,22 @@ localparam CONF_STR = { "T9,Reset;", "V,v1.00.",`BUILD_DATE }; -wire clk_24, clk_12, clk_6; +wire clk_24, clk_6; wire [10:0] ps2_key; -wire r, g,b; +wire r, g, b; wire hs, vs; wire [1:0] buttons, switches; wire ypbpr; wire scandoublerD; wire [31:0] status; -wire [15:0] audiol, audior; +wire [15:0] audio; assign LED = 1'b1; +assign AUDIO_R = AUDIO_L; pll pll ( .inclk0 ( CLOCK_27 ), .c0 ( clk_24 ), - .c1 ( clk_12 ), - .c2 ( clk_6 ) + .c1 ( clk_6 ) ); @@ -90,8 +90,7 @@ video_mixer video_mixer ( oricatmos oricatmos( .RESET(status[0] | status[9] | buttons[1]), .ps2_key(ps2_key), - .PSG_LEFT(audiol), - .PSG_RIGHT(audior), + .PSG_OUT(audio), .VIDEO_R(r), .VIDEO_G(g), .VIDEO_B(b), @@ -104,22 +103,11 @@ oricatmos oricatmos( dac #( .msbi_g(15)) -dacl ( +dac( .clk_i(clk_24), .res_n_i(1'b1), - .dac_i(audiol), + .dac_i(audio), .dac_o(AUDIO_L) ); -dac #( - .msbi_g(15)) -dacr ( - .clk_i(clk_24), - .res_n_i(1'b1), - .dac_i(audior), - .dac_o(AUDIO_R) - ); - - - endmodule diff --git a/Computer_MiST/OricInFPGA_MiST/rtl/ay8912.vhd b/Computer_MiST/OricInFPGA_MiST/rtl/ay8912.vhd index 8b7f7c60..9cd0a82e 100644 --- a/Computer_MiST/OricInFPGA_MiST/rtl/ay8912.vhd +++ b/Computer_MiST/OricInFPGA_MiST/rtl/ay8912.vhd @@ -27,18 +27,20 @@ use ieee.std_logic_unsigned.all; entity ay8912 is port ( - cpuclk : in STD_LOGIC; --48MHz - reset : in STD_LOGIC; - cs : in STD_LOGIC; --H-aktiv - bc0 : in STD_LOGIC; -- - bdir : in STD_LOGIC; - Data_in : in STD_LOGIC_VECTOR (7 downto 0); - oData : out STD_LOGIC_VECTOR (7 downto 0); - chanA : buffer STD_LOGIC_VECTOR (10 downto 0); - chanB : buffer STD_LOGIC_VECTOR (10 downto 0); - chanC : buffer STD_LOGIC_VECTOR (10 downto 0); + cpuclk : in STD_LOGIC; --48MHz + reset : in STD_LOGIC; + cs : in STD_LOGIC; --H-aktiv + bc0 : in STD_LOGIC; -- + bdir : in STD_LOGIC; + Data_in : in STD_LOGIC_VECTOR (7 downto 0); + Data_out : out STD_LOGIC_VECTOR (7 downto 0); + IO_A : in STD_LOGIC_VECTOR (7 downto 0); + chanA : buffer STD_LOGIC_VECTOR (10 downto 0); + chanB : buffer STD_LOGIC_VECTOR (10 downto 0); + chanC : buffer STD_LOGIC_VECTOR (10 downto 0); Arechts : out STD_LOGIC_VECTOR (15 downto 0); - Alinks : out STD_LOGIC_VECTOR (15 downto 0) + Alinks : out STD_LOGIC_VECTOR (15 downto 0); + Amono : out STD_LOGIC_VECTOR (15 downto 0) ); end ay8912; @@ -92,7 +94,7 @@ begin process (cpuclk, clockgen) begin S_Tick <= '0'; --sound - H_Tick <= '0'; --Huellkurve + H_Tick <= '0'; --Hüllkurve IF clockgen(9 downto 1)=0 THEN S_Tick <= '1'; IF clockgen(0)='0' THEN @@ -102,6 +104,7 @@ begin IF rising_edge(cpuclk) THEN Arechts <= (chanA&"00000")+('0'&chanB&"0000"); Alinks <= (chanC&"00000")+('0'&chanB&"0000"); + Amono <= (chanC&"00000")+('0'&chanB&"0000")+(chanA&"00000"); IF H_Tick='1' THEN -- clockgen <= ((48*16)-1); --48MHz clockgen <= "1011111111"; --48MHz @@ -113,7 +116,7 @@ END process; ------------------------------------------------------------------------- --IO Regs ------------------------------------------------------------------------- -process (cpuclk, reset, PortA, PortB, Aperiode, Bperiode, Cperiode, Hperiode, AVol, BVol, CVol, Noise, HKurve, enable, Data_in, t_Data, PSGReg, bdir, bc0) +process (cpuclk, reset, IO_A, PortA, PortB, Aperiode, Bperiode, Cperiode, Hperiode, AVol, BVol, CVol, Noise, HKurve, enable, Data_in, t_Data, PSGReg, bdir, bc0) begin IF reset='0' THEN enable <= (others => '0'); @@ -171,7 +174,7 @@ begin END IF; CASE Data_in(3 downto 0) IS WHEN "1111" => n_Pegel <= X"2AA"; -- Umsetzung in logarithmische Werte in ca. 3dB Schritten - WHEN "1110" => n_Pegel <= X"1E2"; -- f�r Kan�le + WHEN "1110" => n_Pegel <= X"1E2"; -- für Kanäle WHEN "1101" => n_Pegel <= X"155"; WHEN "1100" => n_Pegel <= X"0F1"; WHEN "1011" => n_Pegel <= X"0AA"; @@ -191,9 +194,9 @@ begin -- read reg IF bc0='1' AND bdir='0' THEN - oData <= t_Data; + Data_out <= t_Data; ELSE - oData <= "11111111"; + Data_out <= "11111111"; END IF; t_Data <= "00000000"; @@ -227,7 +230,11 @@ begin WHEN "1101" => t_Data(3 downto 0) <= HKurve; WHEN "1110" => + IF enable(6)='0' THEN + t_Data <= PortA AND IO_A; + ELSE t_Data <= PortA; + END IF; WHEN "1111" => t_Data <= PortB; END CASE; @@ -351,7 +358,7 @@ begin CASE nHVol(3 downto 0) IS WHEN "1111" => HVollog <= X"2AA"; -- Umsetzung in logarithmische Werte in ca. 3dB Schritten - WHEN "1110" => HVollog <= X"1E2"; -- f�r H�llkurve + WHEN "1110" => HVollog <= X"1E2"; -- für Hüllkurve WHEN "1101" => HVollog <= X"155"; WHEN "1100" => HVollog <= X"0F1"; WHEN "1011" => HVollog <= X"0AA"; diff --git a/Computer_MiST/OricInFPGA_MiST/rtl/oricatmos.vhd b/Computer_MiST/OricInFPGA_MiST/rtl/oricatmos.vhd index 5f47d7f4..d939ed0c 100644 --- a/Computer_MiST/OricInFPGA_MiST/rtl/oricatmos.vhd +++ b/Computer_MiST/OricInFPGA_MiST/rtl/oricatmos.vhd @@ -67,8 +67,9 @@ entity oricatmos is K7_TAPEIN : in std_logic; K7_TAPEOUT : out std_logic; K7_REMOTE : out std_logic; - PSG_RIGHT : out std_logic_vector(15 downto 0); - PSG_LEFT : out std_logic_vector(15 downto 0); +-- PSG_RIGHT : out std_logic_vector(15 downto 0); +-- PSG_LEFT : out std_logic_vector(15 downto 0); + PSG_OUT : out std_logic_vector(15 downto 0); VIDEO_R : out std_logic; VIDEO_G : out std_logic; VIDEO_B : out std_logic; @@ -297,12 +298,14 @@ ad <= ula_AD_SRAM when ula_PHI2 = '0' else cpu_ad(15 downto 0); bc0 => psg_bdir, bdir => via_cb2_out, Data_in => via_pa_out, - oData => via_pa_in, + Data_out => via_pa_in, + IO_A => x"FF", chanA => open, chanB => open, chanC => open, - Arechts => PSG_RIGHT, - Alinks => PSG_LEFT +-- Arechts => PSG_RIGHT, +-- Alinks => PSG_LEFT, + Amono => PSG_OUT ); inst_key : keyboard diff --git a/Computer_MiST/OricInFPGA_MiST/rtl/pll.v b/Computer_MiST/OricInFPGA_MiST/rtl/pll.v index 7c58b095..e6d2715a 100644 --- a/Computer_MiST/OricInFPGA_MiST/rtl/pll.v +++ b/Computer_MiST/OricInFPGA_MiST/rtl/pll.v @@ -39,27 +39,23 @@ module pll ( inclk0, c0, - c1, - c2); + c1); input inclk0; output c0; output c1; - output c2; wire [4:0] sub_wire0; - wire [0:0] sub_wire6 = 1'h0; - wire [2:2] sub_wire3 = sub_wire0[2:2]; - wire [0:0] sub_wire2 = sub_wire0[0:0]; - wire [1:1] sub_wire1 = sub_wire0[1:1]; - wire c1 = sub_wire1; - wire c0 = sub_wire2; - wire c2 = sub_wire3; - wire sub_wire4 = inclk0; - wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; + wire [0:0] sub_wire5 = 1'h0; + wire [1:1] sub_wire2 = sub_wire0[1:1]; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire c1 = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; altpll altpll_component ( - .inclk (sub_wire5), + .inclk (sub_wire4), .clk (sub_wire0), .activeclock (), .areset (1'b0), @@ -104,12 +100,8 @@ module pll ( altpll_component.clk0_phase_shift = "0", altpll_component.clk1_divide_by = 9, altpll_component.clk1_duty_cycle = 50, - altpll_component.clk1_multiply_by = 4, + altpll_component.clk1_multiply_by = 2, altpll_component.clk1_phase_shift = "0", - altpll_component.clk2_divide_by = 9, - altpll_component.clk2_duty_cycle = 50, - altpll_component.clk2_multiply_by = 2, - altpll_component.clk2_phase_shift = "0", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 37037, altpll_component.intended_device_family = "Cyclone III", @@ -144,7 +136,7 @@ module pll ( altpll_component.port_scanwrite = "PORT_UNUSED", altpll_component.port_clk0 = "PORT_USED", altpll_component.port_clk1 = "PORT_USED", - altpll_component.port_clk2 = "PORT_USED", + altpll_component.port_clk2 = "PORT_UNUSED", altpll_component.port_clk3 = "PORT_UNUSED", altpll_component.port_clk4 = "PORT_UNUSED", altpll_component.port_clk5 = "PORT_UNUSED", @@ -184,13 +176,10 @@ endmodule // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9" -// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "6.000000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -212,33 +201,25 @@ endmodule // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" -// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4" -// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "6.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -262,16 +243,13 @@ endmodule // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" // Retrieval info: PRIVATE: USE_CLK1 STRING "1" -// Retrieval info: PRIVATE: USE_CLK2 STRING "1" // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all @@ -282,12 +260,8 @@ endmodule // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" -// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2" -// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -321,7 +295,7 @@ endmodule // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" @@ -339,13 +313,11 @@ endmodule // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" -// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE