diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1.qsf b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1.qsf index d27cc801..a4d5552e 100644 --- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1.qsf +++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1.qsf @@ -18,7 +18,7 @@ # # Quartus II 64-Bit # Version 13.1.4 Build 182 03/12/2014 SJ Full Version -# Date created = 23:55:41 May 24, 2020 +# Date created = 02:55:28 May 26, 2020 # # -------------------------------------------------------------------------- # # @@ -43,6 +43,23 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name LAST_QUARTUS_VERSION 13.1 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/System1_MiST.sv +set_global_assignment -name VERILOG_FILE rtl/System1_Top.v +set_global_assignment -name VERILOG_FILE rtl/System1_Main.v +set_global_assignment -name VERILOG_FILE rtl/System1_Decoder.v +set_global_assignment -name VERILOG_FILE rtl/System1_Video.v +set_global_assignment -name VERILOG_FILE rtl/System1_Sound.v +set_global_assignment -name VERILOG_FILE rtl/System1_Sprite.v +set_global_assignment -name VERILOG_FILE rtl/System1_Parts.v +set_global_assignment -name VERILOG_FILE rtl/System1_hvgen.v +set_global_assignment -name VERILOG_FILE rtl/SN76496.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv +set_global_assignment -name VERILOG_FILE rtl/pll_mist.v +set_global_assignment -name VERILOG_FILE rtl/z80ip.v +set_global_assignment -name VERILOG_FILE rtl/DPRAM1024_11B.v +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip +set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip # Pin & Location Assignments # ========================== @@ -222,20 +239,4 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - # end ENTITY(System1_MiST) # ------------------------ -set_global_assignment -name SYSTEMVERILOG_FILE rtl/System1_MiST.sv -set_global_assignment -name VERILOG_FILE rtl/System1_Top.v -set_global_assignment -name VERILOG_FILE rtl/System1_Main.v -set_global_assignment -name VERILOG_FILE rtl/System1_Video.v -set_global_assignment -name VERILOG_FILE rtl/System1_Sound.v -set_global_assignment -name VERILOG_FILE rtl/System1_Sprite.v -set_global_assignment -name VERILOG_FILE rtl/System1_Parts.v -set_global_assignment -name VERILOG_FILE rtl/System1_hvgen.v -set_global_assignment -name VERILOG_FILE rtl/SN76496.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv -set_global_assignment -name VERILOG_FILE rtl/pll_mist.v -set_global_assignment -name VERILOG_FILE rtl/z80ip.v -set_global_assignment -name VERILOG_FILE rtl/DPRAM1024_11B.v -set_global_assignment -name VHDL_FILE rtl/dpram.vhd -set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip -set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Decoder.v b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Decoder.v new file mode 100644 index 00000000..c69160c6 --- /dev/null +++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Decoder.v @@ -0,0 +1,206 @@ +// Copyright (c) 2017,19 MiSTer-X + +`define DECTBLADRS (25'h2E100) + +`define EN_DEC1TBL (dl_addr[17:7]==11'b10111000010;//2E100 + +`define EN_DEC2XOR (dl_addr[17:7]==11'b10111000010;//2E100 +`define EN_DEC2SWP (dl_addr[17:7]==11'b10111000011;//2E180 + +module System1_Decoder +( + input clk, + + input mrom_m1, // connect to CPU + input [14:0] mrom_ad, + output [7:0] mrom_dt, + + output [14:0] rad, // connect to ROM + input [7:0] rdt, + + input [17:0] dl_addr, + input [7:0] dl_data, + input dl_wr, + input dl_clk +); + +wire [7:0] od0,od1; +wire [14:0] dum; + +SEGASYS1_DECT1 t1(clk,mrom_m1,mrom_ad, od0, rad,rdt, dl_addr,dl_data,dl_wr,dl_clk); +SEGASYS1_DECT2 t2(clk,mrom_m1,mrom_ad, od1, dum,rdt, dl_addr,dl_data,dl_wr,dl_clk); + +// Type Detect and switch +reg [15:0] cnt0,cnt2; +always @(posedge dl_clk) begin + if (~dl_wr) begin + if (dl_addr>=`DECTBLADRS) begin + cnt2 <= (dl_data>=8'd24) ? 0 : (cnt2+1); + cnt0 <= (dl_data!=8'd0 ) ? 0 : (cnt0+1); + end + else begin + cnt2 <= 0; + cnt0 <= 0; + end + end +end +assign mrom_dt = (cnt0>=128) ? rdt : (cnt2>=128) ? od1 : od0; + +endmodule + + +//---------------------------------------- +// Program ROM Decryptor (Type 1) +//---------------------------------------- +module SEGASYS1_DECT1 +( + input clk, + + input mrom_m1, // connect to CPU + input [14:0] mrom_ad, + output reg [7:0] mrom_dt, + + output [14:0] rad, // connect to ROM + input [7:0] rdt, + + input [17:0] dl_addr, + input [7:0] dl_data, + input dl_wr, + input dl_clk +); + +reg [15:0] madr; +wire [7:0] mdat = rdt; + +wire f = mdat[7]; +wire [7:0] xorv = { f, 1'b0, f, 1'b0, f, 3'b000 }; +wire [7:0] andv = ~(8'hA8); +wire [1:0] decidx0 = { mdat[5], mdat[3] } ^ { f, f }; +wire [6:0] decidx = { madr[12], madr[8], madr[4], madr[0], ~madr[15], decidx0 }; +wire [7:0] dectbl; +wire [7:0] mdec = ( mdat & andv ) | ( dectbl ^ xorv ); + +//DLROM #(7,8) dect( clk, decidx, dectbl, ROMCL,ROMAD,ROMDT,ROMEN & `EN_DEC1TBL ); +wire dec_we = dl_addr[17:7] == 11'b10111000010;//2E100 +dpram#(8,7)decrom( + .clk_a(clk), + .addr_a(decidx), + .q_a(dectbl), + .clk_b(dl_clk), + .addr_b(dl_addr[6:0]), + .we_b(dec_we & dl_wr), + .d_b(dl_data) + ); + +assign rad = madr[14:0]; +assign mdat = rdt; + +reg phase = 1'b0; +always @( negedge clk ) begin + if ( phase ) mrom_dt <= mdec; + else madr <= { mrom_m1, mrom_ad }; + phase <= ~phase; +end + +endmodule + + +//---------------------------------------- +// Program ROM Decryptor (Type 2) +//---------------------------------------- +module SEGASYS1_DECT2 +( + input clk, + + input mrom_m1, // connect to CPU + input [14:0] mrom_ad, + output reg [7:0] mrom_dt, + + output [14:0] rad, // connect to ROM + input [7:0] rdt, + + input [17:0] dl_addr, + input [7:0] dl_data, + input dl_wr, + input dl_clk +); + +`define bsw(A,B,C,D) {v[7],v[A],v[5],v[B],v[3],v[C],v[1],v[D]} + +function [7:0] bswp; +input [4:0] m; +input [7:0] v; + + case (m) + + 0: bswp = `bsw(6,4,2,0); + 1: bswp = `bsw(4,6,2,0); + 2: bswp = `bsw(2,4,6,0); + 3: bswp = `bsw(0,4,2,6); + 4: bswp = `bsw(6,2,4,0); + 5: bswp = `bsw(6,0,2,4); + 6: bswp = `bsw(6,4,0,2); + 7: bswp = `bsw(2,6,4,0); + 8: bswp = `bsw(4,2,6,0); + 9: bswp = `bsw(4,6,0,2); + 10: bswp = `bsw(6,0,4,2); + 11: bswp = `bsw(0,6,4,2); + 12: bswp = `bsw(4,0,6,2); + 13: bswp = `bsw(0,4,6,2); + 14: bswp = `bsw(6,2,0,4); + 15: bswp = `bsw(2,6,0,4); + 16: bswp = `bsw(0,6,2,4); + 17: bswp = `bsw(2,0,6,4); + 18: bswp = `bsw(0,2,6,4); + 19: bswp = `bsw(4,2,0,6); + 20: bswp = `bsw(2,4,0,6); + 21: bswp = `bsw(4,0,2,6); + 22: bswp = `bsw(2,0,4,6); + 23: bswp = `bsw(0,2,4,6); + + default: bswp = 0; + endcase + +endfunction + +reg [15:0] madr; + +wire [7:0] sd,xd; +wire [6:0] ix = {madr[14],madr[12],madr[9],madr[6],madr[3],madr[0],~madr[15]}; + +//DLROM #(7,8) xort(clk,ix,xd, ROMCL,ROMAD,ROMDT,ROMEN & `EN_DEC2XOR); +wire dec_we = dl_addr[17:7] == 11'b10111000010;//2E100 +dpram#(8,7)decrom( + .clk_a(clk), + .addr_a(ix), + .q_a(xd), + .clk_b(dl_clk), + .addr_b(dl_addr[6:0]), + .we_b(dec_we & dl_wr), + .d_b(dl_data) + ); + +assign rad = madr[14:0]; +//assign mdat = rdt; + +//DLROM #(7,8) swpt(clk,ix,sd, ROMCL,ROMAD,ROMDT,ROMEN & `EN_DEC2SWP); +wire dec2_we = dl_addr[17:7] == 11'b10111000011;//2E180 10 1110 0001 1000 0000 +dpram#(8,7)decrom2( + .clk_a(clk), + .addr_a(ix), + .q_a(sd), + .clk_b(dl_clk), + .addr_b(dl_addr[6:0]), + .we_b(dec2_we & dl_wr), + .d_b(dl_data) + ); + +reg phase = 1'b0; +always @( negedge clk ) begin + if ( phase ) mrom_dt <= (bswp(sd,rdt) ^ xd); + else madr <= { mrom_m1, mrom_ad }; + phase <= ~phase; +end + +endmodule + diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Main.v b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Main.v index 3163cebe..58a6dfbc 100644 --- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Main.v +++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Main.v @@ -1,9 +1,11 @@ // Copyright (c) 2017,19 MiSTer-X +`define EN_MCPU0 (dl_addr[17:15]==3'b00_0 ) //todo +`define EN_MCPU8 (dl_addr[17:14]==4'b00_10) //todo + module System1_Main ( input CLK48M, - input CLK3M, input RESET, input crypt, @@ -17,13 +19,14 @@ module System1_Main input VBLK, input VIDCS, input [7:0] VIDDO, - + output reg [7:0] VIDMD, output CPUCLn, output [15:0] CPUAD, output [7:0] CPUDO, output CPUWR, - output SNDRQ, + output reg SNDRQ, + output reg [7:0] SNDNO, output [15:0] cpu_rom_addr, input [7:0] cpu_rom_do, input [17:0] dl_addr, @@ -32,6 +35,10 @@ module System1_Main input dl_clk ); +reg [3:0] clkdiv; +always @(posedge CLK48M) clkdiv <= clkdiv+1; +wire CLK3M = clkdiv[3]; + wire AXSCL = CLK48M; wire CPUCL = CLK3M; assign CPUCLn = ~CPUCL; @@ -64,104 +71,105 @@ Z80IP maincpu( assign CPUWR = _cpu_wr & cpu_mreq; assign CPURD = _cpu_rd & cpu_mreq; -assign SNDRQ = (CPUAD[4:0] == 5'b1_1000) & cpu_iorq & _cpu_wr; +// Input Port +wire cpu_cs_port; +wire [7:0] cpu_rd_port; +SEGASYS1_IPORT port(CPUAD,cpu_iorq, INP0,INP1,INP2, DSW0,DSW1, cpu_cs_port,cpu_rd_port); -wire cpu_cs_port1 = (CPUAD[4:2] == 3'b0_00) & cpu_iorq; -wire cpu_cs_port2 = (CPUAD[4:2] == 3'b0_01) & cpu_iorq; -wire cpu_cs_portS = (CPUAD[4:2] == 3'b0_10) & cpu_iorq; -wire cpu_cs_portA = (CPUAD[4:2] == 3'b0_11) & ~CPUAD[0] & cpu_iorq; -wire cpu_cs_portB =(((CPUAD[4:2] == 3'b0_11) & CPUAD[0]) | (CPUAD[4:0] == 5'b1_0000)) & cpu_iorq; -wire cpu_cs_portI = (CPUAD[4:2] == 3'b1_10) & cpu_iorq; - -wire [7:0] cpu_rd_port1 = INP0; -wire [7:0] cpu_rd_port2 = INP1; -wire [7:0] cpu_rd_portS = INP2; - -wire [7:0] cpu_rd_portA = DSW0; -wire [7:0] cpu_rd_portB = DSW1; - -wire [7:0] cpu_rd_mrom; -wire cpu_cs_mrom = (CPUAD[15:12] < 4'b1100); -PRGROM prom(AXSCL, cpu_m1, CPUAD[14:0], cpu_rd_mrom, cpu_rom_addr[14:0],cpu_rom_do,dl_addr,dl_data,dl_wr,dl_clk ); +wire cpu_cs_mrom0 = (CPUAD[15] == 1'b0 ) & cpu_mreq; +wire cpu_cs_mrom1 = (CPUAD[15:14] == 2'b10) & cpu_mreq; +wire [7:0] cpu_rd_mrom0; +wire [7:0] cpu_rd_mrom1; +wire [14:0] rad; +wire [7:0] rdt; +System1_Decoder decr(AXSCL,cpu_m1,CPUAD,cpu_rd_mrom0, cpu_rom_addr,cpu_rom_do,dl_addr,dl_data,dl_wr,dl_clk ); +//PRGROM prom(AXSCL, cpu_m1, CPUAD[14:0], cpu_rd_mrom, cpu_rom_addr[14:0],cpu_rom_do,dl_addr,dl_data,dl_wr,dl_clk ); +//DLROM #(15,8) rom0(AXSCL, rad, rdt, ROMCL,ROMAD,ROMDT,ROMEN & `EN_MCPU0); // ($0000-$7FFF encrypted) +//DLROM #(14,8) rom1(CPUCLn,CPUAD,cpu_rd_mrom1, ROMCL,ROMAD,ROMDT,ROMEN & `EN_MCPU8); // ($8000-$BFFF non-encrypted) +wire rom2_we = (dl_addr >= 16'h8000) & (dl_addr < 16'hC000); +dpram#(8,14)rom2( + .clk_a(CPUCLn), + .addr_a(CPUAD), + .q_a(cpu_rd_mrom1), + .clk_b(dl_clk), + .addr_b(dl_addr[7:0]), + .we_b(rom2_we & dl_wr), + .d_b(dl_data) + ); + +// Work RAM wire [7:0] cpu_rd_mram; -wire cpu_cs_mram = (CPUAD[15:12] == 4'b1100); +wire cpu_cs_mram = (CPUAD[15:12] == 4'b1100) & cpu_mreq; SRAM_4096 mainram(CPUCLn, CPUAD[11:0], cpu_rd_mram, cpu_cs_mram & CPUWR, CPUDO ); -reg [7:0] vidmode; -always @(posedge CPUCLn) begin - if ((CPUAD[4:0] == 5'b1_1001) & cpu_iorq & _cpu_wr) begin - vidmode <= CPUDO; +// Video mode latch & Sound Request +wire cpu_cs_sreq = ((CPUAD[7:0] == 8'h14)|(CPUAD[7:0] == 8'h18)) & cpu_iorq; +wire cpu_cs_vidm = ((CPUAD[7:0] == 8'h15)|(CPUAD[7:0] == 8'h19)) & cpu_iorq; + +wire cpu_wr_sreq = cpu_cs_sreq & _cpu_wr; +wire cpu_wr_vidm = cpu_cs_vidm & _cpu_wr; + +always @(posedge CPUCLn or posedge RESET) begin + if (RESET) begin + VIDMD <= 0; + SNDRQ <= 0; + SNDNO <= 0; + end + else begin + if (cpu_wr_vidm) VIDMD <= CPUDO; + if (cpu_wr_sreq) begin SNDNO <= CPUDO; SNDRQ <= 1'b1; end else SNDRQ <= 1'b0; end end -wire [7:0] mrom_data = (crypt == 1'b1 & CPUAD[15] == 1'b0) ? cpu_rd_mrom : cpu_rom_do; - -dataselector8 mcpudisel( +// CPU data selector +dataselector6 mcpudisel( CPUDI, - VIDCS, VIDDO, - cpu_cs_port1, cpu_rd_port1, - cpu_cs_port2, cpu_rd_port2, - cpu_cs_portS, cpu_rd_portS, - cpu_cs_portA, cpu_rd_portA, - cpu_cs_portB, cpu_rd_portB, + VIDCS, VIDDO, + cpu_cs_vidm, VIDMD, + cpu_cs_port, cpu_rd_port, cpu_cs_mram, cpu_rd_mram, - cpu_cs_mrom, mrom_data, + cpu_cs_mrom0, (crypt == 1'b1) ? cpu_rd_mrom0 : cpu_rom_do, + cpu_cs_mrom1, cpu_rd_mrom1, 8'hFF ); endmodule - -//---------------------------------- -// Program ROM with Decryptor -//---------------------------------- -module PRGROM +module SEGASYS1_IPORT ( - input clk, + input [15:0] CPUAD, + input CPUIO, - input mrom_m1, - input [14:0] mrom_ad, - output reg [7:0] mrom_dt, - output [14:0] cpu_rom_addr, - input [7:0] cpu_rom_do, - input [17:0] dl_addr, - input [7:0] dl_data, - input dl_wr, - input dl_clk + input [7:0] INP0, + input [7:0] INP1, + input [7:0] INP2, + + input [7:0] DSW0, + input [7:0] DSW1, + + output DV, + output [7:0] OD ); -reg [15:0] madr; -wire [7:0] mdat; +wire cs_port1 = (CPUAD[4:2] == 3'b0_00) & CPUIO; +wire cs_port2 = (CPUAD[4:2] == 3'b0_01) & CPUIO; +wire cs_portS = (CPUAD[4:2] == 3'b0_10) & CPUIO; +wire cs_portA = (CPUAD[4:2] == 3'b0_11) & ~CPUAD[0] & CPUIO; +wire cs_portB =(((CPUAD[4:2] == 3'b0_11) & CPUAD[0]) | (CPUAD[4:2] == 3'b1_00)) & CPUIO; -wire f = mdat[7]; -wire [7:0] xorv = { f, 1'b0, f, 1'b0, f, 3'b000 }; -wire [7:0] andv = ~(8'hA8); -wire [1:0] decidx0 = { mdat[5], mdat[3] } ^ { f, f }; -wire [6:0] decidx = { madr[12], madr[8], madr[4], madr[0], ~madr[15], decidx0 }; -wire [7:0] dectbl; -wire [7:0] mdec = ( mdat & andv ) | ( dectbl ^ xorv ); +wire [7:0] inp; +dataselector5 dsel( + inp, + cs_port1,INP0, + cs_port2,INP1, + cs_portS,INP2, + cs_portA,DSW0, + cs_portB,DSW1, + 8'hFF +); -//DLROM #( 7,8) decrom( clk, decidx, dectbl, ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16: 7]==10'b1_1110_0001_0) ); // $1E100-$1E17F -wire dec_we = dl_addr[17:7] == 11'b10111000010;//2E100 -dpram#(8,7)decrom( - .clk_a(clk), - .addr_a(decidx), - .q_a(dectbl), - .clk_b(dl_clk), - .addr_b(dl_addr[6:0]), - .we_b(dec_we & dl_wr), - .d_b(dl_data) - ); +assign DV = cs_port1|cs_port2|cs_portS|cs_portA|cs_portB; +assign OD = inp; -assign cpu_rom_addr = madr[14:0]; -assign mdat = cpu_rom_do; - -reg phase = 1'b0; -always @( negedge clk ) begin - if ( phase ) mrom_dt <= mdec; - else madr <= { mrom_m1, mrom_ad }; - phase <= ~phase; -end - -endmodule +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_MiST.sv b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_MiST.sv index 6300fb26..e5bbe5f0 100644 --- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_MiST.sv +++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_MiST.sv @@ -71,8 +71,10 @@ always @(*) begin DSW1 = 8'hFF; // crypt = 1'b0; case (core_mod) - 7'h0: // FLICKY - PIO + 7'h0: // FLICKY begin + //Sound OK(on latest Version) + //not working anymore try with new MRA(Decoder Rom2) INP0 = ~{m_left, m_right,3'b000,m_fireA,2'b00}; INP1 = ~{m_left2,m_right2,3'b000,m_fire2A,2'b00}; INP2 = ~{2'b00,m_two_players, m_one_player,3'b000, m_coin1}; @@ -81,8 +83,9 @@ always @(*) begin // crypt = 1'b1; end - 7'h1: // PITFALL2 - PIO + 7'h1: // PITFALL2 begin + //Sound OK INP0 = ~{m_left, m_right,3'd0,m_fireA,m_fireB,1'b0}; INP1 = ~{m_left2,m_right2,3'd0,m_fire2A,m_fire2B,1'b0}; INP2 = ~{2'b00,m_two_players, m_one_player,3'd0, m_coin1}; @@ -91,8 +94,9 @@ always @(*) begin // crypt = 1'b0; end - 7'h2: // STARJACKER no Sound todo + 7'h2: // STARJACKER begin + //Sound OK INP0 = ~{m_left, m_right,m_up, m_down,1'b0,m_fireA,m_fireB,1'b0}; INP1 = ~{m_left2,m_right2,m_up2, m_down2,1'b0,m_fire2A,m_fire2B,1'b0}; INP2 = ~{2'b00,m_two_players, m_one_player,dsService,2'b00, m_coin1}; @@ -101,8 +105,9 @@ always @(*) begin // crypt = 1'b0; end - 7'h3: // REGULUS - PPI no Sound todo + 7'h3: // REGULUS begin + //Sound OK INP0 = ~{m_left, m_right,m_up, m_down,1'b0,m_fireA,m_fireB,1'b0}; INP1 = ~{m_left2,m_right2,m_up2, m_down2,1'b0,m_fire2A,m_fire2B,1'b0}; INP2 = ~{2'd0,m_two_players, m_one_player,dsService,2'b0, m_coin1}; @@ -111,8 +116,9 @@ always @(*) begin // crypt = 1'b0; end - 7'h4: // UPN´DOWN - PPI no Sound todo + 7'h4: // UPN´DOWN begin + //Sound OK INP0 = ~{m_left, m_right,m_up, m_down,1'b0,m_fireA,2'b0}; INP1 = ~{m_left2,m_right2,m_up2, m_down2,1'b0,m_fire2A,2'b0}; INP2 = ~{2'd0,m_two_players, m_one_player,dsService,2'b0, m_coin1}; @@ -121,8 +127,9 @@ always @(*) begin // crypt = 1'b0; end - 7'h5: // My Hero - PIO + 7'h5: // My Hero begin + //Sound OK INP0 = ~{m_left, m_right,m_up, m_down,1'b0,m_fireA,2'b0}; INP1 = ~{m_left2,m_right2,m_up2, m_down2,1'b0,m_fire2A,2'b0}; INP2 = ~{2'd0,m_two_players, m_one_player,dsService,2'b0, m_coin1}; @@ -133,6 +140,7 @@ always @(*) begin end 7'h6: // Sega Ninja - PIO begin + //Sound OK INP0 = ~{m_left, m_right,m_up, m_down,1'b0,m_fireA,2'b0}; INP1 = ~{m_left2,m_right2,m_up2, m_down2,1'b0,m_fire2A,2'b0}; INP2 = ~{2'd0,m_two_players, m_one_player,dsService,2'b0, m_coin1}; @@ -144,6 +152,8 @@ always @(*) begin end 7'h7: // Mr Viking begin + //Sound OK(on latest Version) + //not working anymore try with new MRA(Decoder Rom2) INP0 = ~{m_left, m_right,m_up, m_down,1'b0,m_fireA,2'b0}; INP1 = ~{m_left2,m_right2,m_up2, m_down2,1'b0,m_fire2A,2'b0}; INP2 = ~{2'd0,m_two_players, m_one_player,dsService,2'b0, m_coin1}; @@ -223,7 +233,7 @@ wire [7:0] ioctl_index; wire ioctl_wr; wire [24:0] ioctl_addr; wire [7:0] ioctl_dout; -wire dl_wr = ioctl_wr && ioctl_addr < 18'h2E180; +wire dl_wr = ioctl_wr && ioctl_addr < 18'h2E200; data_io data_io( .clk_sys ( clk_sys ), @@ -237,7 +247,6 @@ data_io data_io( .ioctl_dout ( ioctl_dout ) ); - reg port1_req, port2_req; wire [24:0] tl_ioctl_addr = ioctl_addr - 18'h22000; sdram sdram( diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Parts.v b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Parts.v index 59503a4f..1e6b496c 100644 --- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Parts.v +++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Parts.v @@ -300,6 +300,30 @@ assign oDATA = iSEL0 ? iDATA0 : endmodule +//---------------------------------- +// Data Selector 5 to 1 +//---------------------------------- +module dataselector5( + + output [7:0] oDATA, + + input iSEL0, input [7:0] iDATA0, + input iSEL1, input [7:0] iDATA1, + input iSEL2, input [7:0] iDATA2, + input iSEL3, input [7:0] iDATA3, + input iSEL4, input [7:0] iDATA4, + + input [7:0] dData +); + +assign oDATA = iSEL0 ? iDATA0 : + iSEL1 ? iDATA1 : + iSEL2 ? iDATA2 : + iSEL3 ? iDATA3 : + iSEL4 ? iDATA4 : + dData; + +endmodule //---------------------------------- // Data Selector 8 to 1 diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Sound.v b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Sound.v index 2ce368c8..ad3519a0 100644 --- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Sound.v +++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Sound.v @@ -2,7 +2,7 @@ module System1_Sound ( - input clk8M, + input clk48M, input reset, input [7:0] sndno, @@ -16,8 +16,8 @@ module System1_Sound //---------------------------------- // ClockGen //---------------------------------- -wire clk4M,clk2M; -SndClkGen clkgen(clk8M,clk4M,clk2M); +wire clk8M,clk4M,clk2M; +SndClkGen clkgen(clk48M,clk8M,clk4M,clk2M); wire cpuclkx2 = clk8M; wire cpu_clk = clk4M; @@ -78,7 +78,7 @@ dataselector3 scpudisel( ); SndPlayReq sndreq ( - clk4M, reset, + clk8M, reset, sndno, sndstart, cpu_irq, cpu_irqa, cpu_nmi, cpu_nmia, @@ -121,10 +121,21 @@ endmodule module SndClkGen ( - input clk8M, - output clk4M, - output clk2M + input clk48M, + output reg clk8M, + output clk4M, + output clk2M ); + +reg [1:0] count; +always @( posedge clk48M ) begin + if (count > 2'd2) begin + count <= count - 2'd2; + clk8M <= ~clk8M; + end + else count <= count + 2'd1; +end + reg [1:0] clkdiv; always @ ( posedge clk8M ) clkdiv <= clkdiv+1; @@ -168,7 +179,7 @@ endmodule //---------------------------------- module SndPlayReq ( - input clk4M, + input clk8M, input reset, input [7:0] sndno, @@ -183,10 +194,10 @@ module SndPlayReq output reg [7:0] comlatch ); -reg [15:0] timercnt; +reg [16:0] timercnt; reg psndstart; -always @( posedge clk4M or posedge reset ) begin +always @( posedge clk8M or posedge reset ) begin if ( reset ) begin cpu_nmi <= 0; cpu_irq <= 0; @@ -204,11 +215,11 @@ always @( posedge clk4M or posedge reset ) begin end psndstart <= sndstart; - if ( timercnt == 16666 ) cpu_irq <= 1'b1; if ( timercnt == 33333 ) cpu_irq <= 1'b1; + if ( timercnt == 66666 ) cpu_irq <= 1'b1; - timercnt <= ( timercnt == 33333 ) ? 0 : (timercnt+1); // 1/60sec + timercnt <= ( timercnt == 66666 ) ? 0 : (timercnt+1); // 1/60sec end end -endmodule +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Top.v b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Top.v index 496dd259..2b4bcc8e 100644 --- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Top.v +++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Top.v @@ -44,7 +44,7 @@ CLKGEN clks( clk48M, clk24M, clk12M, clk6M, clk3M, clk8M ); // CPU wire CPUCLn; wire [15:0] CPUAD; -wire [7:0] CPUDO,VIDDO; +wire [7:0] CPUDO,VIDDO,SNDNO,VIDMD; wire CPUWR,VIDCS,VBLK; wire SNDRQ; @@ -57,7 +57,6 @@ System1_Main System1_Main( .DSW0(DSW0), .DSW1(DSW1), .CLK48M(clk48M), - .CLK3M(clk3M), .CPUCLn(CPUCLn), .CPUAD(CPUAD), .CPUDO(CPUDO), @@ -65,7 +64,9 @@ System1_Main System1_Main( .VBLK(VBLK), .VIDCS(VIDCS), .VIDDO(VIDDO), + .VIDMD(VIDMD), .SNDRQ(SNDRQ), + .SNDNO(SNDNO), .cpu_rom_addr(cpu_rom_addr), .cpu_rom_do(cpu_rom_do), .dl_addr(dl_addr), @@ -75,12 +76,11 @@ System1_Main System1_Main( ); System1_Video System1_Video( - .VCLKx8(clk48M), - .VCLKx4(clk24M), - .VCLKx2(clk12M), - .VCLK(clk6M), + .RESET(reset), + .VCLKx8(clk8M), .PH(HPOS), .PV(VPOS), + .VFLP(VIDMD[7]), .VBLK(VBLK), .RGB8(POUT), .PALDSW(1'b0), @@ -102,9 +102,9 @@ System1_Video System1_Video( assign PCLK = clk6M; System1_Sound System1_Sound( - .clk8M(clk8M), + .clk48M(clk48M), .reset(reset), - .sndno(CPUDO), + .sndno(SNDNO), .sndstart(SNDRQ), .sndout(SOUT), .snd_rom_addr(snd_rom_addr), diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Video.v b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Video.v index d3a837c7..05b2d2e0 100644 --- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Video.v +++ b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Video.v @@ -2,13 +2,13 @@ module System1_Video ( + input RESET, input VCLKx8, - input VCLKx4, - input VCLKx2, - input VCLK, + input [8:0] PH, input [8:0] PV, + input VFLP, output VBLK, output [7:0] RGB8, @@ -31,6 +31,12 @@ module System1_Video input dl_clk ); +reg [2:0] clkdiv; +always @(posedge VCLKx8) clkdiv <= clkdiv+1; +wire VCLKx4 = clkdiv[0]; +wire VCLKx2 = clkdiv[1]; +wire VCLK = clkdiv[2]; + // CPU Interface wire [10:0] palno; wire [7:0] palout; @@ -52,6 +58,7 @@ wire [15:0] scrx; wire [7:0] scry; VIDCPUINTF intf( + RESET, cpu_cl, cpu_ad, cpu_wr, cpu_dw, cpu_rd, cpu_dr, @@ -150,6 +157,7 @@ endmodule //---------------------------------- module VIDCPUINTF ( + input RESET, input cpu_cl, input [15:0] cpu_ad, input cpu_wr, @@ -225,14 +233,20 @@ VIDADEC adecs( ); // Scroll Register -always @ ( posedge cpu_cl ) begin - if (cpu_wr_scrreg) begin - case({cpu_ad[6],cpu_ad[0]}) - 2'b11: scrx[15:8] <= cpu_dw; - 2'b10: scrx[ 7:0] <= cpu_dw; - 2'b01: scry <= cpu_dw; - 2'b00: ; - endcase +always @ ( posedge cpu_cl or posedge RESET) begin + if (RESET) begin + scrx <= 0; + scry <= 0; + end + else begin + if (cpu_wr_scrreg) begin + case(cpu_ad[7:0]) + 8'hBD: scry <= cpu_dw; + 8'hFC: scrx[ 7:0] <= cpu_dw; + 8'hFD: scrx[15:8] <= cpu_dw; + default:; + endcase + end end end @@ -254,16 +268,15 @@ DPRAM2048_8_16 sprram( // Collision RAM (Mixer & Sprite) -wire noclip = 1'b1; wire [7:0] cpu_rd_mixcoll; wire [7:0] cpu_rd_sprcoll; COLLRAM_M mixc( cpu_cl,cpu_ad[5:0],cpu_wr_mixcoll,cpu_wr_mixcollclr,cpu_rd_mixcoll, - VCLKx4,mixcoll_ad,mixcoll & noclip + VCLKx4,mixcoll_ad,mixcoll ); COLLRAM_S sprc( cpu_cl,cpu_ad[9:0],cpu_wr_sprcoll,cpu_wr_sprcollclr,cpu_rd_sprcoll, - VCLKx4,sprcoll_ad,sprcoll & noclip + VCLKx4,sprcoll_ad,sprcoll ); @@ -377,16 +390,16 @@ module VIDHVGEN output VBLK ); -assign VBLK = (PV == 8'd224) & (PH <= 8'd64); +assign VBLK = (PV == 9'd224) & (PH <= 9'd64); assign HPOS = PH+1; assign VPOS = PV; -wire [8:0] BGHSCR = (511-scrx[9:1])-10; -wire [8:0] BGVSCR = { 1'b0, scry }; +wire [7:0] BGHSCR = scrx[9:1]+14; +wire [7:0] BGVSCR = scry; -assign BG0HP = BGHSCR+HPOS; -assign BG0VP = BGVSCR+VPOS; +assign BG0HP = (HPOS-BGHSCR)+3; +assign BG0VP = (VPOS+BGVSCR); assign BG1HP = HPOS+3; assign BG1VP = VPOS; @@ -422,15 +435,15 @@ module VIDADEC output cpu_rd ); -assign cpu_cs_palram = ( cpu_ad[15:11] == 5'b1101_1 ); -assign cpu_cs_spram = ( cpu_ad[15:11] == 5'b11010 ); -assign cpu_cs_mixcoll = ( cpu_ad[15:10] == 6'b1111_00 ); -wire cpu_cs_mixcollclr = ( cpu_ad[15:10] == 6'b1111_01 ); -assign cpu_cs_sprcoll = ( cpu_ad[15:10] == 6'b1111_10 ); -wire cpu_cs_sprcollclr = ( cpu_ad[15:10] == 6'b1111_11 ); -assign cpu_cs_vram0 = ( cpu_ad[15:11] == 5'b11100 ); -assign cpu_cs_vram1 = ( cpu_ad[15:11] == 5'b11101 ); -wire cpu_cs_scrreg = ((cpu_ad[15: 0] & 16'b1111_1111_1011_1110) == 16'b1110_1111_1011_1100); +assign cpu_cs_palram = (cpu_ad[15:11] == 5'b1101_1 ); +assign cpu_cs_spram = (cpu_ad[15:11] == 5'b1101_0 ); +assign cpu_cs_mixcoll = (cpu_ad[15:10] == 6'b1111_00 ); +wire cpu_cs_mixcollclr = (cpu_ad[15:10] == 6'b1111_01 ); +assign cpu_cs_sprcoll = (cpu_ad[15:10] == 6'b1111_10 ); +wire cpu_cs_sprcollclr = (cpu_ad[15:10] == 6'b1111_11 ); +assign cpu_cs_vram0 = (cpu_ad[15:11] == 5'b1110_0 ); +assign cpu_cs_vram1 = (cpu_ad[15:11] == 5'b1110_1 ); +wire cpu_cs_scrreg = (cpu_ad[15: 8] == 8'b1110_1111); assign cpu_wr_palram = cpu_cs_palram & cpu_wr; @@ -566,17 +579,12 @@ module COLLRAM_M reg [63:0] core; reg coll_rd, coll_sm; -always @(posedge cpu_cl) coll_rd <= core[cpu_ad]; - always @(posedge VCLKx4) begin - if (cpu_cl) begin - if (cpu_wr_coll) core[cpu_ad] <= 1'b0; - if (cpu_wr_collclr) coll_sm <= 1'b0; - end - else coll_sm <= coll; - if (coll) core[coll_ad] <= 1'b1; + if (cpu_cl & cpu_wr_coll) core[cpu_ad] <= 1'b0; else if (coll) core[coll_ad] <= 1'b1; + if (cpu_cl & cpu_wr_collclr) coll_sm <= 1'b0; else if (coll) coll_sm <= 1'b1; end +always @(posedge cpu_cl) coll_rd <= core[cpu_ad]; assign cpu_rd_coll = { coll_sm, 6'b111111, coll_rd }; endmodule @@ -597,18 +605,12 @@ module COLLRAM_S reg [1023:0] core; reg coll_rd, coll_sm; -always @(posedge cpu_cl) coll_rd <= core[cpu_ad]; - always @(posedge VCLKx4) begin - if (cpu_cl) begin - if (cpu_wr_coll) core[cpu_ad] <= 1'b0; - if (cpu_wr_collclr) coll_sm <= 1'b0; - end - else coll_sm <= coll; - if (coll) core[coll_ad] <= 1'b1; + if (cpu_cl & cpu_wr_coll ) core[cpu_ad] <= 1'b0; else if (coll) core[coll_ad] <= 1'b1; + if (cpu_cl & cpu_wr_collclr) coll_sm <= 1'b0; else if (coll) coll_sm <= 1'b1; end +always @(posedge cpu_cl) coll_rd <= core[cpu_ad]; assign cpu_rd_coll = { coll_sm, 6'b111111, coll_rd }; -endmodule - +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/pll_mist.qip b/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/pll_mist.qip deleted file mode 100644 index 6182871f..00000000 --- a/Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/pll_mist.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_mist.v"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"]