From fecc94a2903dece73e6dcdbe97a19dbb2279b3fd Mon Sep 17 00:00:00 2001 From: Marcel Date: Thu, 13 Jul 2023 12:03:43 +0200 Subject: [PATCH] Update true_dual_port_ram.vhd --- Arcade_MiST/Toaplan v1 Hardware/rtl/true_dual_port_ram.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Arcade_MiST/Toaplan v1 Hardware/rtl/true_dual_port_ram.vhd b/Arcade_MiST/Toaplan v1 Hardware/rtl/true_dual_port_ram.vhd index 03011d30..fbfb61d6 100644 --- a/Arcade_MiST/Toaplan v1 Hardware/rtl/true_dual_port_ram.vhd +++ b/Arcade_MiST/Toaplan v1 Hardware/rtl/true_dual_port_ram.vhd @@ -78,7 +78,7 @@ begin clock_enable_output_a => "BYPASS", clock_enable_output_b => "BYPASS", indata_reg_b => "CLOCK1", - intended_device_family => "Cyclone V", + intended_device_family => "Cyclone III", lpm_type => "altsyncram", numwords_a => 2**ADDR_WIDTH_A, numwords_b => 2**ADDR_WIDTH_B,