diff --git a/Arcade_MiST/Data East Express Raider/ExpressRaider.qpf b/Arcade_MiST/Data East Express Raider/ExpressRaider.qpf new file mode 100644 index 00000000..2a72afd3 --- /dev/null +++ b/Arcade_MiST/Data East Express Raider/ExpressRaider.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "ExpressRaider" diff --git a/Arcade_MiST/Data East Express Raider/ExpressRaider.qsf b/Arcade_MiST/Data East Express Raider/ExpressRaider.qsf new file mode 100644 index 00000000..830f6db1 --- /dev/null +++ b/Arcade_MiST/Data East Express Raider/ExpressRaider.qsf @@ -0,0 +1,235 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 05:08:48 November 15, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Arcade-Scramble_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_90 -to SPI_SS4 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PIN_49 -to SDRAM_A[0] +set_location_assignment PIN_44 -to SDRAM_A[1] +set_location_assignment PIN_42 -to SDRAM_A[2] +set_location_assignment PIN_39 -to SDRAM_A[3] +set_location_assignment PIN_4 -to SDRAM_A[4] +set_location_assignment PIN_6 -to SDRAM_A[5] +set_location_assignment PIN_8 -to SDRAM_A[6] +set_location_assignment PIN_10 -to SDRAM_A[7] +set_location_assignment PIN_11 -to SDRAM_A[8] +set_location_assignment PIN_28 -to SDRAM_A[9] +set_location_assignment PIN_50 -to SDRAM_A[10] +set_location_assignment PIN_30 -to SDRAM_A[11] +set_location_assignment PIN_32 -to SDRAM_A[12] +set_location_assignment PIN_83 -to SDRAM_DQ[0] +set_location_assignment PIN_79 -to SDRAM_DQ[1] +set_location_assignment PIN_77 -to SDRAM_DQ[2] +set_location_assignment PIN_76 -to SDRAM_DQ[3] +set_location_assignment PIN_72 -to SDRAM_DQ[4] +set_location_assignment PIN_71 -to SDRAM_DQ[5] +set_location_assignment PIN_69 -to SDRAM_DQ[6] +set_location_assignment PIN_68 -to SDRAM_DQ[7] +set_location_assignment PIN_86 -to SDRAM_DQ[8] +set_location_assignment PIN_87 -to SDRAM_DQ[9] +set_location_assignment PIN_98 -to SDRAM_DQ[10] +set_location_assignment PIN_99 -to SDRAM_DQ[11] +set_location_assignment PIN_100 -to SDRAM_DQ[12] +set_location_assignment PIN_101 -to SDRAM_DQ[13] +set_location_assignment PIN_103 -to SDRAM_DQ[14] +set_location_assignment PIN_104 -to SDRAM_DQ[15] +set_location_assignment PIN_58 -to SDRAM_BA[0] +set_location_assignment PIN_51 -to SDRAM_BA[1] +set_location_assignment PIN_85 -to SDRAM_DQMH +set_location_assignment PIN_67 -to SDRAM_DQML +set_location_assignment PIN_60 -to SDRAM_nRAS +set_location_assignment PIN_64 -to SDRAM_nCAS +set_location_assignment PIN_66 -to SDRAM_nWE +set_location_assignment PIN_59 -to SDRAM_nCS +set_location_assignment PIN_33 -to SDRAM_CKE +set_location_assignment PIN_43 -to SDRAM_CLK +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_* +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_* +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name TOP_LEVEL_ENTITY ExpressRaider_MiST + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# ---------------------- +# start ENTITY(ExpressRaider) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(ExpressRaider) +# -------------------- +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE output_files/cpu.stp +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON +set_global_assignment -name FORCE_SYNCH_CLEAR ON +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name VERILOG_MACRO "EXT_ROM=1" +set_global_assignment -name VERILOG_MACRO "SYNTH=1" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/ExpressRaider_MiST.sv +set_global_assignment -name QIP_FILE rtl/pll_mist.qip +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv +set_global_assignment -name VERILOG_FILE rtl/prot.v +set_global_assignment -name VERILOG_FILE rtl/er_decode.v +set_global_assignment -name VERILOG_FILE rtl/core.v +set_global_assignment -name VERILOG_FILE rtl/audio/audio.v +set_global_assignment -name VERILOG_FILE rtl/audio/acpu_mem.v +set_global_assignment -name VERILOG_FILE rtl/cpu/CPU16.v +set_global_assignment -name VERILOG_FILE rtl/cpu/mcpu_rom.v +set_global_assignment -name VERILOG_FILE rtl/cpu/mcpu.v +set_global_assignment -name VERILOG_FILE rtl/video/VSC30.v +set_global_assignment -name VERILOG_FILE rtl/video/video.v +set_global_assignment -name VERILOG_FILE rtl/video/vdata.v +set_global_assignment -name VERILOG_FILE rtl/video/hvgen.v +set_global_assignment -name VERILOG_FILE rtl/tools/rising_edge.v +set_global_assignment -name VERILOG_FILE rtl/tools/falling_edge.v +set_global_assignment -name VERILOG_FILE rtl/tools/clk_en.v +set_global_assignment -name VERILOG_FILE rtl/mem/ram.v +set_global_assignment -name VERILOG_FILE rtl/mem/dpram.v +set_global_assignment -name QIP_FILE ../../common/mist/mist.qip +set_global_assignment -name QIP_FILE ../../common/CPU/T65/T65.qip +set_global_assignment -name QIP_FILE ../../common/Sound/JT12/hdl/jt03.qip +set_global_assignment -name QIP_FILE ../../common/Sound/jtopl/jt26.qip +set_global_assignment -name QIP_FILE ../../common/Sound/JT49/jt49.qip +set_global_assignment -name VERILOG_FILE ../../common/CPU/MC6809/mc6809is.v +set_global_assignment -name CDF_FILE output_files/Chain1.cdf +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Data East Express Raider/ExpressRaider.sdc b/Arcade_MiST/Data East Express Raider/ExpressRaider.sdc new file mode 100644 index 00000000..be003953 --- /dev/null +++ b/Arcade_MiST/Data East Express Raider/ExpressRaider.sdc @@ -0,0 +1,135 @@ +## Generated SDC file "vectrex_MiST.out.sdc" + +## Copyright (C) 1991-2013 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +## DATE "Sun Jun 24 12:53:00 2018" + +## +## DEVICE "EP3C25E144C8" +## + +# Clock constraints + +# Automatically constrain PLL and other generated clocks +derive_pll_clocks -create_base_clocks + +# Automatically calculate clock uncertainty to jitter and other effects. +derive_clock_uncertainty + +# tsu/th constraints + +# tco constraints + +# tpd constraints + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] + +set sys_clk "pll|altpll_component|auto_generated|pll1|clk[0]" +set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]" + +#************************************************************** +# Create Generated Clock +#************************************************************** + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +#************************************************************** +# Set Input Delay +#************************************************************** + +set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] + +set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]] +set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]] + +#************************************************************** +# Set Output Delay +#************************************************************** + +set_output_delay -add_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] +set_output_delay -add_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}] +set_output_delay -add_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}] +set_output_delay -add_delay -clock [get_clocks $sdram_clk] 1.000 [get_ports {LED}] +set_output_delay -add_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}] + +set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] +set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] + +#************************************************************** +# Set Clock Groups +#************************************************************** + +set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + +set_multicycle_path -to {VGA_*[*]} -setup 2 +set_multicycle_path -to {VGA_*[*]} -hold 1 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/Arcade_MiST/Data East Express Raider/Readme.md b/Arcade_MiST/Data East Express Raider/Readme.md new file mode 100644 index 00000000..e7089c7b --- /dev/null +++ b/Arcade_MiST/Data East Express Raider/Readme.md @@ -0,0 +1,5 @@ +# Express Raider + +## General description +This core is a port of Express Raider PCB from Data East USA by [Pierco](https://github.com/pcornier). I tried to stay as close as possible to the original schematics. + diff --git a/Arcade_MiST/Data East Express Raider/_schematics/Express Raider Schematics.pdf b/Arcade_MiST/Data East Express Raider/_schematics/Express Raider Schematics.pdf new file mode 100644 index 00000000..c92510c2 Binary files /dev/null and b/Arcade_MiST/Data East Express Raider/_schematics/Express Raider Schematics.pdf differ diff --git a/Arcade_MiST/Data East Express Raider/meta/Express Raider.mra b/Arcade_MiST/Data East Express Raider/meta/Express Raider.mra new file mode 100644 index 00000000..06b57a39 --- /dev/null +++ b/Arcade_MiST/Data East Express Raider/meta/Express Raider.mra @@ -0,0 +1,79 @@ + + Express Raider (World, Rev 4) + exprraid + no + no + + 1986 + Data East USA + Platform / Fighter Scrolling + expressraider + + 15kHz + horizontal + + 2 + 8-way + + 4 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Arcade_MiST/Data East Express Raider/meta/Western Express (Japan, rev 4).mra b/Arcade_MiST/Data East Express Raider/meta/Western Express (Japan, rev 4).mra new file mode 100644 index 00000000..642d17ac --- /dev/null +++ b/Arcade_MiST/Data East Express Raider/meta/Western Express (Japan, rev 4).mra @@ -0,0 +1,79 @@ + + Western Express (Japan, rev 4) + no + no + + 1986 + Data East USA + Platform / Fighter Scrolling + expressraider + + 15kHz + horizontal + + 2 + 8-way + + 4 + wexpress + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Arcade_MiST/Data East Express Raider/rtl/ExpressRaider_MiST.sv b/Arcade_MiST/Data East Express Raider/rtl/ExpressRaider_MiST.sv new file mode 100644 index 00000000..96a23c9b --- /dev/null +++ b/Arcade_MiST/Data East Express Raider/rtl/ExpressRaider_MiST.sv @@ -0,0 +1,341 @@ +//============================================================================ +// Data East Express Raider top-level for MiST +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module ExpressRaider_MiST +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + inout SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input SPI_SS4, + input CONF_DATA0, + input CLOCK_27, + + output [12:0] SDRAM_A, + inout [15:0] SDRAM_DQ, + output SDRAM_DQML, + output SDRAM_DQMH, + output SDRAM_nWE, + output SDRAM_nCAS, + output SDRAM_nRAS, + output SDRAM_nCS, + output [1:0] SDRAM_BA, + output SDRAM_CLK, + output SDRAM_CKE +); + +`include "build_id.v" + +`define CORE_NAME "EXPRRAID" +wire [6:0] core_mod; + +localparam CONF_STR = { + `CORE_NAME, ";;", + "O2,Rotate Controls,Off,On;", + "O34,Scanlines,Off,25%,50%,75%;", + "O5,Blending,Off,On;", + "O6,Joystick Swap,Off,On;", + "O7,Pause,Off,On;", + "DIP;", + "T0,Reset;", + "V,v1.20.",`BUILD_DATE +}; + +wire rotate = status[2]; +wire [1:0] scanlines = status[4:3]; +wire blend = status[5]; +wire joyswap = status[6]; +wire pause = status[7]; +wire [7:0] sw0 = status[15:8]; +wire [7:0] sw1 = status[23:16]; + +assign LED = ~ioctl_downl; +assign SDRAM_CLK = clk_96; +assign SDRAM_CKE = 1; + +wire clk_96, clk_48; +wire pll_locked; +pll_mist pll( + .inclk0(CLOCK_27), + .c0(clk_96), + .c1(clk_48), + .locked(pll_locked) + ); + +// reset generation +reg reset = 1; +reg rom_loaded = 0; +always @(posedge clk_48) begin + reg ioctl_downlD; + ioctl_downlD <= ioctl_downl; + + if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1; + reset <= status[0] | buttons[1] | ~rom_loaded | ioctl_downl; +end + +// ARM connection +wire [63:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [31:0] joystick_0; +wire [31:0] joystick_1; +wire scandoublerD; +wire ypbpr; +wire no_csync; +wire key_strobe; +wire key_pressed; +wire [7:0] key_code; + +user_io #( + .STRLEN($size(CONF_STR)>>3), + .ROM_DIRECT_UPLOAD(1)) +user_io( + .clk_sys (clk_48 ), + .conf_str (CONF_STR ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable (scandoublerD ), + .ypbpr (ypbpr ), + .no_csync (no_csync ), + .core_mod (core_mod ), + .key_strobe (key_strobe ), + .key_pressed (key_pressed ), + .key_code (key_code ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) + ); + +wire ioctl_downl; +wire [7:0] ioctl_index; +wire ioctl_wr; +wire [24:0] ioctl_addr; +wire [7:0] ioctl_dout; + +data_io #(.ROM_DIRECT_UPLOAD(1)) data_io( + .clk_sys ( clk_48 ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS2 ( SPI_SS2 ), + .SPI_SS4 ( SPI_SS4 ), + .SPI_DI ( SPI_DI ), + .SPI_DO ( SPI_DO ), + .ioctl_download( ioctl_downl ), + .ioctl_index ( ioctl_index ), + .ioctl_wr ( ioctl_wr ), + .ioctl_addr ( ioctl_addr ), + .ioctl_dout ( ioctl_dout ) +); + +wire rom_cs; +wire [15:0] rom_addr; +wire [15:0] rom_do; +wire snd_cs; +wire [14:0] snd_addr; +wire [15:0] snd_do; +wire [14:0] gfx1_addr; +wire [15:0] gfx1_do; +wire [14:0] gfx2_addr; +wire [15:0] gfx2_do; +wire [15:0] gfx3_addr; +wire [31:0] gfx3_do; +wire [15:0] sp_addr; +wire [31:0] sp_do; +reg port1_req, port2_req; +reg [23:0] port1_a; +reg [23:0] port2_a; + +// ROM download controller +always @(posedge clk_48) begin + reg ioctl_wr_last = 0; + + ioctl_wr_last <= ioctl_wr; + if (ioctl_downl) begin + if (~ioctl_wr_last && ioctl_wr && ioctl_index == 0) begin + port1_req <= ~port1_req; + port2_req <= ~port2_req; + end + end +end + +sdram #(96) sdram( + .*, + .init_n ( pll_locked ), + .clk ( clk_96 ), + + // port1 used for main + sound CPU + .port1_req ( port1_req ), + .port1_ack ( ), + .port1_a ( ioctl_addr[23:1] ), + .port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ), + .port1_we ( ioctl_downl ), + .port1_d ( {ioctl_dout, ioctl_dout} ), + .port1_q ( ), + + .cpu1_cs ( rom_cs ), + .cpu1_addr ( rom_addr[15:1] ), + .cpu1_q ( rom_do ), + .cpu2_cs ( snd_cs ), + .cpu2_addr ( 15'h6000 + snd_addr[14:1] ), + .cpu2_q ( snd_do ), + .gfx1_addr ( 20'h38000 + gfx1_addr[14:1] ), + .gfx1_q ( gfx1_do ), + .gfx2_addr ( 20'h2C000 + gfx2_addr[14:1] ), + .gfx2_q ( gfx2_do ), + + // port2 for sprite graphics + .port2_req ( port2_req ), + .port2_ack ( ), + .port2_a ( ioctl_addr[23:1] ), + .port2_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ), + .port2_we ( ioctl_downl ), + .port2_d ( {ioctl_dout, ioctl_dout} ), + .port2_q ( ), + + .gfx3_addr ( 20'h18000 + gfx3_addr[14:1] ), + .gfx3_q ( gfx3_do ), + .sp_addr ( 20'h6000 + sp_addr ), + .sp_q ( sp_do ) +); + +reg [7:0] gfx3_data; +always @(*) + case({gfx3_addr[0], gfx3_addr[15]}) + 2'b00: gfx3_data = gfx3_do[7:0]; + 2'b01: gfx3_data = gfx3_do[15:8]; + 2'b10: gfx3_data = gfx3_do[23:16]; + 2'b11: gfx3_data = gfx3_do[31:24]; + default: ; + endcase + +wire rom_dl = ioctl_downl && ioctl_index == 0; +wire [16:0] sound; +wire HSync, VSync; +wire HBlank, VBlank; +wire blankn = ~(HBlank | VBlank); +wire [3:0] vred, vgreen, vblue; + +wire [7:0] p1 = ~{ m_two_players, m_one_player, m_fire1[1], m_fire1[0], m_down1, m_up1, m_left1, m_right1 }; +wire [7:0] p2 = ~{ m_coin2, m_coin1, m_fire2[1], m_fire2[0], m_down2, m_up2, m_left2, m_right2 }; + +core u_core( + .reset ( reset ), + .clk_sys ( clk_48 ), + .pause ( pause ), + .p1 ( p1 ), + .p2 ( p2 ), + .p3 ( sw1 ), + .dsw ( sw0 ), + .ioctl_index ( ioctl_index ), + .ioctl_download ( rom_dl ), + .ioctl_addr ( ioctl_addr ), + .ioctl_dout ( ioctl_dout ), + .ioctl_wr ( ioctl_wr ), + .red ( vred ), + .green ( vgreen ), + .blue ( vblue ), + .vs ( VSync ), + .vb ( VBlank ), + .hs ( HSync ), + .hb ( HBlank ), + .ce_pix ( ), + .sound ( sound ), + .cpu_rom_cs ( rom_cs ), + .cpu_rom_addr ( rom_addr ), + .cpu_rom_data ( rom_addr[0] ? rom_do[15:8] : rom_do[7:0] ), + .audio_rom_cs ( snd_cs ), + .audio_rom_addr ( snd_addr ), + .audio_rom_data ( snd_addr[0] ? snd_do[15:8] : snd_do[7:0] ), + .gfx1_addr ( gfx1_addr ), + .gfx1_data ( gfx1_addr[0] ? gfx1_do[15:8] : gfx1_do[7:0] ), + .gfx2_addr ( gfx2_addr ), + .gfx2_data ( gfx2_addr[0] ? gfx2_do[15:8] : gfx2_do[7:0] ), + .gfx3_addr ( gfx3_addr ), + .gfx3_data ( gfx3_data ), + .sp_addr ( sp_addr ), + .sp_data ( sp_do ) +); + +mist_video #(.COLOR_DEPTH(4),.SD_HCNT_WIDTH(10)) mist_video( + .clk_sys(clk_48), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(blankn ? vred : 4'd0), + .G(blankn ? vgreen : 4'd0), + .B(blankn ? vblue : 4'd0), + .HSync(~HSync), + .VSync(~VSync), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .no_csync(no_csync), + .rotate({1'b0,rotate}), + .ce_divider(3'd0), // pix clock = 48/4 + .blend(blend), + .scandoubler_disable(scandoublerD), + .scanlines(scanlines), + .ypbpr(ypbpr) + ); + +dac #(16) dacl( + .clk_i(clk_48), + .res_n_i(1), + .dac_i({~sound[16], sound[15:1]}), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + +// Common inputs +wire m_up1, m_down1, m_left1, m_right1, m_up1B, m_down1B, m_left1B, m_right1B; +wire m_up2, m_down2, m_left2, m_right2, m_up2B, m_down2B, m_left2B, m_right2B; +wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players; +wire [11:0] m_fire1, m_fire2; + +arcade_inputs inputs ( + .clk ( clk_48 ), + .key_strobe ( key_strobe ), + .key_pressed ( key_pressed ), + .key_code ( key_code ), + .joystick_0 ( joystick_0 ), + .joystick_1 ( joystick_1 ), + .rotate ( rotate ), + .orientation ( 2'b00 ), + .joyswap ( joyswap ), + .oneplayer ( 1'b0 ), + .controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ), + .player1 ( {m_up1B, m_down1B, m_left1B, m_right1B, m_fire1, m_up1, m_down1, m_left1, m_right1} ), + .player2 ( {m_up2B, m_down2B, m_left2B, m_right2B, m_fire2, m_up2, m_down2, m_left2, m_right2} ) +); + +endmodule diff --git a/Arcade_MiST/Data East Express Raider/rtl/audio/acpu_mem.v b/Arcade_MiST/Data East Express Raider/rtl/audio/acpu_mem.v new file mode 100644 index 00000000..8e9bf759 --- /dev/null +++ b/Arcade_MiST/Data East Express Raider/rtl/audio/acpu_mem.v @@ -0,0 +1,78 @@ + +module acpu_mem( + input clk_sys, + input cpu_cen, + input [15:0] acpu_ab, + input [7:0] din, + output [7:0] dout, + input rw, + input ioctl_download, + input [26:0] ioctl_addr, + input [15:0] ioctl_dout, + input ioctl_wr, + input [7:0] mcpu_dout, + input snd_write, + output cs1, + output cs2, + input [7:0] ym2203_data, + input [7:0] ym3526_data, + output rom_cs, + output[14:0] rom_addr, + input [7:0] rom_data +); + +wire [7:0] u3A_q; +wire [7:0] u6A_q; + +reg [7:0] u2E; +always @(posedge clk_sys) + if (snd_write) u2E <= mcpu_dout; + +// memory map decoding u1D +// cs1 = ym2203 cs2 = ym3526 cs3 = snd latch +wire [3:0] cs = acpu_ab[15] ? 4'b0 : 1 << acpu_ab[14:13]; + +assign cs1 = cs[1]; +assign cs2 = cs[2]; + +//always @(posedge clk_sys) +// if (cpu_cen) +assign dout = + cs[0] ? u6A_q : // ram + cs[1] ? ym2203_data : + cs[2] ? ym3526_data : + cs[3] ? u2E : // snd latch + u3A_q; // rom + +assign rom_cs = acpu_ab[15]; +assign rom_addr = acpu_ab[14:0]; + +`ifdef EXT_ROM +assign u3A_q = rom_data; +`else + +wire [14:0] u3A_addr = ioctl_download ? ioctl_addr - 27'hc000 : acpu_ab[14:0]; +wire u3A_wr_n = ioctl_download && ioctl_addr >= 27'hc000 && ioctl_addr < 27'h14000 ? ioctl_wr : 1'b0; + +ram #(15,8) u3A( + .clk ( clk_sys ), + .addr ( u3A_addr ), + .din ( ioctl_dout ), + .q ( u3A_q ), + .rd_n ( 1'b0 ), + .wr_n ( ~u3A_wr_n ), + .ce_n ( ~acpu_ab[15] ) +); +`endif + +ram #(11,8) u6A( + .clk ( clk_sys ), + .addr ( acpu_ab[10:0] ), + .din ( din ), + .q ( u6A_q ), + .rd_n ( 1'b0 ), + .wr_n ( rw | ~cs[0] ), + .ce_n ( ~cs[0] ) +); + +endmodule diff --git a/Arcade_MiST/Data East Express Raider/rtl/audio/audio.v b/Arcade_MiST/Data East Express Raider/rtl/audio/audio.v new file mode 100644 index 00000000..d9733e73 --- /dev/null +++ b/Arcade_MiST/Data East Express Raider/rtl/audio/audio.v @@ -0,0 +1,136 @@ + +module audio( + input reset, + input clk_sys, + input ioctl_download, + input [26:0] ioctl_addr, + input [15:0] ioctl_dout, + input ioctl_wr, + input snd_write, + input [7:0] mcpu_dout, + output signed [16:0] sound_mix, + output rom_cs, + output [14:0] rom_addr, + input [7:0] rom_data +); + +wire cen_e, cen_q, clk_e, clk_q; +clk_en #( 31 ) cpu_clk_e(clk_sys, cen_e, clk_e); +clk_en #( 31, 8 ) cpu_clk_q(clk_sys, cen_q, clk_q); + + +wire ym3526_irq; +wire [7:0] acpu_di; +wire [7:0] acpu_do; +wire [15:0] acpu_ab; +wire acpu_rw; +wire bs, ba; +wire n_irq = ym3526_irq; +wire n_firq = 1'b1; +wire n_nmi = ~snd_write; +wire avma; +wire busy; +wire lic; +wire [7:0] ym2203_do; +wire [7:0] ym3526_do; +wire cs1, cs2; +reg [7:0] ym2203_do2; + + +mc6809is u_acpu( + .CLK ( clk_sys ), + .D ( acpu_di ), + .DOut ( acpu_do ), + .ADDR ( acpu_ab ), + .RnW ( acpu_rw ), + .fallE_en ( cen_e ), + .fallQ_en ( cen_q ), + .BS ( bs ), + .BA ( ba ), + .nIRQ ( n_irq ), + .nFIRQ ( n_firq ), + .nNMI ( n_nmi ), + .AVMA ( avma ), + .BUSY ( busy ), + .LIC ( lic ), + .nHALT ( 1'b1 ), + .nRESET ( ~reset ), + .nDMABREQ ( 1'b1 ) +); + +acpu_mem u_acpu_mem( + .clk_sys ( clk_sys ), + .cpu_cen ( cen_q ), + .acpu_ab ( acpu_ab ), + .din ( acpu_do ), + .dout ( acpu_di ), + .rw ( acpu_rw ), + .ioctl_download ( ioctl_download ), + .ioctl_addr ( ioctl_addr ), + .ioctl_dout ( ioctl_dout ), + .ioctl_wr ( ioctl_wr ), + .mcpu_dout ( mcpu_dout ), + .snd_write ( snd_write ), + .cs1 ( cs1 ), + .cs2 ( cs2 ), + .ym2203_data ( ym2203_do ), + .ym3526_data ( ym3526_do ), + .rom_cs ( rom_cs ), + .rom_addr ( rom_addr ), + .rom_data ( rom_data ) +); + +wire cen_6, cen_12; +wire clk_6, clk_12; + +clk_en #( 31 ) m2h_en(clk_sys, cen_6, clk_6); +clk_en #( 15 ) m1h_en(clk_sys, cen_12, clk_12); + +// all +assign sound_mix = {ym3526_snd[15], ym3526_snd[15:0]} + {ym2203_snd[15], ym2203_snd[15:0]} + ym2203_psg[9:0]; + +wire signed [15:0] ym2203_snd; +wire [9:0] ym2203_psg; +wire signed [15:0] ym3526_snd; + +wire wr1 = acpu_rw; + +jt03 ym2203( + .rst ( reset ), + .clk ( clk_sys ), + .cen ( cen_6 ), + .din ( acpu_do ), + .addr ( acpu_ab[0] ), + .cs_n ( ~cs1 ), + .wr_n ( wr1 ), + .dout ( ym2203_do ), + .snd ( ym2203_snd ), + .psg_snd ( ym2203_psg ) +); + +reg old_cs2; +reg [7:0] ym3526_din; +reg ym3526_addr; +always @(posedge clk_sys) begin + old_cs2 <= cs2; + if (~old_cs2 & cs2) begin + ym3526_din <= acpu_do; + ym3526_addr <= acpu_ab[0]; + end +end + +jtopl ym3526( + .rst ( reset ), + .clk ( clk_sys ), + .cen ( cen_12 ), + .din ( ym3526_din ), + .addr ( ym3526_addr ), + .cs_n ( ~cs2 ), + .wr_n ( wr1 ), + .dout ( ym3526_do ), + .irq_n ( ym3526_irq ), + .snd ( ym3526_snd ) +); + + +endmodule diff --git a/Arcade_MiST/Data East Express Raider/rtl/build_id.tcl b/Arcade_MiST/Data East Express Raider/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade_MiST/Data East Express Raider/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Data East Express Raider/rtl/core.v b/Arcade_MiST/Data East Express Raider/rtl/core.v new file mode 100644 index 00000000..24c6fcaf --- /dev/null +++ b/Arcade_MiST/Data East Express Raider/rtl/core.v @@ -0,0 +1,242 @@ + +module core( + + input reset, + input clk_sys, + input pause, + + input [7:0] p1, + input [7:0] p2, + input [7:0] p3, + input [7:0] dsw, + + input [7:0] ioctl_index, + input ioctl_download, + input [26:0] ioctl_addr, + input [15:0] ioctl_dout, + input ioctl_wr, + + output [3:0] red, + output [3:0] green, + output [3:0] blue, + output vb, + output hb, + output vs, + output hs, + output ce_pix, + + output signed [16:0] sound, + + output cpu_rom_cs, + output [15:0] cpu_rom_addr, + input [7:0] cpu_rom_data, + output audio_rom_cs, + output [14:0] audio_rom_addr, + input [7:0] audio_rom_data, + output[14:0] gfx1_addr, + input [7:0] gfx1_data, + output[14:0] gfx2_addr, + input [7:0] gfx2_data, + output[15:0] gfx3_addr, + input [7:0] gfx3_data, + output[15:0] sp_addr, + input [31:0] sp_data +); + +wire [7:0] cpu_dout; +wire [15:0] cpu_ab; +wire [7:0] romdata; +wire [7:0] prot_data; +wire [7:0] prot_status; +wire [7:0] sram_data; +wire [14:0] map_rom_addr; +wire [7:0] map_data; +wire [15:0] bg_rom_addr; +wire [7:0] bg_data1; +wire [7:0] bg_data2; +wire [13:0] char_rom_addr; +wire [7:0] char_data; +wire [7:0] col_rom_addr; +wire [11:0] col_data; +wire [15:0] sp_rom_addr; +wire [7:0] sp_rom_data1; +wire [7:0] sp_rom_data2; +wire [7:0] sp_rom_data3; +wire [7:0] prom_addr; +wire [7:0] prom_data; +wire sram_cs; +wire vram_cs; +wire cram_cs; +wire rom_cs; +wire ds0_read; +wire ds1_read; +wire in1_read; +wire in2_read; +wire nmi_clear; +wire snd_write; +wire flp_write; +wire dma_swap; +wire bg_sel; +wire pdat_read; +wire psta_read; +wire pdat_write; +wire scx_write; +wire scy_write; +wire rw; + +wire coin1 = ~&p2[7:6]; + +wire [7:0] cpu_din = + ds0_read ? dsw : + in1_read ? p1 : + in2_read ? p2 : + ds1_read ? p3 : + rom_cs ? romdata : + pdat_read ? prot_data : + psta_read ? prot_status : + sram_cs ? sram_data : + 8'h0; + + +er_decode u_er_decode( + .cpu_addr ( cpu_ab ), + .sram_cs ( sram_cs ), + .vram_cs ( vram_cs ), + .cram_cs ( cram_cs ), + .rom_cs ( rom_cs ), + .ds0_read ( ds0_read ), + .ds1_read ( ds1_read ), + .in1_read ( in1_read ), + .in2_read ( in2_read ), + .nmi_clear ( nmi_clear ), + .snd_write ( snd_write ), + .flp_write ( flp_write ), + .dma_swap ( dma_swap ), + .bg_sel ( bg_sel ), + .pdat_read ( pdat_read ), + .psta_read ( psta_read ), + .pdat_write ( pdat_write ), + .scx_write ( scx_write ), + .scy_write ( scy_write ) +); + +prot u_prot( + .clk_sys ( clk_sys ), + .wr ( pdat_write ), + .din ( cpu_dout ), + .dout ( prot_data ), + .status ( prot_status ) +); + +mcpu u_mcpu( + .clk_sys ( clk_sys ), + .reset ( reset ), + .pause ( pause ), + .coin1 ( coin1 ), + .nmi_clear ( nmi_clear ), + .vblk ( vb ), + .cpu_din ( cpu_din ), + .cpu_ab ( cpu_ab ), + .cpu_dout ( cpu_dout ), + .rw ( rw ) +); + +mcpu_rom u_mcpu_rom( + .clk_sys ( clk_sys ), + .cpu_ab ( cpu_ab ), + .romdata ( romdata ), + .ioctl_download ( ioctl_download ), + .ioctl_addr ( ioctl_addr ), + .ioctl_dout ( ioctl_dout ), + .ioctl_wr ( ioctl_wr ), + .rom_cs ( cpu_rom_cs ), + .rom_addr ( cpu_rom_addr ), + .rom_data ( cpu_rom_data ) +); + +video u_video( + .reset ( reset ), + .clk_sys ( clk_sys ), + .hb ( hb ), + .vb ( vb ), + .hs ( hs ), + .vs ( vs ), + .ce_pix ( ce_pix ), + .red ( red ), + .green ( green ), + .blue ( blue ), + .cpu_ab ( cpu_ab ), + .cpu_dout ( cpu_dout ), + .rw ( rw ), + .sram_data ( sram_data ), + .map_rom_addr ( map_rom_addr ), + .map_data ( map_data ), + .char_rom_addr ( char_rom_addr ), + .char_data ( char_data ), + .bg_rom_addr ( bg_rom_addr ), + .bg_data1 ( bg_data1 ), + .bg_data2 ( bg_data2 ), + .col_rom_addr ( col_rom_addr ), + .col_data ( col_data ), + .prom_addr ( prom_addr ), + .prom_data ( prom_data ), + .sp_rom_addr ( sp_rom_addr ), + .sp_rom_data1 ( sp_rom_data1 ), + .sp_rom_data2 ( sp_rom_data2 ), + .sp_rom_data3 ( sp_rom_data3 ), + .vram_cs ( vram_cs ), + .sram_cs ( sram_cs ), + .cram_cs ( cram_cs ), + .scx_write ( scx_write ), + .scy_write ( scy_write ), + .bg_sel ( bg_sel ) +); + +vdata u_vdata( + .clk_sys ( clk_sys ), + .map_rom_addr ( map_rom_addr ), + .map_data ( map_data ), + .char_rom_addr ( char_rom_addr ), + .char_data ( char_data ), + .col_rom_addr ( col_rom_addr ), + .col_data ( col_data ), + .prom_addr ( prom_addr ), + .prom_data ( prom_data ), + .bg_rom_addr ( bg_rom_addr ), + .bg_data1 ( bg_data1 ), + .bg_data2 ( bg_data2 ), + .sp_rom_addr ( sp_rom_addr ), + .sp_rom_data1 ( sp_rom_data1 ), + .sp_rom_data2 ( sp_rom_data2 ), + .sp_rom_data3 ( sp_rom_data3 ), + .ioctl_download ( ioctl_download ), + .ioctl_addr ( ioctl_addr ), + .ioctl_dout ( ioctl_dout ), + .ioctl_wr ( ioctl_wr ), + .gfx1_addr ( gfx1_addr ), + .gfx1_data ( gfx1_data ), + .gfx2_addr ( gfx2_addr ), + .gfx2_data ( gfx2_data ), + .gfx3_addr ( gfx3_addr ), + .gfx3_data ( gfx3_data ), + .sp_addr ( sp_addr ), + .sp_data ( sp_data ) +); + +audio audio( + .reset ( reset ), + .clk_sys ( clk_sys ), + .ioctl_download ( ioctl_download ), + .ioctl_addr ( ioctl_addr ), + .ioctl_dout ( ioctl_dout ), + .ioctl_wr ( ioctl_wr ), + .snd_write ( snd_write ), + .mcpu_dout ( cpu_dout ), + .sound_mix ( sound ), + .rom_cs ( audio_rom_cs ), + .rom_addr ( audio_rom_addr ), + .rom_data ( audio_rom_data ) +); + + +endmodule diff --git a/Arcade_MiST/Data East Express Raider/rtl/cpu/CPU16.v b/Arcade_MiST/Data East Express Raider/rtl/cpu/CPU16.v new file mode 100644 index 00000000..00b0a134 --- /dev/null +++ b/Arcade_MiST/Data East Express Raider/rtl/cpu/CPU16.v @@ -0,0 +1,107 @@ + + +// 6502 BUS CONTROLLER + +module CPU16( + input reset, + input clk, + input cen, + input SYNC, + input VB, + input RW, + input [15:0] ABI, // from CPU + output reg [15:0] ABO, // to PCB + input [7:0] CPU_DBI, // from CPU + output reg [7:0] CPU_DBO, // to CPU + input [7:0] DBI, // from PCB + output [7:0] DBO // to PCB +); + +reg read_io0; +reg read_io1; +reg read_dat; +reg [7:0] din; + +reg [15:0] PAB; +wire [15:0] ABN = PAB + 16'd2; + +assign DBO = CPU_DBI; + +wire [7:0] RAM_Q; + +wire ram_en = ABI[15:9] < 2'd3; +ram #(11,8) RAM( + .clk ( clk ), + .addr ( ABI[10:0] ), + .din ( CPU_DBI ), + .q ( RAM_Q ), + .rd_n ( 1'b0 ), + .wr_n ( RW | ~ram_en ), + .ce_n ( ~ram_en ) +); + +always @* begin + ABO = ABI; + + // decode vector addresses + if (ABI[15:4] == 12'hfff) begin + + ABO[15:4] = ABI[15:4]; + ABO[3:0] = ABI[3:0] ^ 4'hd; + + end + +end + +always @(posedge cen) begin + if (cen) begin + + CPU_DBO <= DBI | RAM_Q; + + + if (DBI[0] & DBI[1] & SYNC) begin // illegal + + PAB <= ABI; + + if (DBI == 8'b0110_0111) begin + CPU_DBO <= 8'hA9; // send lda + read_io0 <= 1'b1; + end + + else if (DBI == 8'b0100_1011) begin // 4b + CPU_DBO <= 8'hA9; // send lda + read_io1 <= 1'b1; + end + + else if (DBI == 8'b1000_1111) begin + // ???? write "din" to IO + end + + else begin + CPU_DBO <= 8'hEA; // send nop + read_dat <= 1'b1; + end + + end + + else if (read_io0) begin + CPU_DBO <= 8'd0; // ??? + read_io0 <= 1'b0; + end + + else if (read_io1) begin + CPU_DBO <= { 6'd0, VB, 1'b0 }; + read_io1 <= 1'b0; + end + + if (read_dat) begin + read_dat <= 1'b0; + din <= DBI; + end + + + end +end + + +endmodule diff --git a/Arcade_MiST/Data East Express Raider/rtl/cpu/mcpu.v b/Arcade_MiST/Data East Express Raider/rtl/cpu/mcpu.v new file mode 100644 index 00000000..b4faeb2a --- /dev/null +++ b/Arcade_MiST/Data East Express Raider/rtl/cpu/mcpu.v @@ -0,0 +1,85 @@ + +module mcpu( + input clk_sys, + input reset, + input pause, + input coin1, + input nmi_clear, + input vblk, + output [15:0] cpu_ab, + input [7:0] cpu_din, + output [7:0] cpu_dout, + output rw +); + +wire cen_15; +wire cpu_clk; +clk_en #(31) cpu_clk_en(clk_sys, cen_15, cpu_clk); + +wire coin1_re; +rising_edge rising_edge_coin(clk_sys, coin1, coin1_re); + +reg F13E_Q; +always @(posedge clk_sys) begin + if (coin1_re) F13E_Q <= 1'b1; + if (nmi_clear) F13E_Q <= 1'b0; +end + +wire irq = ~F13E_Q; + +wire [7:0] din, dout; +wire [15:0] addr; +wire sync; + +`ifdef SYNTH + +T65 M6502 ( + .Res_n ( ~reset ), + .Enable ( cen_15 ), + .Rdy ( ~pause ), + .Clk ( clk_sys ), + .IRQ_n ( irq ), + .R_W_n ( rw ), + .A ( addr ), + .DI ( din ), + .DO ( dout ), + .Sync ( sync ) +); + +`else + +wire m6502_we; +assign rw = ~m6502_we; + +cpu6502 M6502( + .clk ( cen_15 ), + .reset ( reset ), + .AB ( addr ), + .DI ( din ), + .DO ( dout ), + .WE ( m6502_we ), + .IRQ ( ~irq ), + .NMI ( 1'b0 ), + .RDY ( 1'b1 ), + .SYNC ( sync ) +); + +`endif + +CPU16 CPU16( + .clk ( clk_sys ), + .cen ( cen_15 ), + .reset ( reset ), + .ABI ( addr ), + .ABO ( cpu_ab ), + .CPU_DBI ( dout ), + .CPU_DBO ( din ), + .DBI ( cpu_din ), + .DBO ( cpu_dout ), + .SYNC ( sync ), + .RW ( rw ), + .VB ( vblk ) +); + + +endmodule diff --git a/Arcade_MiST/Data East Express Raider/rtl/cpu/mcpu_rom.v b/Arcade_MiST/Data East Express Raider/rtl/cpu/mcpu_rom.v new file mode 100644 index 00000000..773bd79a --- /dev/null +++ b/Arcade_MiST/Data East Express Raider/rtl/cpu/mcpu_rom.v @@ -0,0 +1,51 @@ + +module mcpu_rom( + input clk_sys, + input [15:0] cpu_ab, + output [7:0] romdata, + + input ioctl_download, + input [26:0] ioctl_addr, + input [15:0] ioctl_dout, + input ioctl_wr, + + output rom_cs, + output[15:0] rom_addr, + input [7:0] rom_data +); + +assign rom_cs = cpu_ab[15] | cpu_ab[14]; +assign rom_addr = cpu_ab[15:0] - 16'h4000; +`ifdef EXT_ROM +assign romdata = rom_data; +`else +wire [13:0] u16B_addr = ioctl_download ? ioctl_addr : cpu_ab[13:0]; +wire u16B_wr_n = ioctl_download && ioctl_addr < 27'h4000 ? ioctl_wr : 1'b0; +wire [14:0] u16A_addr = ioctl_download ? ioctl_addr - 27'h4000 : cpu_ab[14:0]; +wire u16A_wr_n = ioctl_download && ioctl_addr >= 27'h4000 && ioctl_addr < 27'hc000 ? ioctl_wr : 1'b0; + +wire [7:0] u16A_Q, u16B_Q; +assign romdata = u16A_Q | u16B_Q; + +wire u16B_ce_n = ~(cpu_ab[14] & ~cpu_ab[15]); +ram #(14,8) u16B( + .clk ( clk_sys ), + .addr ( u16B_addr ), + .din ( ioctl_dout ), + .q ( u16B_Q ), + .rd_n ( 1'b0 ), + .wr_n ( ~u16B_wr_n ), + .ce_n ( u16B_ce_n ) +); + +ram #(15,8) u16A( + .clk ( clk_sys ), + .addr ( u16A_addr ), + .din ( ioctl_dout ), + .q ( u16A_Q ), + .rd_n ( 1'b0 ), + .wr_n ( ~u16A_wr_n ), + .ce_n ( ~cpu_ab[15] ) +); +`endif +endmodule diff --git a/Arcade_MiST/Data East Express Raider/rtl/er_decode.v b/Arcade_MiST/Data East Express Raider/rtl/er_decode.v new file mode 100644 index 00000000..6362500a --- /dev/null +++ b/Arcade_MiST/Data East Express Raider/rtl/er_decode.v @@ -0,0 +1,90 @@ + +module er_decode( + input [15:0] cpu_addr, + output reg sram_cs, + output reg vram_cs, + output reg cram_cs, + output reg rom_cs, + output reg ds0_read, + output reg ds1_read, + output reg in1_read, + output reg in2_read, + output reg nmi_clear, + output reg snd_write, + output reg flp_write, + output reg dma_swap, + output reg bg_sel, + output reg pdat_read, + output reg psta_read, + output reg pdat_write, + output reg scx_write, + output reg scy_write +); + +always @* begin + + sram_cs = 0; + vram_cs = 0; + cram_cs = 0; + rom_cs = 0; + ds0_read = 0; + ds1_read = 0; + in1_read = 0; + in2_read = 0; + nmi_clear = 0; + snd_write = 0; + flp_write = 0; + dma_swap = 0; + bg_sel = 0; + pdat_read = 0; + psta_read = 0; + pdat_write = 0; + scx_write = 0; + scy_write = 0; + + case (cpu_addr[15:14]) + 0: begin + case (cpu_addr[13:12]) + 0: begin + case (cpu_addr[11:9]) + 3: sram_cs = 1; + 4, 5: vram_cs = 1; + 6, 7: cram_cs = 1; + endcase + end + 1: begin + case (cpu_addr[1:0]) + 0: ds0_read = 1; + 1: in1_read = 1; + 2: in2_read = 1; + 3: ds1_read = 1; + endcase + end + 2: begin + if (~cpu_addr[11]) begin + case (cpu_addr[1:0]) + 0: nmi_clear = 1; + 1: snd_write = 1; + 2: flp_write = 1; + 3: dma_swap = 1; + endcase + end + else begin + if (~cpu_addr[2]) bg_sel = 1; + case (cpu_addr[2:0]) + 0: pdat_read = 1; + 1: psta_read = 1; + 4: scy_write = 1; + 5, 6: scx_write = 1; + 7: pdat_write = 1; + endcase + end + end + endcase + end + 1, 2, 3: rom_cs = 1; + endcase + +end + +endmodule diff --git a/Arcade_MiST/Data East Express Raider/rtl/mem/dpram.v b/Arcade_MiST/Data East Express Raider/rtl/mem/dpram.v new file mode 100644 index 00000000..e5e87fbc --- /dev/null +++ b/Arcade_MiST/Data East Express Raider/rtl/mem/dpram.v @@ -0,0 +1,137 @@ +// megafunction wizard: %RAM: 2-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: dpram.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 17.0.0 Build 595 04/25/2017 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2017 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel MegaCore Function License Agreement, or other +//applicable license agreement, including, without limitation, +//that your use is for the sole purpose of programming logic +//devices manufactured by Intel and sold by Intel or its +//authorized distributors. Please refer to the applicable +//agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module dpram +#( + parameter ADDRWIDTH=12, + parameter DATAWIDTH=8 +) +( + address_a, + address_b, + clock, + data_a, + data_b, + wren_a, + wren_b, + rden_a, + rden_b, + q_a, + q_b); + + input [ADDRWIDTH-1:0] address_a; + input [ADDRWIDTH-1:0] address_b; + input clock; + input [DATAWIDTH-1:0] data_a; + input [DATAWIDTH-1:0] data_b; + input wren_a; + input wren_b; + input rden_a; + input rden_b; + output [DATAWIDTH-1:0] q_a; + output [DATAWIDTH-1:0] q_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; + tri0 wren_a; + tri0 wren_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [DATAWIDTH-1:0] sub_wire0; + wire [DATAWIDTH-1:0] sub_wire1; + wire [DATAWIDTH-1:0] q_a = rden_a ? sub_wire0[DATAWIDTH-1:0] : {DATAWIDTH{1'b0}}; + wire [DATAWIDTH-1:0] q_b = rden_b ? sub_wire1[DATAWIDTH-1:0] : {DATAWIDTH{1'b0}}; + + altsyncram altsyncram_component ( + .address_a (address_a), + .address_b (address_b), + .clock0 (clock), + .data_a (data_a), + .data_b (data_b), + .wren_a (wren_a), + .wren_b (wren_b), + .q_a (sub_wire0), + .q_b (sub_wire1), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .eccstatus (), + .rden_a (1'b1), + .rden_b (1'b1)); + defparam + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.indata_reg_b = "CLOCK0", + altsyncram_component.intended_device_family = "Cyclone V", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 2**ADDRWIDTH, + altsyncram_component.numwords_b = 2**ADDRWIDTH, + altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.outdata_reg_b = "CLOCK0", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = ADDRWIDTH, + altsyncram_component.widthad_b = ADDRWIDTH, + altsyncram_component.width_a = DATAWIDTH, + altsyncram_component.width_b = DATAWIDTH, + altsyncram_component.width_byteena_a = 1, + altsyncram_component.width_byteena_b = 1, + altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0"; + + +endmodule diff --git a/Arcade_MiST/Data East Express Raider/rtl/mem/ram.v b/Arcade_MiST/Data East Express Raider/rtl/mem/ram.v new file mode 100644 index 00000000..75cc848f --- /dev/null +++ b/Arcade_MiST/Data East Express Raider/rtl/mem/ram.v @@ -0,0 +1,30 @@ + +module ram +#( + parameter addr_width=12, + parameter data_width=8 +) +( + input clk, + input [addr_width-1:0] addr, + input [data_width-1:0] din, + output [data_width-1:0] q, + input rd_n, + input wr_n, + input ce_n +); + +reg [data_width-1:0] data; +reg [data_width-1:0] mem[(1< +// Copyright (c) 2019 Gyorgy Szombathelyi +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +module sdram ( + + // interface to the MT48LC16M16 chip + inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus + output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus + output reg SDRAM_DQML, // two byte masks + output reg SDRAM_DQMH, // two byte masks + output reg [1:0] SDRAM_BA, // two banks + output SDRAM_nCS, // a single chip select + output SDRAM_nWE, // write enable + output SDRAM_nRAS, // row address select + output SDRAM_nCAS, // columns address select + + // cpu/chipset interface + input init_n, // init signal after FPGA config to initialize RAM + input clk, // sdram clock + + input port1_req, + output reg port1_ack, + input port1_we, + input [23:1] port1_a, + input [1:0] port1_ds, + input [15:0] port1_d, + output reg [15:0] port1_q, + + input cpu1_cs, + input [19:1] cpu1_addr, + output reg [15:0] cpu1_q, + input cpu2_cs, + input [19:1] cpu2_addr, + output reg [15:0] cpu2_q, + input [19:1] gfx1_addr, + output reg [15:0] gfx1_q, + input [19:1] gfx2_addr, + output reg [15:0] gfx2_q, + + input port2_req, + output reg port2_ack, + input port2_we, + input [23:1] port2_a, + input [1:0] port2_ds, + input [15:0] port2_d, + output reg [31:0] port2_q, + + input [19:2] gfx3_addr, + output reg [31:0] gfx3_q, + input [19:2] sp_addr, + output reg [31:0] sp_q +); + +parameter MHZ = 16'd80; // 80 MHz default clock, set it to proper value to calculate refresh rate + +localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz +localparam BURST_LENGTH = 3'b001; // 000=1, 001=2, 010=4, 011=8 +localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved +localparam CAS_LATENCY = 3'd2; // 2/3 allowed +localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed +localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write + +localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; + +// 64ms/8192 rows = 7.8us +localparam RFRSH_CYCLES = 16'd78*MHZ/4'd10; + +// --------------------------------------------------------------------- +// ------------------------ cycle state machine ------------------------ +// --------------------------------------------------------------------- +/* + SDRAM state machine for 2 bank interleaved access + 1 word burst, CL2 +cmd issued registered + 0 RAS0 cas1 - data0 read burst terminated + 1 ras0 + 2 data1 returned + 3 CAS0 data1 returned + 4 RAS1 cas0 + 5 ras1 + 6 CAS1 data0 returned +*/ + +localparam STATE_RAS0 = 3'd0; // first state in cycle +localparam STATE_RAS1 = 3'd4; // Second ACTIVE command after RAS0 + tRRD (15ns) +localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3 +localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6 +localparam STATE_READ0 = 3'd0;// STATE_CAS0 + CAS_LATENCY + 2'd2; // 7 +localparam STATE_READ1 = 3'd3; +localparam STATE_DS1b = 3'd0; +localparam STATE_READ1b = 3'd4; +localparam STATE_LAST = 3'd6; + +reg [2:0] t; + +always @(posedge clk) begin + t <= t + 1'd1; + if (t == STATE_LAST) t <= STATE_RAS0; +end + +// --------------------------------------------------------------------- +// --------------------------- startup/reset --------------------------- +// --------------------------------------------------------------------- + +// wait 1ms (32 8Mhz cycles) after FPGA config is done before going +// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0) +reg [4:0] reset; +reg init = 1'b1; +always @(posedge clk, negedge init_n) begin + if(!init_n) begin + reset <= 5'h1f; + init <= 1'b1; + end else begin + if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1; + init <= !(reset == 0); + end +end + +// --------------------------------------------------------------------- +// ------------------ generate ram control signals --------------------- +// --------------------------------------------------------------------- + +// all possible commands +localparam CMD_INHIBIT = 4'b1111; +localparam CMD_NOP = 4'b0111; +localparam CMD_ACTIVE = 4'b0011; +localparam CMD_READ = 4'b0101; +localparam CMD_WRITE = 4'b0100; +localparam CMD_BURST_TERMINATE = 4'b0110; +localparam CMD_PRECHARGE = 4'b0010; +localparam CMD_AUTO_REFRESH = 4'b0001; +localparam CMD_LOAD_MODE = 4'b0000; + +reg [3:0] sd_cmd; // current command sent to sd ram +reg [15:0] sd_din; // Fast Input register latching incoming SDRAM data + +// drive control signals according to current command +assign SDRAM_nCS = sd_cmd[3]; +assign SDRAM_nRAS = sd_cmd[2]; +assign SDRAM_nCAS = sd_cmd[1]; +assign SDRAM_nWE = sd_cmd[0]; + +reg [24:1] addr_latch[2]; +reg [24:1] addr_latch_next[2]; +reg [19:1] addr_last[5]; +reg [19:2] addr_last2[3]; +reg [15:0] din_latch[2]; +reg [1:0] oe_latch; +reg [1:0] we_latch; +reg [1:0] ds[2]; + +reg port1_state; +reg port2_state; + +localparam PORT_NONE = 3'd0; +localparam PORT_CPU1 = 3'd1; +localparam PORT_CPU2 = 3'd2; +localparam PORT_GFX1 = 3'd3; +localparam PORT_GFX2 = 3'd4; +localparam PORT_SP = 3'd1; +localparam PORT_GFX3 = 3'd2; +localparam PORT_REQ = 3'd7; + +reg [2:0] next_port[2]; +reg [2:0] port[2]; + +reg refresh; +reg [11:0] refresh_cnt; +reg need_refresh; + +// PORT1: bank 0,1 +always @(*) begin + if (refresh) begin + next_port[0] = PORT_NONE; + addr_latch_next[0] = addr_latch[1]; + end else if (port1_req ^ port1_state) begin + next_port[0] = PORT_REQ; + addr_latch_next[0] = { 1'b0, port1_a }; + end else if (cpu1_addr != addr_last[PORT_CPU1] && cpu1_cs) begin + next_port[0] = PORT_CPU1; + addr_latch_next[0] = { 5'd0, cpu1_addr }; + end else if (cpu2_addr != addr_last[PORT_CPU2] && cpu2_cs) begin + next_port[0] = PORT_CPU2; + addr_latch_next[0] = { 5'd0, cpu2_addr }; + end else if (gfx1_addr != addr_last[PORT_GFX1]) begin + next_port[0] = PORT_GFX1; + addr_latch_next[0] = { 5'd0, gfx1_addr }; + end else if (gfx2_addr != addr_last[PORT_GFX2]) begin + next_port[0] = PORT_GFX2; + addr_latch_next[0] = { 5'd0, gfx2_addr }; + end else begin + next_port[0] = PORT_NONE; + addr_latch_next[0] = addr_latch[0]; + end +end + +// PORT1: bank 2,3 +always @(*) begin + if (port2_req ^ port2_state) begin + next_port[1] = PORT_REQ; + addr_latch_next[1] = { 1'b1, port2_a }; + end else if (gfx3_addr != addr_last2[PORT_GFX3]) begin + next_port[1] = PORT_GFX3; + addr_latch_next[1] = { 1'b1, 4'd0, gfx3_addr, 1'b0 }; + end else if (sp_addr != addr_last2[PORT_SP]) begin + next_port[1] = PORT_SP; + addr_latch_next[1] = { 1'b1, 4'd0, sp_addr, 1'b0 }; + end else begin + next_port[1] = PORT_NONE; + addr_latch_next[1] = addr_latch[1]; + end +end + +always @(posedge clk) begin + + // permanently latch ram data to reduce delays + sd_din <= SDRAM_DQ; + SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; + { SDRAM_DQMH, SDRAM_DQML } <= 2'b11; + sd_cmd <= CMD_NOP; // default: idle + refresh_cnt <= refresh_cnt + 1'd1; + need_refresh <= (refresh_cnt >= RFRSH_CYCLES); + + if(init) begin + // initialization takes place at the end of the reset phase + if(t == STATE_RAS0) begin + + if(reset == 15) begin + sd_cmd <= CMD_PRECHARGE; + SDRAM_A[10] <= 1'b1; // precharge all banks + end + + if(reset == 10 || reset == 8) begin + sd_cmd <= CMD_AUTO_REFRESH; + end + + if(reset == 2) begin + sd_cmd <= CMD_LOAD_MODE; + SDRAM_A <= MODE; + SDRAM_BA <= 2'b00; + end + end + end else begin + // RAS phase + // bank 0,1 + if(t == STATE_RAS0) begin + addr_latch[0] <= addr_latch_next[0]; + port[0] <= next_port[0]; + { oe_latch[0], we_latch[0] } <= 2'b00; + + if (next_port[0] != PORT_NONE) begin + sd_cmd <= CMD_ACTIVE; + SDRAM_A <= addr_latch_next[0][22:10]; + SDRAM_BA <= addr_latch_next[0][24:23]; + addr_last[next_port[0]] <= addr_latch_next[0][19:1]; + if (next_port[0] == PORT_REQ) begin + { oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we }; + ds[0] <= port1_ds; + din_latch[0] <= port1_d; + port1_state <= port1_req; + end else begin + { oe_latch[0], we_latch[0] } <= 2'b10; + ds[0] <= 2'b11; + end + end + end + + // bank 2,3 + if(t == STATE_RAS1) begin + refresh <= 0; + addr_latch[1] <= addr_latch_next[1]; + { oe_latch[1], we_latch[1] } <= 2'b00; + port[1] <= next_port[1]; + + if (next_port[1] != PORT_NONE) begin + sd_cmd <= CMD_ACTIVE; + SDRAM_A <= addr_latch_next[1][22:10]; + SDRAM_BA <= addr_latch_next[1][24:23]; + addr_last2[next_port[1]] <= addr_latch_next[1][19:2]; + if (next_port[1] == PORT_REQ) begin + { oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we }; + ds[1] <= port2_ds; + din_latch[1] <= port2_d; + port2_state <= port2_req; + end else begin + { oe_latch[1], we_latch[1] } <= 2'b10; + ds[1] <= 2'b11; + end + end else if (need_refresh && !oe_latch[0] & !we_latch[0]) begin + refresh <= 1; + refresh_cnt <= 0; + sd_cmd <= CMD_AUTO_REFRESH; + end + end + + // CAS phase + if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin + sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ; + { SDRAM_DQMH, SDRAM_DQML } <= ~ds[0]; + if (we_latch[0]) begin + SDRAM_DQ <= din_latch[0]; + port1_ack <= port1_req; + end + SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge + SDRAM_BA <= addr_latch[0][24:23]; + end + + if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin + sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ; + { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1]; + if (we_latch[1]) begin + SDRAM_DQ <= din_latch[1]; + port2_ack <= port2_req; + end + SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge + SDRAM_BA <= addr_latch[1][24:23]; + end + + // Data returned + if(t == STATE_READ0 && oe_latch[0]) begin + case(port[0]) + PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end + PORT_CPU1: begin cpu1_q <= sd_din; end + PORT_CPU2: begin cpu2_q <= sd_din; end + PORT_GFX1: begin gfx1_q <= sd_din; end + PORT_GFX2: begin gfx2_q <= sd_din; end + default: ; + endcase; + end + + if(t == STATE_READ1 && oe_latch[1]) begin + case(port[1]) + PORT_REQ: port2_q[15:0] <= sd_din; + PORT_GFX3: gfx3_q[15:0] <= sd_din; + PORT_SP : sp_q[15:0] <= sd_din; + default: ; + endcase; + end + + //set DQM two cycles before the 2nd word in the burst + if(t == STATE_DS1b && oe_latch[1]) { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1]; + + if(t == STATE_READ1b && oe_latch[1]) begin + case(port[1]) + PORT_REQ: begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end + PORT_GFX3: gfx3_q[31:16] <= sd_din; + PORT_SP : sp_q[31:16] <= sd_din; + default: ; + endcase; + end + end +end + +endmodule diff --git a/Arcade_MiST/Data East Express Raider/rtl/tools/clk_en.v b/Arcade_MiST/Data East Express Raider/rtl/tools/clk_en.v new file mode 100644 index 00000000..7766b3b1 --- /dev/null +++ b/Arcade_MiST/Data East Express Raider/rtl/tools/clk_en.v @@ -0,0 +1,27 @@ + +module clk_en #( + parameter DIV=12, + parameter OFFSET=0 +) +( + input ref_clk, + output reg cen, + output reg clk +); + +reg [15:0] cnt = OFFSET; + +always @(posedge ref_clk) begin + if (cnt == DIV) clk <= 1'b1; + if (cnt == (DIV >> 1)) clk <= 1'b0; + if (cnt == DIV) begin + cnt <= 16'd0; + cen <= 1'b1; + end + else begin + cen <= 1'b0; + cnt <= cnt + 16'd1; + end +end + +endmodule diff --git a/Arcade_MiST/Data East Express Raider/rtl/tools/falling_edge.v b/Arcade_MiST/Data East Express Raider/rtl/tools/falling_edge.v new file mode 100644 index 00000000..f3769308 --- /dev/null +++ b/Arcade_MiST/Data East Express Raider/rtl/tools/falling_edge.v @@ -0,0 +1,14 @@ + +module falling_edge( + input clk_sys, + input signal, + output falling +); + +assign falling = old & ~signal ? 1'b1 : 1'b0; + +reg old; +always @(posedge clk_sys) + old <= signal; + +endmodule diff --git a/Arcade_MiST/Data East Express Raider/rtl/tools/rising_edge.v b/Arcade_MiST/Data East Express Raider/rtl/tools/rising_edge.v new file mode 100644 index 00000000..09a361ff --- /dev/null +++ b/Arcade_MiST/Data East Express Raider/rtl/tools/rising_edge.v @@ -0,0 +1,15 @@ + +module rising_edge( + input clk_sys, + input signal, + output rising +); + +assign rising = ~old & signal ? 1'b1 : 1'b0; + +reg old; +always @(posedge clk_sys) + old <= signal; + + +endmodule diff --git a/Arcade_MiST/Data East Express Raider/rtl/video/VSC30.v b/Arcade_MiST/Data East Express Raider/rtl/video/VSC30.v new file mode 100644 index 00000000..9ea2942c --- /dev/null +++ b/Arcade_MiST/Data East Express Raider/rtl/video/VSC30.v @@ -0,0 +1,163 @@ +// DECO VSC30 +// RE and HDL by furrtek 05/2022 +// Chip provided by Caius + +// VNOOOOOOOOOOOOOOOOOO +// |""""""""""""""""""| +// ) DECO VSC30 | +// |__________________| +// IIIIIIIIIINNOOOONIIG + +module VSC30( + input PIN1, // /RESET + + input PIN2, // Shift clock + input PIN3, // Delay in + input PIN4, // Delay in + input PIN5, // Shift in + input PIN6, // Shift in + input PIN7, // Shift grab + input PIN8, // Shift in + input PIN9, // Shift output reverse + input PIN10, // Shift output reverse + + output PIN13, PIN14, PIN15, PIN16, // Shift out + + input PIN18, // V count flip + input PIN19, // V count clock + + output PIN21, PIN22, PIN23, PIN24, PIN25, PIN26, PIN27, PIN28, // V count + + output PIN29, PIN30, PIN31, PIN32, // Shift out + output PIN33, PIN34, PIN35, PIN36, // Shift out + + output reg PIN37, // Delay out + output reg PIN38 // Delay out +); + +wire PIN2_INV = ~PIN2; +wire RES = ~PIN1; + +reg [7:0] SR1; +reg [7:0] SR2; + +reg [3:0] SR3; +reg [3:0] SR4; +reg [3:0] SR5; +always @(posedge PIN2_INV or posedge RES) begin + if (RES) begin + SR1 <= 8'h00; + SR2 <= 8'h00; + SR3 <= 4'h0; + SR4 <= 4'h0; + SR5 <= 4'h0; + end else begin + SR1 <= {SR1[6:0], PIN3}; + SR2 <= {SR2[6:0], PIN4}; + + SR3 <= {SR3[2:0], PIN8}; + SR4 <= {SR4[2:0], PIN5}; + SR5 <= {SR5[2:0], PIN6}; + end +end + +always @(posedge PIN2 or posedge RES) begin + if (RES) begin + PIN38 <= 1'b0; + PIN37 <= 1'b0; + end else begin + PIN38 <= SR1[7]; + PIN37 <= SR2[7]; + end +end + +reg [3:0] SR3_REG; +reg [3:0] SR4_REG; +reg [3:0] SR5_REG; +always @(posedge PIN7 or posedge RES) begin + if (RES) begin + SR3_REG <= 4'h0; + SR4_REG <= 4'h0; + SR5_REG <= 4'h0; + end else begin + SR3_REG <= SR3; + SR4_REG <= SR4; + SR5_REG <= SR5; + end +end + +wire SEL = PIN9 ^ PIN10; + +assign PIN29 = SEL ? SR3_REG[0] : SR3_REG[3]; +assign PIN30 = SEL ? SR3_REG[1] : SR3_REG[2]; +assign PIN31 = SEL ? SR3_REG[2] : SR3_REG[1]; +assign PIN32 = SEL ? SR3_REG[3] : SR3_REG[0]; + +assign PIN13 = SEL ? SR5_REG[3] : SR5_REG[0]; +assign PIN14 = SEL ? SR5_REG[2] : SR5_REG[1]; +assign PIN15 = SEL ? SR5_REG[1] : SR5_REG[2]; +assign PIN16 = SEL ? SR5_REG[0] : SR5_REG[3]; + +assign PIN33 = SEL ? SR4_REG[0] : SR4_REG[3]; +assign PIN34 = SEL ? SR4_REG[1] : SR4_REG[2]; +assign PIN35 = SEL ? SR4_REG[2] : SR4_REG[1]; +assign PIN36 = SEL ? SR4_REG[3] : SR4_REG[0]; + +// Counter +// This can be simplified a lot, see notes on schematic sheet. + +reg [7:0] CNT_REG; +reg L14; + +wire B9 = &{CNT_REG[3:0]}; +wire M5 = ~&{CNT_REG[6:4]}; +wire M8 = ~&{B9, CNT_REG[7]}; +wire M7 = ~|{M5 | M8}; +wire D4 = ~M7; +wire B21 = D4 & PIN1; + +wire D5 = ~|{D4, RES}; +wire D9 = ~|{RES, D5}; + +wire C28 = ~&{~&{~CNT_REG[0], D4}, ~&{~B21, D9, CNT_REG[0]}}; +wire D8 = ~&{~&{CNT_REG[0], B21, ~CNT_REG[1]}, ~&{~&{B21, CNT_REG[0]}, D9, CNT_REG[1]}}; +wire B25 = ~&{~&{B21, CNT_REG[1], CNT_REG[0], ~CNT_REG[2]}, ~&{~&{B21, CNT_REG[0], CNT_REG[1]}, D9, CNT_REG[2]}}; +wire D13 = |{&{D9, ~&{CNT_REG[2:0]}, CNT_REG[3]}, ~|{~&{~CNT_REG[3], B21, CNT_REG[0]}, ~&{CNT_REG[2:1]}}, D5}; + +wire M2 = ~&{CNT_REG[6:5]} | ~&{J15, CNT_REG[4], ~CNT_REG[7]}; + +wire J15 = &{PIN1, D4, B9}; + +wire L9 = ~|{D4, RES}; +wire L12 = ~|{RES, L9}; + +wire N16 = ~&{~&{~CNT_REG[4], J15}, ~&{~J15, L12, CNT_REG[4]}}; +wire R15 = ~&{~&{L9, ~L14}, ~&{~CNT_REG[5], J15, CNT_REG[4]}, ~&{CNT_REG[5], ~&{CNT_REG[4], J15}, L12}}; +wire P23 = ~&{~&{~L14, L9}, ~&{CNT_REG[5:4], J15, ~CNT_REG[6]}, ~&{L12, ~&{J15, CNT_REG[5:4]}, CNT_REG[6]}}; +wire N7 = ~&{~&{L9, ~L14}, M2, ~&{CNT_REG[7], ~&{J15, CNT_REG[6:4]}, L12}}; + +wire PIN19_INV = ~PIN19; + +always @(posedge PIN19_INV or posedge RES) begin + if (RES) begin + CNT_REG <= 8'h08; + L14 <= 1'b0; + end else begin + CNT_REG[0] <= C28; + CNT_REG[1] <= D8; + CNT_REG[2] <= B25; + CNT_REG[3] <= D13; + + CNT_REG[4] <= N16; + CNT_REG[5] <= R15; + CNT_REG[6] <= P23; + CNT_REG[7] <= N7; + + if (M7) + L14 <= ~L14; + end +end + +assign {PIN21, PIN22, PIN23, PIN24, PIN25, PIN26, PIN27, PIN28} = {8{PIN18}} ^ CNT_REG; + +endmodule diff --git a/Arcade_MiST/Data East Express Raider/rtl/video/hvgen.v b/Arcade_MiST/Data East Express Raider/rtl/video/hvgen.v new file mode 100644 index 00000000..9e040574 --- /dev/null +++ b/Arcade_MiST/Data East Express Raider/rtl/video/hvgen.v @@ -0,0 +1,37 @@ + +module hvgen( + input clk_sys, + output reg hb, vb, hs, vs, + output reg [8:0] hcount, vcount, + output ce_pix +); + +wire cen_6; +clk_en #(7) hclk_en(clk_sys, cen_6); +assign ce_pix = cen_6; + +always @(posedge clk_sys) begin + if (cen_6) begin + hcount <= hcount + 9'd1; + case (hcount) + 21: hb <= 1'b0; + 276: hb <= 1'b1; + 308: hs <= 1'b0; + 340: hs <= 1'b1; + 383: begin + vcount <= vcount + 9'd1; + hcount <= 9'b0; + case (vcount) + 8: vb <= 1'b0; + 247: vb <= 1'b1; + 249: vs <= 1'b0; + 252: vs <= 1'b1; + 262: vcount <= 9'd0; + endcase + end + endcase + end +end + + +endmodule diff --git a/Arcade_MiST/Data East Express Raider/rtl/video/vdata.v b/Arcade_MiST/Data East Express Raider/rtl/video/vdata.v new file mode 100644 index 00000000..195b1e53 --- /dev/null +++ b/Arcade_MiST/Data East Express Raider/rtl/video/vdata.v @@ -0,0 +1,304 @@ + +module vdata( + input clk_sys, + input [14:0] map_rom_addr, + output [7:0] map_data, + + input [13:0] char_rom_addr, + output [7:0] char_data, + + input [7:0] col_rom_addr, + output [11:0] col_data, + + input [7:0] prom_addr, + output [7:0] prom_data, + + input [15:0] bg_rom_addr, + output [7:0] bg_data1, + output [7:0] bg_data2, + + input [15:0] sp_rom_addr, + output [7:0] sp_rom_data1, + output [7:0] sp_rom_data2, + output [7:0] sp_rom_data3, + + input ioctl_download, + input [26:0] ioctl_addr, + input [15:0] ioctl_dout, + input ioctl_wr, + + output[14:0] gfx1_addr, + input [7:0] gfx1_data, + output[14:0] gfx2_addr, + input [7:0] gfx2_data, + output[15:0] gfx3_addr, + input [7:0] gfx3_data, + output[15:0] sp_addr, + input [31:0] sp_data +); + +// color ROMs + +wire [3:0] uc5B_q; +wire [3:0] uc6B_q; +wire [3:0] uc7B_q; +wire [3:0] uc9B_q; + +assign col_data = { uc5B_q, uc6B_q, uc7B_q }; +assign prom_data = uc9B_q; + +wire [7:0] uc5B_addr = ioctl_download ? ioctl_addr - 27'h78000 : col_rom_addr; +wire uc5B_wr_n = ioctl_download && ioctl_addr >= 27'h78000 && ioctl_addr < 27'h78100 ? ioctl_wr : 1'b0; +wire [7:0] uc6B_addr = ioctl_download ? ioctl_addr - 27'h78100 : col_rom_addr; +wire uc6B_wr_n = ioctl_download && ioctl_addr >= 27'h78100 && ioctl_addr < 27'h78200 ? ioctl_wr : 1'b0; +wire [7:0] uc7B_addr = ioctl_download ? ioctl_addr - 27'h78200 : col_rom_addr; +wire uc7B_wr_n = ioctl_download && ioctl_addr >= 27'h78200 && ioctl_addr < 27'h78300 ? ioctl_wr : 1'b0; +wire [7:0] uc9B_addr = ioctl_download ? ioctl_addr - 27'h78300 : prom_addr; +wire uc9B_wr_n = ioctl_download && ioctl_addr >= 27'h78300 && ioctl_addr < 27'h78400 ? ioctl_wr : 1'b0; + +ram #(8,8) uc5B( + .clk ( clk_sys ), + .addr ( uc5B_addr ), + .din ( ioctl_dout ), + .q ( uc5B_q ), + .rd_n ( 1'b0 ), + .wr_n ( ~uc5B_wr_n ), + .ce_n ( 1'b0 ) +); + +ram #(8,8) uc6B( + .clk ( clk_sys ), + .addr ( uc6B_addr ), + .din ( ioctl_dout ), + .q ( uc6B_q ), + .rd_n ( 1'b0 ), + .wr_n ( ~uc6B_wr_n ), + .ce_n ( 1'b0 ) +); + +ram #(8,8) uc7B( + .clk ( clk_sys ), + .addr ( uc7B_addr ), + .din ( ioctl_dout ), + .q ( uc7B_q ), + .rd_n ( 1'b0 ), + .wr_n ( ~uc7B_wr_n ), + .ce_n ( 1'b0 ) +); + +ram #(8,8) uc9B( + .clk ( clk_sys ), + .addr ( uc9B_addr ), + .din ( ioctl_dout ), + .q ( uc9B_q ), + .rd_n ( 1'b0 ), + .wr_n ( ~uc9B_wr_n ), + .ce_n ( 1'b0 ) +); + + + +// char ROM + +wire [7:0] u5B_q; + +wire [13:0] u5B_addr = ioctl_download ? ioctl_addr - 27'h14000 : char_rom_addr; +wire u5B_wr_n = ioctl_download && ioctl_addr >= 27'h14000 && ioctl_addr < 27'h18000 ? ioctl_wr : 1'b0; + +assign char_data = u5B_q; + +ram #(14,8) u5B( + .clk ( clk_sys ), + .addr ( u5B_addr ), + .din ( ioctl_dout ), + .q ( u5B_q ), + .rd_n ( 1'b0 ), + .wr_n ( ~u5B_wr_n ), + .ce_n ( 1'b0 ) +); + +// tilemap ROM + +`ifdef EXT_ROM +assign gfx1_addr = map_rom_addr; +assign map_data = gfx1_data; +`else +wire [7:0] u12F_q; + +assign map_data = u12F_q; +wire [14:0] u12F_addr = ioctl_download ? ioctl_addr - 27'h60000 : map_rom_addr; +wire u12F_wr_n = ioctl_download && ioctl_addr >= 27'h60000 && ioctl_addr < 27'h68000 ? ioctl_wr : 1'b0; + +ram #(15,8) u12F( + .clk ( clk_sys ), + .addr ( u12F_addr ), + .din ( ioctl_dout ), + .q ( u12F_q ), + .rd_n ( 1'b0 ), + .wr_n ( ~u12F_wr_n ), + .ce_n ( 1'b0 ) +); +`endif + +// background tiles ROMs + +wire [7:0] u8E_q; +wire [7:0] u8F_q; +wire [7:0] u8H_q; + +// remove bit 12 (BGCA 7) +wire [14:0] bg_rom_addr_u8E = { bg_rom_addr[15:13], bg_rom_addr[11:0] }; + +`ifdef EXT_ROM +assign gfx2_addr = bg_rom_addr_u8E; +assign bg_data2 = gfx2_data; +assign gfx3_addr = bg_rom_addr; +assign bg_data1 = gfx3_data; +`else +wire [14:0] u8E_addr = ioctl_download ? ioctl_addr - 27'h48000 : bg_rom_addr_u8E; +wire u8E_wr_n = ioctl_download && ioctl_addr >= 27'h48000 && ioctl_addr < 27'h50000 ? ioctl_wr : 1'b0; +wire [14:0] u8F_addr = ioctl_download ? ioctl_addr - 27'h50000 : bg_rom_addr[14:0]; +wire u8F_wr_n = ioctl_download && ioctl_addr >= 27'h50000 && ioctl_addr < 27'h58000 ? ioctl_wr : 1'b0; +wire [14:0] u8H_addr = ioctl_download ? ioctl_addr - 27'h58000 : bg_rom_addr[14:0]; +wire u8H_wr_n = ioctl_download && ioctl_addr >= 27'h58000 && ioctl_addr < 27'h60000 ? ioctl_wr : 1'b0; + +assign bg_data1 = u8F_q | u8H_q; +assign bg_data2 = u8E_q; + +wire u8F_ce = ~bg_rom_addr[15]; +wire u8H_ce = bg_rom_addr[15]; + +ram #(15,8) u8E( + .clk ( clk_sys ), + .addr ( u8E_addr ), + .din ( ioctl_dout ), + .q ( u8E_q ), + .rd_n ( 1'b0 ), + .wr_n ( ~u8E_wr_n ), + .ce_n ( 1'b0 ) +); + +ram #(15,8) u8F( + .clk ( clk_sys ), + .addr ( u8F_addr ), + .din ( ioctl_dout ), + .q ( u8F_q ), + .rd_n ( 1'b0 ), + .wr_n ( ~u8F_wr_n ), + .ce_n ( ~u8F_ce ) +); + +ram #(15,8) u8H( + .clk ( clk_sys ), + .addr ( u8H_addr ), + .din ( ioctl_dout ), + .q ( u8H_q ), + .rd_n ( 1'b0 ), + .wr_n ( ~u8H_wr_n ), + .ce_n ( ~u8H_ce ) +); +`endif + +// sprite ROMs + +assign sp_addr = sp_rom_addr[15:0]; + +`ifdef EXT_ROM + +assign sp_rom_data1 = sp_data[ 7: 0]; +assign sp_rom_data2 = sp_data[15: 8]; +assign sp_rom_data3 = sp_data[23:16]; + +`else + +wire [14:0] u16H_addr = ioctl_download ? ioctl_addr - 27'h18000 : sp_rom_addr[14:0]; +wire u16H_wr_n = ioctl_download && ioctl_addr >= 27'h18000 && ioctl_addr < 27'h20000 ? ioctl_wr : 1'b0; +wire [14:0] u14H_addr = ioctl_download ? ioctl_addr - 27'h20000 : sp_rom_addr[14:0]; +wire u14H_wr_n = ioctl_download && ioctl_addr >= 27'h20000 && ioctl_addr < 27'h28000 ? ioctl_wr : 1'b0; +wire [14:0] u16K_addr = ioctl_download ? ioctl_addr - 27'h28000 : sp_rom_addr[14:0]; +wire u16K_wr_n = ioctl_download && ioctl_addr >= 27'h28000 && ioctl_addr < 27'h30000 ? ioctl_wr : 1'b0; +wire [14:0] u14K_addr = ioctl_download ? ioctl_addr - 27'h30000 : sp_rom_addr[14:0]; +wire u14K_wr_n = ioctl_download && ioctl_addr >= 27'h30000 && ioctl_addr < 27'h38000 ? ioctl_wr : 1'b0; +wire [14:0] u13K_addr = ioctl_download ? ioctl_addr - 27'h38000 : sp_rom_addr[14:0]; +wire u13K_wr_n = ioctl_download && ioctl_addr >= 27'h38000 && ioctl_addr < 27'h40000 ? ioctl_wr : 1'b0; +wire [14:0] u11K_addr = ioctl_download ? ioctl_addr - 27'h40000 : sp_rom_addr[14:0]; +wire u11K_wr_n = ioctl_download && ioctl_addr >= 27'h40000 && ioctl_addr < 27'h48000 ? ioctl_wr : 1'b0; + +wire [7:0] u16H_q; +wire [7:0] u14H_q; +wire [7:0] u16K_q; +wire [7:0] u14K_q; +wire [7:0] u13K_q; +wire [7:0] u11K_q; + +wire sroml_ce = ~sp_rom_addr[15]; +wire sromh_ce = sp_rom_addr[15]; + +assign sp_rom_data1 = sroml_ce ? u16H_q : u14H_q; +assign sp_rom_data2 = sroml_ce ? u16K_q : u14K_q; +assign sp_rom_data3 = sroml_ce ? u13K_q : u11K_q; + +ram #(15,8) u16H( + .clk ( clk_sys ), + .addr ( u16H_addr ), + .din ( ioctl_dout ), + .q ( u16H_q ), + .rd_n ( 1'b0 ), + .wr_n ( ~u16H_wr_n ), + .ce_n ( ~sroml_ce ) +); + +ram #(15,8) u14H( + .clk ( clk_sys ), + .addr ( u14H_addr ), + .din ( ioctl_dout ), + .q ( u14H_q ), + .rd_n ( 1'b0 ), + .wr_n ( ~u14H_wr_n ), + .ce_n ( ~sromh_ce ) +); + +ram #(15,8) u16K( + .clk ( clk_sys ), + .addr ( u16K_addr ), + .din ( ioctl_dout ), + .q ( u16K_q ), + .rd_n ( 1'b0 ), + .wr_n ( ~u16K_wr_n ), + .ce_n ( ~sroml_ce ) +); + +ram #(15,8) u14K( + .clk ( clk_sys ), + .addr ( u14K_addr ), + .din ( ioctl_dout ), + .q ( u14K_q ), + .rd_n ( 1'b0 ), + .wr_n ( ~u14K_wr_n ), + .ce_n ( ~sromh_ce ) +); + +ram #(15,8) u13K( + .clk ( clk_sys ), + .addr ( u13K_addr ), + .din ( ioctl_dout ), + .q ( u13K_q ), + .rd_n ( 1'b0 ), + .wr_n ( ~u13K_wr_n ), + .ce_n ( ~sroml_ce ) +); + +ram #(15,8) u11K( + .clk ( clk_sys ), + .addr ( u11K_addr ), + .din ( ioctl_dout ), + .q ( u11K_q ), + .rd_n ( 1'b0 ), + .wr_n ( ~u11K_wr_n ), + .ce_n ( ~sromh_ce ) +); + +`endif + +endmodule + diff --git a/Arcade_MiST/Data East Express Raider/rtl/video/video.v b/Arcade_MiST/Data East Express Raider/rtl/video/video.v new file mode 100644 index 00000000..b0bf8ab0 --- /dev/null +++ b/Arcade_MiST/Data East Express Raider/rtl/video/video.v @@ -0,0 +1,347 @@ + +module video( + input reset, + input clk_sys, + output hb, vb, hs, vs, + output ce_pix, + + output reg [3:0] red, + output reg [3:0] green, + output reg [3:0] blue, + + input [15:0] cpu_ab, + input [7:0] cpu_dout, + input rw, + + output reg [7:0] sram_data, + + output [14:0] map_rom_addr, + input [7:0] map_data, + + output [13:0] char_rom_addr, + input [7:0] char_data, + + output reg [7:0] col_rom_addr, + input [11:0] col_data, + + output [7:0] prom_addr, + input [7:0] prom_data, + + output [15:0] bg_rom_addr, + input [7:0] bg_data1, + input [7:0] bg_data2, + + output reg [15:0] sp_rom_addr, + input [7:0] sp_rom_data1, + input [7:0] sp_rom_data2, + input [7:0] sp_rom_data3, + + input vram_cs, + input sram_cs, + input cram_cs, + input scx_write, + input scy_write, + input bg_sel +); + +wire [8:0] hcount; +wire [8:0] vcount; +wire [7:0] vram_q; +wire [7:0] cram_q; +wire [7:0] sram1_q; +wire [7:0] sram2_q; +wire [7:0] sram3_q; +wire [7:0] sram4_q; +wire [7:0] sram1_dout; +wire [7:0] sram2_dout; +wire [7:0] sram3_dout; +wire [7:0] sram4_dout; + +reg [7:0] scx1; // 10C +reg [7:0] scx2; // 11C +reg [7:0] scy; +wire [8:0] sv = vcount + scy; +wire [8:0] sh = hcount + (sv[8] ? scx2 : scx1) - 4'd5; +wire[11:0] vram_addr; +reg [6:0] sram_addr; +reg [5:0] bg_reg[3:0]; + +// TODO: replace vertical counter with VSC30 from Furrtek! + +hvgen u_hvgen( + .clk_sys ( clk_sys ), + .hb ( hb ), + .vb ( vb ), + .hs ( hs ), + .vs ( vs ), + .hcount ( hcount ), + .vcount ( vcount ), + .ce_pix ( ce_pix ) +); + +// VRAM (FG) + +wire u8C_en = vram_cs | cram_cs; +wire vram_wr = u8C_en & ~rw; + +dpram #(12,8) u8C( + .clock ( clk_sys ), + .address_a ( cpu_ab[11:0] ), + .data_a ( cpu_dout ), + .wren_a ( vram_wr ), + .address_b ( vram_addr ), + .rden_b ( 1'b1 ), + .q_b ( vram_q ) +); + +// SRAM + +wire sram_wr = sram_cs & ~rw; +wire sram1_en = cpu_ab[1:0] == 2'b00; +wire sram2_en = cpu_ab[1:0] == 2'b01; +wire sram3_en = cpu_ab[1:0] == 2'b10; +wire sram4_en = cpu_ab[1:0] == 2'b11; + +// must be synced to cpu clock if chip_6502 is used +// a typical symptom is the horse with static legs +always @(posedge clk_sys) + if (rw) + sram_data <= + sram1_en ? sram1_dout : + sram2_en ? sram2_dout : + sram3_en ? sram3_dout : + sram4_en ? sram4_dout : 8'hff; + +dpram #(7,8) sram1( + .clock ( ~clk_sys ), + .address_a ( cpu_ab[8:2] ), + .data_a ( cpu_dout ), + .q_a ( sram1_dout ), + .rden_a ( 1'b1 ), + .wren_a ( sram_wr & sram1_en ), + .address_b ( sram_addr ), + .rden_b ( 1'b1 ), + .q_b ( sram1_q ) +); + +dpram #(7,8) sram2( + .clock ( ~clk_sys ), + .address_a ( cpu_ab[8:2] ), + .data_a ( cpu_dout ), + .q_a ( sram2_dout ), + .rden_a ( 1'b1 ), + .wren_a ( sram_wr & sram2_en ), + .address_b ( sram_addr ), + .rden_b ( 1'b1 ), + .q_b ( sram2_q ) +); + +dpram #(7,8) sram3( + .clock ( ~clk_sys ), + .address_a ( cpu_ab[8:2] ), + .data_a ( cpu_dout ), + .q_a ( sram3_dout ), + .rden_a ( 1'b1 ), + .wren_a ( sram_wr & sram3_en ), + .address_b ( sram_addr ), + .rden_b ( 1'b1 ), + .q_b ( sram3_q ) +); + +dpram #(7,8) sram4( + .clock ( ~clk_sys ), + .address_a ( cpu_ab[8:2] ), + .data_a ( cpu_dout ), + .q_a ( sram4_dout ), + .rden_a ( 1'b1 ), + .wren_a ( sram_wr & sram4_en ), + .address_b ( sram_addr ), + .rden_b ( 1'b1 ), + .q_b ( sram4_q ) +); + + +// registers +always @(posedge clk_sys) begin + + // four 74374 - L:8C R:7C L:6C R:5C + if (bg_sel & ~rw) bg_reg[cpu_ab[1:0]] <= cpu_dout[5:0]; + + if (scy_write & ~rw) scy <= cpu_dout; + if (scx_write & ~rw) begin + if (cpu_ab[0]) + scx1 <= cpu_dout; + else + scx2 <= cpu_dout; + end + +end + +// background + +reg [7:0] bg_data1_l; +reg [3:0] bg_data2_l; +wire[4:0] bg; +reg [4:0] u9J; +reg [7:0] bg_attr; +reg [9:0] bcga; +wire [1:0] dinv = {2{~u9J[2]}}; + +assign map_rom_addr = { ~sh[2], bg_reg[{ sv[8], sh[8] }], sv[7:4], sh[7:4] }; +assign bg_rom_addr = { bcga[9:8], sh[2], bcga[7:0], ~sh[3], sv[3:0] }; + +assign bg = {u9J[1:0], + bg_data2_l[dinv^sh[1:0]], + bg_data1_l[4+(dinv^sh[1:0])], + bg_data1_l[dinv^sh[1:0]] + }; + +always @(posedge clk_sys) begin + + if (ce_pix) begin + if (sh[2:0] == 3'b111) bcga <= { bg_attr[1:0], map_data }; + if (sh[2:0] == 3'b011) bg_attr <= map_data; // u10J + if (sh[3:0] == 4'b1011) u9J <= { bg_attr[7], bg_attr[2], bg_attr[4:3] }; + if (sh[1:0] == 2'b11) begin // BALD + bg_data1_l <= bg_data1; // u6J + u?? + bg_data2_l <= bcga[7] ? bg_data2[7:4] : bg_data2[3:0]; // u4H + end + end +end + +// foreground + +wire [2:0] fg; +reg [7:0] cdata; +reg [7:0] char_data_l; +reg [9:0] mapad, mapad2; + +assign vram_addr = { 1'b1, hcount[2], vcount[7:3], hcount[7:3] }; +assign char_rom_addr = { hcount[2], mapad[9:8], mapad2[7:0], vcount[2:0] }; +assign fg = { + cdata[4], + char_data_l[4+(2'b11^hcount[1:0])], + char_data_l[2'b11^hcount[1:0]] + }; + +always @(posedge clk_sys) begin + + if (ce_pix) begin + if (hcount[2:0] == 3'b111) cdata <= vram_q; + if (hcount[2:0] == 3'b011) begin + mapad <= { cdata[1:0], vram_q }; + mapad2 <= mapad; + end + if (hcount[1:0] == 2'b11) begin + char_data_l <= char_data; + end + end + +end + +// sprites + +// 4 bytes +// y, attr, x, id +// attr: +// ***..... = code high +// ...*.... = sprite group 16x32 (code and code+1) +// ....*.** = color +// .....*.. = hflip + +reg [2:0] state; +reg [2:0] next_state; +reg [5:0] linebuffer[511:0]; +reg [3:0] sxc; +wire flip = ~sram2_q[2]; +wire [7:0] sxc2 = (8'd240-sram3_q)+sxc; +wire [4:0] syc = vcount - sram1_q; +wire [7:0] id = sram4_q + syc[4]; +wire [15:0] spra = { sram2_q[7:5], id, sxc[3]^flip, syc[3:0] }; +wire spc2 = sp_rom_data3[sxc[2:0]^{3{flip}}]; +wire spc1 = sp_rom_data2[sxc[2:0]^{3{flip}}]; +wire spc0 = sp_rom_data1[sxc[2:0]^{3{flip}}]; + + +always @(posedge clk_sys) begin + + if (reset) begin + state <= 0; + end + else begin + + case (state) + 0: begin + sram_addr <= 0; + next_state <= 1; + if (hcount == 0) state <= 7; + end + 1: begin + if (vcount >= sram1_q && vcount < sram1_q + (sram2_q[4] ? 32 : 16)) begin + sxc <= 0; + sp_rom_addr <= { sram2_q[7:5], id, flip, syc[3:0] }; + next_state <= 2; + state <= 3;//7; + end + else begin + sram_addr <= sram_addr + 7'd1; + next_state <= 1; + state <= sram_addr == 7'd127 ? 0 : 7; + end + end + 2: begin + + if (spc2|spc1|spc0) begin + linebuffer[{ vcount[0], sxc2[7:0] }] <= { sram2_q[3], sram2_q[1:0], spc2, spc1, spc0 }; + end + sxc <= sxc + 4'd1; + if (sxc == 4'd7) begin + sp_rom_addr <= { sram2_q[7:5], id, ~flip, syc[3:0] }; + next_state <= 2; + state <= 3;//7; + end + else if (sxc == 4'd15) begin + sram_addr <= sram_addr + 7'd1; + next_state <= sram_addr == 7'd127 ? 0 : 1; + state <= 7; + end + else begin + state <= 2; + end + end + 3: if (ce_pix) state <= 4; + 4: if (ce_pix) state <= 5; + 5: if (ce_pix) state <= 6; + 6: if (ce_pix) state <= 7; + 7: state <= next_state; + default: state <= 0; + endcase + + end + +end + + +// color mux & priority + +reg [5:0] sp; +reg [2:0] fgl; +wire[8:0] sp_hcount = hcount - 5'd18; +assign prom_addr = { |fgl[1:0], u9J[3], sp[2:0], bg[2:0] }; +always @(posedge clk_sys) begin + sp <= linebuffer[{ ~vcount[0], sp_hcount[7:0] }]; + if (ce_pix) begin + if (!sp_hcount[8]) linebuffer[{ ~vcount[0], sp_hcount[7:0] }] <= 6'd0; + + fgl <= fg; + case (prom_data[1:0]) + 2'b10: col_rom_addr <= { prom_data[1:0], 3'b0, fgl }; + 2'b01: col_rom_addr <= { prom_data[1:0], sp }; + 2'b00: col_rom_addr <= { prom_data[1:0], 1'b0, bg[4:0] }; + endcase + + { red , green, blue } <= col_data; + end +end + +endmodule