set_global_assignment -name VHDL_FILE    [file join $::quartus(qip_path) mist.vhd]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) user_io.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) data_io.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) mist_video.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) rgb2ypbpr.sv]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) cofi.sv]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sdram.sv]
--set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) dpram.vhd]
--set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) spram.vhd]
--set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) sprom.vhd]
--set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) dac.vhd]