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26 lines
566 B
Verilog
26 lines
566 B
Verilog
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module mcpu_rom1(
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input clk_sys,
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output [7:0] rom_data,
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input [15:0] cpu_ab,
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input ioctl_download,
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input [26:0] ioctl_addr,
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input [15:0] ioctl_dout,
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input ioctl_wr
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);
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wire [13:0] rom_addr = ioctl_download ? ioctl_addr[13:0] : cpu_ab[13:0];
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wire rom_wr = ioctl_download && ioctl_addr < 27'h4000 ? ioctl_wr : 1'b0;
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ram #(14,8) rom(
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.clk ( clk_sys ),
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.addr ( rom_addr ),
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.din ( ioctl_dout ),
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.q ( rom_data ),
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.rd_n ( 1'b0 ),
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.wr_n ( ~rom_wr ),
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.ce_n ( 1'b0 )
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);
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endmodule
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