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30 lines
1.1 KiB
VHDL
30 lines
1.1 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity ProgSRam is
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port
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(
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address : in std_logic_vector(15 downto 0);
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n_write : in std_logic; -- inverted write
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n_enable : in std_logic; -- inverted enable for read or write
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data : in std_logic_vector(7 downto 0); -- input to RAM (for write)
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q : out std_logic_vector(7 downto 0); -- output from RAM (for read)
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-- external SRAM interface
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sram_lbl, sram_ubl, sram_wel: out std_logic; -- inverted logic signals
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sram_a : out std_logic_vector(18 downto 0);
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sram_d : inout std_logic_vector(15 downto 0)
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);
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end ProgSRam;
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architecture struct of ProgSRam is
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begin
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-- this module will address lower 64K, set 3 high address bits to 0
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sram_a <= "000" & address;
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sram_ubl <= '1'; -- upper 8 bits disabled
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sram_lbl <= n_enable; -- lower 8 bits to enable signal
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sram_wel <= n_write; -- write signal
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sram_d(15 downto 8) <= (others => 'Z'); -- upper bits high impedance
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sram_d(7 downto 0) <= data when n_write='0' else (others => 'Z');
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q <= sram_d(7 downto 0);
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end struct;
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