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https://github.com/Gehstock/Mist_FPGA.git
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105 lines
3.8 KiB
VHDL
105 lines
3.8 KiB
VHDL
-- Copyright (c) 2015, $ME
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-- All rights reserved.
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--
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-- Redistribution and use in source and synthezised forms, with or without modification, are permitted
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-- provided that the following conditions are met:
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--
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-- 1. Redistributions of source code must retain the above copyright notice, this list of conditions
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-- and the following disclaimer.
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--
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-- 2. Redistributions in synthezised form must reproduce the above copyright notice, this list of conditions
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-- and the following disclaimer in the documentation and/or other materials provided with the distribution.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
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-- WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- spi interface
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity spi is
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port (
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clk : in std_logic;
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cs_n : in std_logic; -- negative
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wr_n : in std_logic; -- negative
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addr : in std_logic_vector(1 downto 0);
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dIn : in std_logic_vector(7 downto 0);
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dOut : out std_logic_vector(7 downto 0);
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spi_cs : out std_logic;
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spi_clk : out std_logic;
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spi_miso : in std_logic;
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spi_mosi : out std_logic
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);
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end;
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architecture rtl of spi is
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signal shift_reg : std_logic_vector(8 downto 0);
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signal divider : integer range 0 to 255 := 0;
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signal divider_reg : integer range 0 to 255;
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signal cs_reg : std_logic;
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signal bit_count : integer range 0 to 8 := 0;
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signal spi_clk_int : std_logic := '0';
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begin
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spi_cs <= cs_reg;
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spi_clk <= spi_clk_int;
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-- read data-in or number of bits left
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dOut <= shift_reg(8 downto 1) when addr(0)='0' else std_logic_vector(to_unsigned(bit_count,dOut'length));
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process
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begin
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wait until rising_edge(clk);
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if (bit_count > 0) then -- transmit data
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spi_mosi <= shift_reg(8);
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if (divider=0) then -- prescaler 0? then shift bit out
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divider <= divider_reg;
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if (spi_clk_int='1') then -- H --> L
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shift_reg <= shift_reg(7 downto 0) & '0';
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bit_count <= bit_count - 1;
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else -- L --> H
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shift_reg(0) <= spi_miso;
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end if;
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spi_clk_int <= not spi_clk_int;
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else
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divider <= divider-1;
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end if;
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else
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divider <= divider_reg;
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end if;
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if (cs_n='0' and wr_n='0') then
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case addr is
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when "00" => -- data-reg
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if (bit_count=0) then
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shift_reg <= dIn & '0';
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bit_count <= 8; -- start transmitting
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end if;
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when "10" => -- cs
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cs_reg <= dIn(0);
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when "11" => -- divider
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divider_reg <= to_integer(unsigned(dIn));
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when others => null; -- "01" -> busy-flag (read only)
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end case;
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end if;
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end process;
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end;
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