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52 lines
1.2 KiB
Verilog
52 lines
1.2 KiB
Verilog
// NeoGeo logic definition
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// Copyright (C) 2018 Sean Gonsalves
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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// Z80 CPU plug into TV80 core
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module cpu_z80(
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input CLK_4M,
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input nRESET,
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input [7:0] SDD_IN,
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output [7:0] SDD_OUT,
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output [15:0] SDA,
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output reg nIORQ,
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output nMREQ,
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output reg nRD, nWR,
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input nINT, nNMI, nWAIT
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);
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wire RFSH_n, MREQ_n;
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assign nMREQ = MREQ_n | ~RFSH_n;
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T80s cpu(
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.RESET_n(nRESET),
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.CLK(CLK_4M),
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.CEN(1),
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.WAIT_n(nWAIT),
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.INT_n(nINT),
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.NMI_n(nNMI),
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.MREQ_n(MREQ_n),
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.IORQ_n(nIORQ),
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.RD_n(nRD),
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.WR_n(nWR),
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.RFSH_n(RFSH_n),
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.A(SDA),
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.DI(SDD_IN),
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.DO(SDD_OUT)
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);
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endmodule
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