mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-03-02 01:30:39 +00:00
153 lines
4.4 KiB
Verilog
153 lines
4.4 KiB
Verilog
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module i8088
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(
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input CORE_CLK,
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input CLK,
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input RESET,
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input READY,
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input INTR,
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input NMI,
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output reg [19:0] addr,
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output reg [7:0] dout,
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input [7:0] din,
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output ALE,
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output INTA_n,
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output RD_n,
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output WR_n,
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output IOM,
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output DTR,
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output DEN
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// output SSO_n
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);
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//------------------------------------------------------------------------
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// Internal Signals
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reg t_biu_lock_n_d;
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wire t_eu_prefix_lock;
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wire t_eu_flag_i;
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wire t_biu_lock_n;
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wire t_pfq_empty;
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wire t_biu_done;
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wire t_biu_clk_counter_zero;
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wire t_biu_ad_oe;
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wire t_biu_nmi_caught;
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wire t_biu_nmi_debounce;
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wire t_sram_d_oe;
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wire t_biu_intr;
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wire [19:0] t_biu_ad_out;
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wire [7:0] t_biu_ad_in;
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wire [2:0] t_s2_s0_out;
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wire [15:0] t_eu_biu_command;
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wire [15:0] t_eu_biu_dataout;
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wire [15:0] t_eu_register_r3;
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wire [7:0] t_pfq_top_byte;
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wire [15:0] t_pfq_addr_out;
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wire [15:0] t_biu_register_es;
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wire [15:0] t_biu_register_ss;
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wire [15:0] t_biu_register_cs;
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wire [15:0] t_biu_register_ds;
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wire [15:0] t_biu_register_rm;
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wire [15:0] t_biu_register_reg;
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wire [15:0] t_biu_return_data;
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always @(posedge CORE_CLK) begin
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if (ALE == 1'b0)
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dout <= t_biu_ad_out[7:0];
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else
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addr <= t_biu_ad_out;
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end
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//------------------------------------------------------------------------
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// BIU Core
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//------------------------------------------------------------------------
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biu_min BIU_CORE
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(
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.CORE_CLK_INT (CORE_CLK),
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.RESET_INT (RESET),
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.CLK (CLK),
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.READY_IN (READY),
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.NMI (NMI),
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.INTR (INTR),
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.INTA_n (INTA_n),
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.ALE (ALE),
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.RD_n (RD_n),
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.WR_n (WR_n),
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.IOM (IOM),
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.DTR (DTR),
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.DEN (DEN),
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.AD_OE (t_biu_ad_oe),
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.AD_OUT (t_biu_ad_out),
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.AD_IN (din),
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.EU_BIU_COMMAND (t_eu_biu_command),
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.EU_BIU_DATAOUT (t_eu_biu_dataout),
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.EU_REGISTER_R3 (t_eu_register_r3),
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.EU_PREFIX_LOCK (t_eu_prefix_lock),
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.BIU_DONE (t_biu_done),
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.BIU_CLK_COUNTER_ZERO (t_biu_clk_counter_zero),
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.BIU_SEGMENT ( ),
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.BIU_NMI_CAUGHT (t_biu_nmi_caught),
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.BIU_NMI_DEBOUNCE (t_biu_nmi_debounce),
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.BIU_INTR (t_biu_intr),
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.PFQ_TOP_BYTE (t_pfq_top_byte),
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.PFQ_EMPTY (t_pfq_empty),
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.PFQ_ADDR_OUT (t_pfq_addr_out),
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.BIU_REGISTER_ES (t_biu_register_es),
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.BIU_REGISTER_SS (t_biu_register_ss),
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.BIU_REGISTER_CS (t_biu_register_cs),
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.BIU_REGISTER_DS (t_biu_register_ds),
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.BIU_REGISTER_RM (t_biu_register_rm),
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.BIU_REGISTER_REG (t_biu_register_reg),
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.BIU_RETURN_DATA (t_biu_return_data)
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);
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//------------------------------------------------------------------------
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// EU Core
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//------------------------------------------------------------------------
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mcl86_eu_core EU_CORE
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(
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.CORE_CLK_INT (CORE_CLK),
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.RESET_INT (RESET),
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.TEST_N_INT (1'b1),
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.EU_BIU_COMMAND (t_eu_biu_command),
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.EU_BIU_DATAOUT (t_eu_biu_dataout),
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.EU_REGISTER_R3 (t_eu_register_r3),
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.EU_PREFIX_LOCK (t_eu_prefix_lock),
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.EU_FLAG_I (t_eu_flag_i),
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.BIU_DONE (t_biu_done),
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.BIU_CLK_COUNTER_ZERO (t_biu_clk_counter_zero),
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.BIU_NMI_CAUGHT (t_biu_nmi_caught),
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.BIU_NMI_DEBOUNCE (t_biu_nmi_debounce),
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.BIU_INTR (t_biu_intr),
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.PFQ_TOP_BYTE (t_pfq_top_byte),
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.PFQ_EMPTY (t_pfq_empty),
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.PFQ_ADDR_OUT (t_pfq_addr_out),
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.BIU_REGISTER_ES (t_biu_register_es),
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.BIU_REGISTER_SS (t_biu_register_ss),
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.BIU_REGISTER_CS (t_biu_register_cs),
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.BIU_REGISTER_DS (t_biu_register_ds),
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.BIU_REGISTER_RM (t_biu_register_rm),
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.BIU_REGISTER_REG (t_biu_register_reg),
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.BIU_RETURN_DATA (t_biu_return_data)
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);
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endmodule
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