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90 lines
4.8 KiB
VHDL
90 lines
4.8 KiB
VHDL
-------------------------------------------------------------------------------
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-- --
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-- X X XXXXXX XXXXXX XXXXXX XXXXXX X --
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-- XX XX X X X X X X X XX --
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-- X X X X X X X X X X X X --
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-- X X X X X X X X X X X X --
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-- X X X X XXXXXX X X XXXXXX X --
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-- X X X X X X X X X --
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-- X X X X X X X X X --
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-- X X X X X X X X X X --
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-- X X XXXXXX XXXXXX XXXXXX XXXXXX X --
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-- --
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-- --
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-- O R E G A N O S Y S T E M S --
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-- --
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-- Design & Consulting --
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-- --
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-------------------------------------------------------------------------------
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-- --
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-- Web: http://www.oregano.at/ --
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-- --
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-- Contact: mc8051@oregano.at --
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-- --
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-------------------------------------------------------------------------------
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-- --
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-- MC8051 - VHDL 8051 Microcontroller IP Core --
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-- Copyright (C) 2001 OREGANO SYSTEMS --
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-- --
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-- This library is free software; you can redistribute it and/or --
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-- modify it under the terms of the GNU Lesser General Public --
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-- License as published by the Free Software Foundation; either --
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-- version 2.1 of the License, or (at your option) any later version. --
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-- --
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-- This library is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
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-- Lesser General Public License for more details. --
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-- --
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-- Full details of the license can be found in the file LGPL.TXT. --
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-- --
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-- You should have received a copy of the GNU Lesser General Public --
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-- License along with this library; if not, write to the Free Software --
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
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-- --
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-------------------------------------------------------------------------------
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--
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--
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-- Author: Roland Höller
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--
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-- Filename: dcml_adjust_.vhd
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--
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-- Date of Creation: Mon Aug 9 12:14:48 1999
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--
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-- Version: $Revision: 1.4 $
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--
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-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $
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--
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--
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-- Description: Combinational design to calculate the decimal
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-- representation (BCD) of a data bus.
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--
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--
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--
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--
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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-----------------------------ENTITY DECLARATION--------------------------------
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entity dcml_adjust is
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generic (DWIDTH : integer := 12);
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port (data_i : in std_logic_vector(DWIDTH-1 downto 0);
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cy_i : in std_logic_vector((DWIDTH-1)/4 downto 0);
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data_o : out std_logic_vector(DWIDTH-1 downto 0);
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cy_o : out std_logic);
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-----------------------------------------------------------------------------
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-- data_i .......... Data bus
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-- cy_i ............ Carry flags (one for each nibble)
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-- data_o .......... Adjusted data bus
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-- cy_o ............ New overall carry flag
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-----------------------------------------------------------------------------
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end dcml_adjust;
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