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416 lines
12 KiB
VHDL
416 lines
12 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- The Arithmetic Logic Unit (ALU).
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-- It contains the ALU core plus the Accumulator and the Temp Reg.
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--
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-- $Id: alu.vhd 295 2009-04-01 19:32:48Z arniml $
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t48/
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.t48_pack.word_t;
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use work.t48_alu_pack.alu_op_t;
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entity t48_alu is
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port (
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-- Global Interface -------------------------------------------------------
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clk_i : in std_logic;
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res_i : in std_logic;
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en_clk_i : in boolean;
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-- T48 Bus Interface ------------------------------------------------------
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data_i : in word_t;
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data_o : out word_t;
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write_accu_i : in boolean;
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write_shadow_i : in boolean;
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write_temp_reg_i : in boolean;
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read_alu_i : in boolean;
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-- Decoder Interface ------------------------------------------------------
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carry_i : in std_logic;
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carry_o : out std_logic;
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aux_carry_o : out std_logic;
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alu_op_i : in alu_op_t;
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use_carry_i : in boolean;
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da_high_i : in boolean;
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da_overflow_o : out boolean;
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accu_low_i : in boolean;
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p06_temp_reg_i : in boolean;
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p60_temp_reg_i : in boolean
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);
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end t48_alu;
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library ieee;
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use ieee.numeric_std.all;
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use work.t48_pack.clk_active_c;
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use work.t48_pack.res_active_c;
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use work.t48_pack.bus_idle_level_c;
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use work.t48_pack.nibble_t;
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use work.t48_alu_pack.all;
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-- pragma translate_off
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use work.t48_tb_pack.tb_accu_s;
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-- pragma translate_on
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architecture rtl of t48_alu is
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-- the Accumulator and Temp Reg
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signal accumulator_q,
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accu_shadow_q,
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temp_req_q : word_t;
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-- inputs to the ALU core
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signal in_a_s,
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in_b_s : word_t;
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-- output of the ALU core
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signal data_s : word_t;
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signal add_result_s : alu_operand_t;
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begin
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-----------------------------------------------------------------------------
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-- Process working_regs
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--
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-- Purpose:
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-- Implements the working registers:
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-- + Accumulator
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-- + Temp Reg
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--
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working_regs: process (res_i, clk_i)
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begin
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if res_i = res_active_c then
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accumulator_q <= (others => '0');
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accu_shadow_q <= (others => '0');
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temp_req_q <= (others => '0');
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elsif clk_i'event and clk_i = clk_active_c then
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if en_clk_i then
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if write_accu_i then
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if accu_low_i then
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accumulator_q(nibble_t'range) <= data_i(nibble_t'range);
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else
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accumulator_q <= data_i;
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end if;
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end if;
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if write_shadow_i then
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-- write shadow directly from t48 data bus
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accu_shadow_q <= data_i;
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else
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-- default: update shadow Accumulator from real Accumulator
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accu_shadow_q <= accumulator_q;
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end if;
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if p06_temp_reg_i then
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-- low nibble of DA sequence
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temp_req_q <= "00000110";
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elsif p60_temp_reg_i then
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-- high nibble of DA sequence
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temp_req_q <= "01100000";
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elsif write_temp_reg_i then
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-- normal load from T48 bus
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temp_req_q <= data_i;
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end if;
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end if;
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end if;
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end process working_regs;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Build the inputs to the ALU core.
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-- Input A:
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-- Unary operators use only Input A.
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-- Is always fed from the shadow Accumulator.
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-- Assumption: It never happens that the Accumulator is written and then
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-- read for an ALU operation in the next cycle.
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-- Its contents can thus be staged through the shadow Accu.
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-- Input B:
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-- Is always fed from the Temp Reg.
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-----------------------------------------------------------------------------
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in_a_s <= accu_shadow_q;
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in_b_s <= temp_req_q;
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-----------------------------------------------------------------------------
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-- Process alu_core
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--
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-- Purpose:
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-- Implements the ALU core.
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-- All operations defined in alu_op_t are handled here.
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--
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alu_core: process (in_a_s,
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in_b_s,
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alu_op_i,
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carry_i,
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use_carry_i,
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add_result_s)
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begin
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-- default assigments
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data_s <= (others => '0');
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carry_o <= '0';
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case alu_op_i is
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-- Operation: AND -------------------------------------------------------
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when ALU_AND =>
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data_s <= in_a_s and in_b_s;
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-- Operation: OR --------------------------------------------------------
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when ALU_OR =>
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data_s <= in_a_s or in_b_s;
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-- Operation: XOR -------------------------------------------------------
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when ALU_XOR =>
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data_s <= in_a_s xor in_b_s;
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-- Operation: Add -------------------------------------------------------
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when ALU_ADD =>
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data_s <= add_result_s(data_s'range);
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carry_o <= add_result_s(add_result_s'high);
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-- Operation: CPL -------------------------------------------------------
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when ALU_CPL =>
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data_s <= not in_a_s;
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-- Operation: CLR -------------------------------------------------------
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when ALU_CLR =>
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data_s <= (others => '0');
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-- Operation: RL --------------------------------------------------------
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when ALU_RL =>
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data_s(7 downto 1) <= in_a_s(6 downto 0);
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carry_o <= in_a_s(7);
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if use_carry_i then
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data_s(0) <= carry_i;
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else
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data_s(0) <= in_a_s(7);
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end if;
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-- Operation: RR --------------------------------------------------------
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when ALU_RR =>
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data_s(6 downto 0) <= in_a_s(7 downto 1);
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carry_o <= in_a_s(0);
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if use_carry_i then
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data_s(7) <= carry_i;
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else
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data_s(7) <= in_a_s(0);
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end if;
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-- Operation: Swap ------------------------------------------------------
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when ALU_SWAP =>
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data_s(3 downto 0) <= in_a_s(7 downto 4);
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data_s(7 downto 4) <= in_a_s(3 downto 0);
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-- Operation: DEC -------------------------------------------------------
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when ALU_DEC =>
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data_s <= add_result_s(data_s'range);
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-- Operation: INC -------------------------------------------------------
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when ALU_INC =>
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data_s <= add_result_s(data_s'range);
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-- Operation CONCAT -----------------------------------------------------
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when ALU_CONCAT =>
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data_s <= in_b_s(7 downto 4) & in_a_s(3 downto 0);
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-- Operation: NOP -------------------------------------------------------
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when ALU_NOP =>
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data_s <= in_a_s;
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when others =>
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-- pragma translate_off
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assert false
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report "Unknown ALU operation selected!"
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severity error;
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-- pragma translate_on
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end case;
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end process alu_core;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process adder
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--
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-- Purpose:
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-- Implements the adder used by several instructions.
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-- This way of modelling the adder forces resource sharing of:
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-- * ADD
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-- * INC
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-- * DEC
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--
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adder: process (in_a_s,
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in_b_s,
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alu_op_i,
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carry_i,
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use_carry_i)
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variable add_a_v, add_b_v : alu_operand_t;
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variable c_v : alu_operand_t;
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variable result_v : UNSIGNED(alu_operand_t'range);
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variable aux_c_v : std_logic_vector(1 downto 0);
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begin
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-- Carry Selection --------------------------------------------------------
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c_v := (others => '0');
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if use_carry_i and carry_i = '1' then
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c_v(0) := '1';
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end if;
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-- Operand Selection ------------------------------------------------------
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-- defaults for ADD
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add_a_v := '0' & in_a_s;
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add_b_v := '0' & in_b_s;
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case alu_op_i is
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when ALU_INC =>
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add_b_v := (others => '0');
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add_b_v(0) := '1';
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when ALU_DEC =>
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add_b_v := (others => '1');
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when others =>
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null;
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end case;
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-- The Adder --------------------------------------------------------------
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result_v := UNSIGNED(add_a_v) +
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UNSIGNED(add_b_v) +
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UNSIGNED(c_v);
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add_result_s <= std_logic_vector(result_v);
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-- Auxiliary Carry --------------------------------------------------------
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aux_c_v := in_a_s(4) & in_b_s(4);
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aux_carry_o <= '0';
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case aux_c_v is
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when "00" | "11" =>
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if result_v(4) = '1' then
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aux_carry_o <= '1';
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end if;
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when "01" | "10" =>
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if result_v(4) = '0' then
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aux_carry_o <= '1';
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end if;
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when others =>
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null;
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end case;
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end process adder;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process da_overflow
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--
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-- Purpose:
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-- Detect overflow situation during DA sequence.
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--
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da_overflow: process (accu_shadow_q,
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da_high_i)
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variable da_nibble_v : nibble_t;
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function da_overflow_f(data : in nibble_t) return boolean is
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variable overflow_v : boolean;
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begin
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case data is
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when "1010" |
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"1011" |
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"1100" |
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"1101" |
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"1110" |
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"1111" =>
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overflow_v := true;
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when others =>
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overflow_v := false;
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end case;
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return(overflow_v);
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end;
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begin
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if da_high_i then
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da_nibble_v := accu_shadow_q(7 downto 4);
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else
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da_nibble_v := accu_shadow_q(3 downto 0);
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end if;
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da_overflow_o <= da_overflow_f(da_nibble_v);
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end process da_overflow;
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--
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-----------------------------------------------------------------------------
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-- pragma translate_off
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-----------------------------------------------------------------------------
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-- Testbench support.
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-----------------------------------------------------------------------------
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tb_accu_s <= accumulator_q;
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-- pragma translate_on
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-----------------------------------------------------------------------------
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-- Output Multiplexer.
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-----------------------------------------------------------------------------
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data_o <= data_s
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when read_alu_i else
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(others => bus_idle_level_c);
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end rtl;
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