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250 lines
8.0 KiB
VHDL
250 lines
8.0 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- The Wishbone master module.
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--
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-- $Id: wb_master.vhd 295 2009-04-01 19:32:48Z arniml $
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--
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-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t48/
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--
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--
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-- Short description:
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-- This design implements a simple Wishbone bus master. It connects to the
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-- BUS interface of the T48 uController core.
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--
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-- The CPU clock is suppressed with en_clk_o to stall the CPU until the
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-- acknowledge signal from the peripheral is detected.
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--
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-- The adr_i input selects between configuration and Wishbone address range:
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-- 1 - configuration range
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-- 0 - Wishbone range
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--
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-- When configuration range is selected, two address register are accessible.
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-- 000h -> adr1
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-- 001h -> adr2
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-- These registers can be read and written with movx to their addresses.
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--
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-- When Wishbone range is selected, all movx generate Wishbone bus cycles
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-- (either read or write) at following address:
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-- Wishbone address = adr2 & adr1 & address of movx
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.t48_pack.all;
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entity t48_wb_master is
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port (
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xtal_i : in std_logic;
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res_i : in std_logic;
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en_clk_o : out std_logic;
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-- T48 Interface ----------------------------------------------------------
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ale_i : in std_logic;
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rd_n_i : in std_logic;
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wr_n_i : in std_logic;
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adr_i : in std_logic;
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db_bus_i : in std_logic_vector( 7 downto 0);
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db_bus_o : out std_logic_vector( 7 downto 0);
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-- Wishbone Interface -----------------------------------------------------
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wb_cyc_o : out std_logic;
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wb_stb_o : out std_logic;
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wb_we_o : out std_logic;
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wb_adr_o : out std_logic_vector(23 downto 0);
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wb_ack_i : in std_logic;
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wb_dat_i : in std_logic_vector( 7 downto 0);
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wb_dat_o : out std_logic_vector( 7 downto 0)
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);
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end t48_wb_master;
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architecture rtl of t48_wb_master is
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-----------------------------------------------------------------------------
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-- Controller FSM
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-----------------------------------------------------------------------------
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type state_t is (IDLE, CYC, WAIT_INACT);
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signal state_s,
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state_q : state_t;
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-----------------------------------------------------------------------------
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-- Select signals for each range
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-----------------------------------------------------------------------------
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signal sel_adr1_s,
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sel_adr2_s,
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sel_wb_s : boolean;
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signal wr_s,
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rd_s : boolean;
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signal adr_q : std_logic_vector(23 downto 0);
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signal wb_dat_q : std_logic_vector( 7 downto 0);
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begin
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-----------------------------------------------------------------------------
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-- Select signal generation
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-----------------------------------------------------------------------------
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sel_adr1_s <= adr_i = '1' and adr_q(word_t'range) = "00000000";
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sel_adr2_s <= adr_i = '1' and adr_q(word_t'range) = "00000001";
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sel_wb_s <= adr_i = '0';
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wr_s <= wr_n_i = '0';
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rd_s <= rd_n_i = '0';
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-----------------------------------------------------------------------------
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-- Process seq
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--
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-- Purpose:
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-- Implements the sequential elements.
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--
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seq: process (res_i, xtal_i)
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begin
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if res_i = res_active_c then
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adr_q <= (others => '0');
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wb_dat_q <= (others => '0');
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state_q <= IDLE;
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elsif xtal_i'event and xtal_i = clk_active_c then
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-- Address register -----------------------------------------------------
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-- update lowest address byte
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if ale_i = '1' then
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adr_q(word_t'range) <= db_bus_i;
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end if;
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-- set adr1 part
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if wr_s and sel_adr1_s then
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adr_q(word_t'length*2 - 1 downto word_t'length) <= db_bus_i;
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end if;
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-- set adr2 part
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if wr_s and sel_adr2_s then
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adr_q(word_t'length*3 - 1 downto word_t'length*2) <= db_bus_i;
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end if;
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-- Data from peripheral has to be saved ---------------------------------
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if wb_ack_i = '1' then
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wb_dat_q <= wb_dat_i;
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end if;
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-- FSM state ------------------------------------------------------------
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state_q <= state_s;
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end if;
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end process seq;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process fsm
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--
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-- Purpose:
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-- Implements the state transitions of the controller FSM.
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--
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fsm: process (state_q,
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wr_s,
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rd_s,
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sel_wb_s,
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wb_ack_i)
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begin
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-- default assignments
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wb_cyc_o <= '0';
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wb_stb_o <= '0';
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en_clk_o <= '1';
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state_s <= IDLE;
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case state_q is
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-- Idle State: Wait for read or write access ----------------------------
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when IDLE =>
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if sel_wb_s and (wr_s or rd_s) then
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state_s <= CYC;
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end if;
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-- WB Cycle State: Start Wishbone cycle and wait for ack ----------------
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when CYC =>
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wb_cyc_o <= '1';
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wb_stb_o <= '1';
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en_clk_o <= '0';
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if wb_ack_i = '1' then
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state_s <= WAIT_INACT;
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else
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state_s <= CYC;
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end if;
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-- Wait inact State: Wait for end of T48 access -------------------------
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when WAIT_INACT =>
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if not wr_s and not rd_s then
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state_s <= IDLE;
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else
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state_s <= WAIT_INACT;
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end if;
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when others =>
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null;
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end case;
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end process fsm;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Output multiplexer
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-----------------------------------------------------------------------------
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db_bus_o <= adr_q(word_t'length*2 - 1 downto word_t'length)
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when sel_adr1_s else
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adr_q(word_t'length*3 - 1 downto word_t'length*2)
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when sel_adr2_s else
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wb_dat_q;
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-----------------------------------------------------------------------------
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-- Output mapping
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-----------------------------------------------------------------------------
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wb_adr_o <= adr_q;
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wb_dat_o <= db_bus_i;
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wb_we_o <= '1'
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when wr_s and sel_wb_s else
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'0';
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end rtl;
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