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Gehstock.Mist_FPGA/common/CPU/v30/V30.qip
2022-07-30 13:31:00 +02:00

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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) cpu.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) divider.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) export.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) registerpackage.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) bus_savestates.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) reg_savestates.vhd ]