mirror of
https://github.com/Gehstock/Mist_FPGA.git
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106 lines
2.9 KiB
VHDL
106 lines
2.9 KiB
VHDL
-----------------------------------------------------------------
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--------------- Bus Package --------------------------------
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-----------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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package pBus_savestates is
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constant SSBUS_buswidth : integer := 64;
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constant SSBUS_busadr : integer := 7;
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type savestate_type is record
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Adr : integer range 0 to (2**SSBUS_busadr)-1;
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upper : integer range 0 to SSBUS_buswidth-1;
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lower : integer range 0 to SSBUS_buswidth-1;
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size : integer range 0 to (2**SSBUS_busadr)-1;
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defval : std_logic_vector(SSBUS_buswidth-1 downto 0);
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end record;
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end package;
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-----------------------------------------------------------------
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--------------- Reg Interface -----------------------------------
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-----------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library work;
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use work.pBus_savestates.all;
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entity eReg_SS is
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generic
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(
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Reg : savestate_type;
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index : integer := 0
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);
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port
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(
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clk : in std_logic;
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BUS_Din : in std_logic_vector(SSBUS_buswidth-1 downto 0);
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BUS_Adr : in std_logic_vector(SSBUS_busadr-1 downto 0);
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BUS_wren : in std_logic;
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BUS_rst : in std_logic;
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BUS_Dout : out std_logic_vector(SSBUS_buswidth-1 downto 0) := (others => '0');
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Din : in std_logic_vector(Reg.upper downto Reg.lower);
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Dout : out std_logic_vector(Reg.upper downto Reg.lower)
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);
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end entity;
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architecture arch of eReg_SS is
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signal Dout_buffer : std_logic_vector(Reg.upper downto Reg.lower) := Reg.defval(Reg.upper downto Reg.lower);
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signal AdrI : std_logic_vector(BUS_Adr'left downto 0);
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begin
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AdrI <= std_logic_vector(to_unsigned(Reg.Adr + index, BUS_Adr'length));
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process (clk)
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begin
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if rising_edge(clk) then
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if (BUS_rst = '1') then
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Dout_buffer <= Reg.defval(Reg.upper downto Reg.lower);
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else
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if (BUS_Adr = AdrI and BUS_wren = '1') then
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for i in Reg.lower to Reg.upper loop
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Dout_buffer(i) <= BUS_Din(i);
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end loop;
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end if;
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end if;
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end if;
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end process;
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Dout <= Dout_buffer;
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goutputbit: for i in Reg.lower to Reg.upper generate
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BUS_Dout(i) <= Din(i) when BUS_Adr = AdrI else '0';
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end generate;
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glowzero_required: if Reg.lower > 0 generate
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glowzero: for i in 0 to Reg.lower - 1 generate
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BUS_Dout(i) <= '0';
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end generate;
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end generate;
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ghighzero_required: if Reg.upper < SSBUS_buswidth-1 generate
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ghighzero: for i in Reg.upper + 1 to SSBUS_buswidth-1 generate
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BUS_Dout(i) <= '0';
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end generate;
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end generate;
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end architecture;
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