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63 lines
3.6 KiB
Verilog
63 lines
3.6 KiB
Verilog
/*******************************************************************************************/
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/** **/
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/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
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/** **/
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/** alu logic module Rev 0.0 07/17/2011 **/
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/** **/
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/*******************************************************************************************/
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module alu_log (logic_c, logic_hc, logic_out, alua_in, alub_in, aluop_reg, carry_bit);
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input carry_bit; /* cpu carry flag */
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input [15:0] alua_in; /* alu a input */
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input [15:0] alub_in; /* alu b input */
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input [`AOP_IDX:0] aluop_reg; /* alu operation control */
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output logic_c; /* alu logic carry result */
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output logic_hc; /* alu logic half-carry result */
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output [15:0] logic_out; /* alu logic result */
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/*****************************************************************************************/
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/* */
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/* signal declarations */
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/* */
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/*****************************************************************************************/
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reg logic_c; /* logic carry output */
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reg logic_hc; /* logic half-carry output */
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reg [15:0] logic_out; /* logic output */
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/*****************************************************************************************/
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/* */
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/* alu logic function */
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/* */
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/*****************************************************************************************/
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always @ (aluop_reg or carry_bit) begin
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casex (aluop_reg)
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`AOP_CCF: logic_c = !carry_bit;
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`AOP_SCF: logic_c = 1'b1;
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default: logic_c = 1'b0;
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endcase
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end
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always @ (aluop_reg or carry_bit) begin
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casex (aluop_reg)
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`AOP_BAND: logic_hc = 1'b1;
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`AOP_CCF: logic_hc = carry_bit;
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default: logic_hc = 1'b0;
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endcase
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end
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always @ (aluop_reg or alua_in or alub_in) begin
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casex (aluop_reg)
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`AOP_BAND: logic_out = {8'h00, alua_in[7:0] & alub_in[7:0]};
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`AOP_BOR: logic_out = {8'h00, alua_in[7:0] | alub_in[7:0]};
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`AOP_BXOR: logic_out = {8'h00, alua_in[7:0] ^ alub_in[7:0]};
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`AOP_RLD1: logic_out = {8'h00, alub_in[3:0], alua_in[3:0]};
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`AOP_RLD2: logic_out = {8'h00, alua_in[7:4], alub_in[7:4]};
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`AOP_RRD1: logic_out = {8'h00, alua_in[3:0], alub_in[7:4]};
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`AOP_RRD2: logic_out = {8'h00, alua_in[7:4], alub_in[3:0]};
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`AOP_APAS: logic_out = alua_in;
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`AOP_PASS: logic_out = alub_in;
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default: logic_out = 16'h0000;
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endcase
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end
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endmodule |