mirror of
https://github.com/Gehstock/Mist_FPGA.git
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92 lines
5.7 KiB
Verilog
92 lines
5.7 KiB
Verilog
/*******************************************************************************************/
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/** **/
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/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
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/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
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/** **/
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/** alu function unit combiner module Rev 0.0 06/13/2012 **/
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/** **/
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/*******************************************************************************************/
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module aluout (cry_nxt, data_bus, hcar_nxt, one_nxt, par_nxt, sign_nxt, zero_nxt, adder_c,
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adder_hc, adder_out, hi_byte, logic_c, logic_hc, logic_out, shft_c, shft_out,
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mult_out,
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unit_sel, word_op);
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input adder_c; /* math carry result */
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input adder_hc; /* math half-carry result */
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input hi_byte; /* shift left byte control */
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input logic_c; /* logic carry result */
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input logic_hc; /* logic half-carry result */
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input shft_c; /* shift carry result */
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input word_op; /* word operation */
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input [1:0] unit_sel; /* alu function unit select */
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input [7:0] shft_out; /* shift unit result */
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input [15:0] adder_out; /* math unit result */
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input [15:0] logic_out; /* logic unit result */
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input [15:0] mult_out; /* multiplier unit result */
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output cry_nxt; /* carry flag next */
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output hcar_nxt; /* half-carry flag next */
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output one_nxt; /* one flag next */
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output par_nxt; /* parity flag next */
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output sign_nxt; /* sign flag next */
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output zero_nxt; /* zero flag next */
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output [15:0] data_bus; /* datapath data bus */
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/*****************************************************************************************/
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/* */
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/* signal declarations */
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/* */
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/*****************************************************************************************/
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wire one_nxt, par_nxt, sign_nxt, zero_nxt;
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wire [15:0] data_bus;
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reg cry_nxt, hcar_nxt;
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reg [15:0] alu_result;
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/*****************************************************************************************/
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/* */
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/* alu function unit combination */
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/* */
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/*****************************************************************************************/
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always @ (unit_sel or adder_out or logic_out or shft_out or mult_out) begin
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casex (unit_sel)
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2'b01: alu_result = adder_out;
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2'b10: alu_result = {8'h00, shft_out};
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2'b11: alu_result = mult_out;
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default: alu_result = logic_out;
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endcase
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end
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/*****************************************************************************************/
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/* */
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/* alu flag outputs */
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/* */
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/*****************************************************************************************/
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always @ (unit_sel or adder_c or logic_c or shft_c) begin
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casex (unit_sel)
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2'b01: cry_nxt = adder_c;
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2'b1x: cry_nxt = shft_c;
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default: cry_nxt = logic_c;
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endcase
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end
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always @ (unit_sel or adder_hc or logic_hc) begin
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casex (unit_sel)
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2'b01: hcar_nxt = adder_hc;
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2'b1x: hcar_nxt = 1'b0;
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default: hcar_nxt = logic_hc;
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endcase
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end
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assign one_nxt = ~|alu_result[7:1] && alu_result[0];
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assign par_nxt = ~^alu_result[7:0];
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assign sign_nxt = (word_op) ? alu_result[15] : alu_result[7];
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assign zero_nxt = (word_op) ? ~|alu_result[15:0] : ~|alu_result[7:0];
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/*****************************************************************************************/
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/* */
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/* alu output left shift */
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/* */
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/*****************************************************************************************/
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assign data_bus = (hi_byte) ? {alu_result[7:0], alu_result[7:0]} : alu_result[15:0];
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endmodule |