mirror of
https://github.com/Gehstock/Mist_FPGA.git
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194 lines
16 KiB
Verilog
194 lines
16 KiB
Verilog
/*******************************************************************************************/
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/** **/
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/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
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/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
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/** **/
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/** processor top level Rev 0.0 06/13/2012 **/
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/** **/
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/*******************************************************************************************/
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module y80_top (dma_ack, halt_tran, iack_tran, io_addr_out, io_data_out, io_read, io_strobe,
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io_tran, ivec_rd, mem_addr_out, mem_data_out, mem_rd, mem_tran, mem_wr,
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reti_tran, t1, clearb, clkc, dma_req, int_req, io_data_in, ivec_data_in,
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mem_data_in, nmi_req, resetb, wait_req);
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input clearb; /* master (test) reset */
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input clkc; /* main cpu clock */
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input dma_req; /* dma request */
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input int_req; /* interrupt request */
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input nmi_req; /* nmi request */
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input resetb; /* internal (user) reset */
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input wait_req; /* wait request */
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input [7:0] io_data_in; /* i/o input data bus */
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input [7:0] ivec_data_in; /* interrupt vector bus */
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input [7:0] mem_data_in; /* memory input bus */
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output dma_ack; /* dma acknowledge */
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output halt_tran; /* halt transaction */
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output iack_tran; /* interrupt acknowledge transaction */
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output io_read; /* i/o read enable */
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output io_tran; /* i/o transaction */
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output io_strobe; /* i/o data strobe */
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output ivec_rd; /* interrupt vector enable */
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output mem_rd; /* memory read enable */
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output mem_tran; /* memory transaction */
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output mem_wr; /* memory write enable */
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output reti_tran; /* return from interrupt transaction */
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output t1; /* first clock of transaction */
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output [7:0] io_data_out; /* i/o output data bus */
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output [7:0] mem_data_out; /* memory output data bus */
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output [15:0] io_addr_out; /* i/o address bus */
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output [15:0] mem_addr_out; /* memory address bus */
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/*****************************************************************************************/
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/* */
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/* signal declarations */
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/* */
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/*****************************************************************************************/
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wire burst_done; /* burst/mlt done */
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wire cflg_en; /* carry flag control */
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wire carry_bit; /* carry flag */
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wire dma_ack; /* dma acknowledge */
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wire dmar_reg; /* latched dma request */
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wire ex_af_pls; /* exchange af,af' */
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wire ex_bank_pls; /* exchange register bank */
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wire ex_dehl_inst; /* exchange de,hl */
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wire ftch_tran; /* inst fetch transaction */
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wire halt_nxt, halt_tran; /* halt transaction */
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wire iack_tran; /* int ack transaction */
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wire if_frst; /* first clock if ifetch */
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wire inta_frst; /* first clock of intack */
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wire intr_reg; /* latched interrupt request */
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wire io_read; /* i/o read enable */
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wire io_tran; /* i/o transaction */
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wire io_strobe; /* i/o data strobe */
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wire ivec_rd; /* interrupt vector enable */
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wire ld_ctrl; /* load control register */
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wire ld_dmaa; /* load dma request */
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wire ld_inst; /* load instruction register */
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wire ld_inta; /* sample latched int */
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wire ld_page; /* load page register */
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wire ld_wait; /* sample wait input */
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wire mem_rd; /* memory read enable */
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wire mem_tran; /* memory transaction */
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wire mem_wr; /* memory write enable */
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wire output_inh; /* disable cpu outputs */
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wire par_bit; /* parity flag */
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wire rd_brst; /* burst read */
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wire rd_frst; /* first clock of read */
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wire rd_nxt; /* read trans next */
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wire reti_nxt, reti_tran; /* reti transaction */
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wire rreg_en; /* update refresh register */
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wire sflg_en; /* sign flag control */
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wire sign_bit; /* sign flag */
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wire tflg_reg; /* temporary flag */
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wire t1; /* first clock of transaction */
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wire vector_int; /* int vector enable */
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wire wait_st; /* wait state identifier */
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wire wr_brst; /* burst write */
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wire wr_frst; /* first clock of write */
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wire xhlt_reg; /* halt exit */
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wire zero_bit; /* zero flag */
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wire zflg_en; /* zero flag control */
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wire [3:0] page_sel; /* inst decode page control */
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wire [3:0] page_reg; /* instruction decode "page" */
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wire [7:0] inst_reg; /* instruction register */
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wire [7:0] data_in; /* read data bus */
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wire [7:0] dout_io_reg, dout_mem_reg; /* write data bus */
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wire [15:0] addr_reg_in; /* processor logical address */
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wire [7:0] io_data_out; /* i/o output data bus */
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wire [7:0] mem_data_out; /* memory output data bus */
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wire [15:0] io_addr_out; /* i/o address bus */
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wire [15:0] mem_addr_out; /* memory address bus */
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wire [`ADCTL_IDX:0] add_sel; /* address output mux control */
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wire [`ALUA_IDX:0] alua_sel; /* alu input a mux control */
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wire [`ALUB_IDX:0] alub_sel; /* alu input b mux control */
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wire [`ALUOP_IDX:0] aluop_sel; /* alu operation control */
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wire [`DI_IDX:0] di_ctl; /* data input control */
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wire [`DO_IDX:0] do_ctl; /* data output control */
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wire [`HFLG_IDX:0] hflg_ctl; /* half-carry flag control */
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wire [`IEF_IDX:0] ief_ctl; /* interrupt enable control */
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wire [`IMD_IDX:0] imd_ctl; /* interrupt mode control */
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wire [`NFLG_IDX:0] nflg_ctl; /* negate flag control */
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wire [`PCCTL_IDX:0] pc_sel; /* pc source control */
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wire [`PFLG_IDX:0] pflg_ctl; /* parity/overflow flag control */
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wire [`STATE_IDX:0] state_nxt, state_reg; /* machine state */
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wire [`TFLG_IDX:0] tflg_ctl; /* temp flag control */
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wire [`TTYPE_IDX:0] tran_sel; /* transaction type */
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wire [`WREG_IDX:0] wr_addr; /* register write address bus */
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/*****************************************************************************************/
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/* */
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/* interface module */
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/* */
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/*****************************************************************************************/
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extint EXTINT ( .data_in(data_in), .dma_ack(dma_ack), .ftch_tran(ftch_tran),
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.halt_tran(halt_tran), .iack_tran(iack_tran),
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.io_addr_out(io_addr_out), .io_data_out(io_data_out),
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.io_read(io_read), .io_strobe(io_strobe), .io_tran(io_tran),
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.ivec_rd(ivec_rd), .mem_addr_out(mem_addr_out),
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.mem_data_out(mem_data_out), .mem_rd(mem_rd), .mem_tran(mem_tran),
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.mem_wr(mem_wr), .reti_tran(reti_tran), .t1(t1),
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.addr_reg_in(addr_reg_in), .clkc(clkc), .dmar_reg(dmar_reg),
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.dout_io_reg(dout_io_reg), .dout_mem_reg(dout_mem_reg),
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.halt_nxt(halt_nxt), .if_frst(if_frst), .inta_frst(inta_frst),
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.io_data_in(io_data_in), .ivec_data_in(ivec_data_in),
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.ld_dmaa(ld_dmaa), .ld_wait(ld_wait), .mem_data_in(mem_data_in),
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.output_inh(output_inh), .rd_frst(rd_frst), .rd_nxt(rd_nxt),
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.resetb(resetb), .reti_nxt(reti_nxt), .tran_sel(tran_sel),
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.wr_frst(wr_frst) );
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/*****************************************************************************************/
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/* */
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/* state machine module */
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/* */
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/*****************************************************************************************/
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machine MACHINE ( .ld_ctrl(ld_ctrl), .state_reg(state_reg), .wait_st(wait_st),
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.clkc(clkc), .dmar_reg(dmar_reg), .intr_reg(intr_reg),
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.ld_inta(ld_inta), .ld_wait(ld_wait), .resetb(resetb),
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.state_nxt(state_nxt), .wait_req(wait_req) );
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/*****************************************************************************************/
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/* */
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/* control module */
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/* */
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/*****************************************************************************************/
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control CONTROL ( .add_sel(add_sel), .alua_sel(alua_sel), .alub_sel(alub_sel),
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.aluop_sel(aluop_sel), .cflg_en(cflg_en), .di_ctl(di_ctl),
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.do_ctl(do_ctl), .ex_af_pls(ex_af_pls), .ex_bank_pls(ex_bank_pls),
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.ex_dehl_inst(ex_dehl_inst), .halt_nxt(halt_nxt), .hflg_ctl(hflg_ctl),
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.ief_ctl(ief_ctl), .if_frst(if_frst), .inta_frst(inta_frst),
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.imd_ctl(imd_ctl), .ld_dmaa(ld_dmaa), .ld_inst(ld_inst),
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.ld_inta(ld_inta), .ld_page(ld_page), .ld_wait(ld_wait),
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.nflg_ctl(nflg_ctl), .output_inh(output_inh), .page_sel(page_sel),
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.pc_sel(pc_sel), .pflg_ctl(pflg_ctl), .rd_frst(rd_frst),
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.rd_nxt(rd_nxt), .reti_nxt(reti_nxt), .rreg_en(rreg_en), .sflg_en(sflg_en),
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.state_nxt(state_nxt), .tflg_ctl(tflg_ctl), .tran_sel(tran_sel),
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.wr_addr(wr_addr), .wr_frst(wr_frst), .zflg_en(zflg_en),
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.carry_bit(carry_bit), .dmar_reg(dmar_reg), .inst_reg(inst_reg),
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.intr_reg(intr_reg), .page_reg(page_reg), .par_bit(par_bit),
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.sign_bit(sign_bit), .state_reg(state_reg), .tflg_reg(tflg_reg),
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.vector_int(vector_int), .xhlt_reg(xhlt_reg), .zero_bit(zero_bit),
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.int_req(int_req) );
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/*****************************************************************************************/
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/* */
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/* data path module */
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/* */
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/*****************************************************************************************/
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datapath DATAPATH ( .addr_reg_in(addr_reg_in), .carry_bit(carry_bit), .dmar_reg(dmar_reg),
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.dout_io_reg(dout_io_reg), .dout_mem_reg(dout_mem_reg),
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.inst_reg(inst_reg), .intr_reg(intr_reg), .page_reg(page_reg),
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.par_bit(par_bit), .sign_bit(sign_bit), .tflg_reg(tflg_reg),
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.vector_int(vector_int), .xhlt_reg(xhlt_reg), .zero_bit(zero_bit),
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.add_sel(add_sel), .alua_sel(alua_sel), .alub_sel(alub_sel),
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.aluop_sel(aluop_sel), .clearb(clearb), .clkc(clkc), .cflg_en(cflg_en),
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.data_in(data_in), .di_ctl(di_ctl), .dma_req(dma_req), .do_ctl(do_ctl),
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.ex_af_pls(ex_af_pls), .ex_bank_pls(ex_bank_pls),
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.ex_dehl_inst(ex_dehl_inst), .hflg_ctl(hflg_ctl), .ief_ctl(ief_ctl),
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.imd_ctl(imd_ctl), .int_req(int_req), .ivec_rd(ivec_rd),
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.ld_ctrl(ld_ctrl), .ld_inst(ld_inst), .ld_page(ld_page),
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.nflg_ctl(nflg_ctl), .nmi_req(nmi_req), .page_sel(page_sel),
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.pc_sel(pc_sel), .pflg_ctl(pflg_ctl), .resetb(resetb), .rreg_en(rreg_en),
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.sflg_en(sflg_en), .tflg_ctl(tflg_ctl), .wait_st(wait_st),
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.wr_addr(wr_addr), .zflg_en(zflg_en) );
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endmodule |