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53 lines
1.2 KiB
Verilog
53 lines
1.2 KiB
Verilog
`timescale 1ns / 1ps
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/* This file is part of JT12.
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JT12 program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 19-3-2017
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*/
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module jt12_mod6
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(
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input [2:0] in, // only 0 to 5 are valid entries
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input [2:0] sum,
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output reg [2:0] out // output between 0 to 5
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);
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reg [3:0] aux;
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always @(*) begin
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aux <= in+sum;
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case( aux )
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4'd6: out <= 3'd0;
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4'd7: out <= 3'd1;
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4'd8: out <= 3'd2;
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4'd9: out <= 3'd3;
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4'ha: out <= 3'd4;
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4'hb: out <= 3'd5;
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4'hc: out <= 3'd0;
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4'he: out <= 3'd1;
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4'hf: out <= 3'd2;
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default: out <= aux;
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endcase
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end
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endmodule
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