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104 lines
3.2 KiB
Verilog
104 lines
3.2 KiB
Verilog
/* This file is part of JT51.
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JT51 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT51 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT51. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 23-10-2019
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*/
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module jt51_csr_op(
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input rst,
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input clk,
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input cen,
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input [ 7:0] din,
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input up_dt1_op,
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input up_mul_op,
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input up_tl_op,
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input up_ks_op,
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input up_amsen_op,
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input up_dt2_op,
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input up_d1l_op,
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input up_ar_op,
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input up_d1r_op,
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input up_d2r_op,
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input up_rr_op,
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output [2:0] dt1,
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output [3:0] mul,
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output [6:0] tl,
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output [1:0] ks,
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output amsen,
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output [1:0] dt2,
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output [3:0] d1l,
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output [4:0] arate,
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output [4:0] rate1,
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output [4:0] rate2,
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output [3:0] rrate
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);
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wire [2:0] dt1_in = din[6:4];
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wire [3:0] mul_in = din[3:0];
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wire [6:0] tl_in = din[6:0];
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wire [1:0] ks_in = din[7:6];
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wire amsen_in= din[7];
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wire [1:0] dt2_in = din[7:6];
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wire [3:0] d1l_in = din[7:4];
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wire [4:0] ar_in = din[4:0];
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wire [4:0] d1r_in = din[4:0];
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wire [4:0] d2r_in = din[4:0];
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wire [3:0] rr_in = din[3:0];
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wire [30:0] reg0_in = {
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up_dt1_op ? dt1_in : dt1, // 3
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up_mul_op ? mul_in : mul, // 4
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up_ks_op ? ks_in : ks, // 2
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up_amsen_op ? amsen_in : amsen, // 1
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up_dt2_op ? dt2_in : dt2, // 2
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up_d1l_op ? d1l_in : d1l, // 4
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up_ar_op ? ar_in : arate, // 5
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up_d1r_op ? d1r_in : rate1, // 5
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up_d2r_op ? d2r_in : rate2 }; // 5
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wire [10:0] reg1_in = {
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up_tl_op ? tl_in : tl, // 7
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up_rr_op ? rr_in : rrate }; // 4
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wire [30:0] reg0_out;
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wire [10:0] reg1_out;
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assign { dt1, mul, ks, amsen, dt2, d1l, arate, rate1, rate2, tl, rrate }
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= {reg0_out, reg1_out};
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// reset to zero
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jt51_sh #( .width(31), .stages(32)) u_reg0op(
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.rst ( rst ),
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.clk ( clk ),
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.cen ( cen ),
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.din ( reg0_in ),
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.drop ( reg0_out )
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);
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// reset to one
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jt51_sh #( .width(11), .stages(32), .rstval(1'b1)) u_reg1op(
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.rst ( rst ),
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.clk ( clk ),
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.cen ( cen ),
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.din ( reg1_in ),
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.drop ( reg1_out )
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);
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endmodule |