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110 lines
2.8 KiB
Verilog
110 lines
2.8 KiB
Verilog
/* This file is part of JT51.
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JT51 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT51 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT51. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 6-2-2021
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*/
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/*
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NFRQ formula in the App:
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Output rate is 55kHz but for NFRQ=1 the formula states that
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the noise is 111kHz, twice the output rate per channel. The
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reason must be the inversion of the LFSR data
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That would suggest that the noise for LEFT and RIGHT are
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different but the rest of the system suggest that LEFT and
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RIGHT outputs are calculated at the same time, based on the
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same OP output.
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I have not been able to measure noise in actual chip because
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operator 31 does not produce any output on my two chips. This
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module is based on NukeYKT's work
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*/
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module jt51_noise(
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input rst,
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input clk,
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input cen, // phi 1
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input [ 4:0] cycles,
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// Noise Frequency
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input [ 4:0] nfrq,
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// Noise envelope
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input [ 9:0] eg, // serial signal in the original design
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input op31_no,
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output out,
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output reg [11:0] mix
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);
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reg update, nfrq_met;
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reg [ 4:0] cnt;
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reg [15:0] lfsr;
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reg last_lfsr0;
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wire all1, fb;
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wire mix_sgn;
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assign out = lfsr[0];
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// period counter
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always @(posedge clk, posedge rst) begin
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if( rst ) begin
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cnt <= 5'b0;
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end else if(cen) begin
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if( &cycles[3:0] ) begin
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cnt <= update ? 5'd0 : (cnt+5'd1);
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end
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update <= nfrq_met;
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nfrq_met <= ~nfrq == cnt;
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end
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end
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// LFSR
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assign fb = update ? ~((all1 & ~last_lfsr0) | (lfsr[2]^last_lfsr0))
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: ~lfsr[0];
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assign all1 = &lfsr;
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always @(posedge clk, posedge rst) begin
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if( rst ) begin
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lfsr <= 16'hffff;
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last_lfsr0 <= 1'b0;
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end else if(cen) begin
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lfsr <= { fb, lfsr[15:1] };
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if(update) last_lfsr0 <= ~lfsr[0];
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end
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end
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// Noise mix
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assign mix_sgn = /*eg!=10'd0 ^*/ ~out;
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always @(posedge clk, posedge rst) begin
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if( rst ) begin
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mix <= 12'd0;
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end else if( op31_no && cen ) begin
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mix <= { mix_sgn, eg[9:2] ^ {8{out}}, {3{mix_sgn}} };
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end
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end
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endmodule
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