mirror of
https://github.com/Gehstock/Mist_FPGA.git
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253 lines
7.6 KiB
Verilog
253 lines
7.6 KiB
Verilog
/* This file is part of JTOPL.
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JTOPL is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JTOPL is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 10-6-2020
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*/
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module jtopl(
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input rst, // rst should be at least 6 clk&cen cycles long
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input clk, // CPU clock
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input cen, // optional clock enable, it not needed leave as 1'b1
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input [ 7:0] din,
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input addr,
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input cs_n,
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input wr_n,
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output [ 7:0] dout,
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output irq_n,
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// combined output
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output signed [15:0] snd,
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output sample
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);
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parameter OPL_TYPE=1;
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wire cenop;
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wire write;
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wire [ 1:0] group;
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wire [17:0] slot;
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wire [ 3:0] trem;
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// Timers
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wire flag_A, flag_B, flagen_A, flagen_B;
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wire [ 7:0] value_A;
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wire [ 7:0] value_B;
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wire load_A, load_B;
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wire clr_flag_A, clr_flag_B;
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wire overflow_A;
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wire zero; // Single-clock pulse at the begginig of s1_enters
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// Phase
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wire [ 9:0] fnum_I;
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wire [ 2:0] block_I;
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wire [ 3:0] mul_II;
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wire [ 9:0] phase_IV;
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wire pg_rst_II;
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wire viben_I;
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wire [ 2:0] vib_cnt;
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// envelope configuration
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wire en_sus_I; // enable sustain
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wire [ 3:0] keycode_II;
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wire [ 3:0] arate_I; // attack rate
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wire [ 3:0] drate_I; // decay rate
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wire [ 3:0] rrate_I; // release rate
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wire [ 3:0] sl_I; // sustain level
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wire ksr_II; // key scale rate - affects rates
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wire [ 1:0] ksl_IV; // key scale level - affects amplitude
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// envelope operation
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wire keyon_I;
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wire eg_stop;
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// envelope number
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wire amen_IV;
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wire [ 5:0] tl_IV;
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wire [ 9:0] eg_V;
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// Global values
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wire am_dep, vib_dep, rhy_en;
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// Operator
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wire [ 2:0] fb_I;
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wire [ 1:0] wavsel_I;
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wire op, con_I, op_out, con_out;
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wire signed [12:0] op_result;
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assign write = !cs_n && !wr_n;
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assign dout = { ~irq_n, flag_A, flag_B, 5'd6 };
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assign eg_stop = 0;
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assign sample = zero;
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jtopl_mmr #(.OPL_TYPE(OPL_TYPE)) u_mmr(
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.rst ( rst ),
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.clk ( clk ),
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.cen ( cen ), // external clock enable
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.cenop ( cenop ), // internal clock enable
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.din ( din ),
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.write ( write ),
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.addr ( addr ),
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.zero ( zero ),
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.group ( group ),
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.op ( op ),
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.slot ( slot ),
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.rhy_en ( rhy_en ),
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// Timers
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.value_A ( value_A ),
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.value_B ( value_B ),
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.load_A ( load_A ),
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.load_B ( load_B ),
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.flagen_A ( flagen_A ),
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.flagen_B ( flagen_B ),
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.clr_flag_A ( clr_flag_A ),
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.clr_flag_B ( clr_flag_B ),
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.flag_A ( flag_A ),
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.overflow_A ( overflow_A ),
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// Phase Generator
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.fnum_I ( fnum_I ),
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.block_I ( block_I ),
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.mul_II ( mul_II ),
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// Operator
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.wavsel_I ( wavsel_I ),
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// Envelope Generator
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.keyon_I ( keyon_I ),
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.en_sus_I ( en_sus_I ),
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.arate_I ( arate_I ),
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.drate_I ( drate_I ),
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.rrate_I ( rrate_I ),
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.sl_I ( sl_I ),
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.ks_II ( ksr_II ),
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.tl_IV ( tl_IV ),
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.ksl_IV ( ksl_IV ),
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.amen_IV ( amen_IV ),
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.viben_I ( viben_I ),
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// Global Values
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.am_dep ( am_dep ),
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.vib_dep ( vib_dep ),
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// Timbre
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.fb_I ( fb_I ),
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.con_I ( con_I )
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);
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jtopl_timers u_timers(
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.rst ( rst ),
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.clk ( clk ),
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.cenop ( cenop ),
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.zero ( zero ),
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.value_A ( value_A ),
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.value_B ( value_B ),
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.load_A ( load_A ),
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.load_B ( load_B ),
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.flagen_A ( flagen_A ),
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.flagen_B ( flagen_B ),
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.clr_flag_A ( clr_flag_A ),
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.clr_flag_B ( clr_flag_B ),
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.flag_A ( flag_A ),
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.flag_B ( flag_B ),
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.overflow_A ( overflow_A ),
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.irq_n ( irq_n )
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);
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jtopl_lfo u_lfo(
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.rst ( rst ),
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.clk ( clk ),
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.cenop ( cenop ),
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.slot ( slot ),
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.vib_cnt ( vib_cnt ),
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.trem ( trem )
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);
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jtopl_pg u_pg(
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.rst ( rst ),
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.clk ( clk ),
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.cenop ( cenop ),
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.slot ( slot ),
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.rhy_en ( rhy_en ),
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// Channel frequency
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.fnum_I ( fnum_I ),
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.block_I ( block_I ),
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// Operator multiplying
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.mul_II ( mul_II ),
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// phase modulation from LFO (vibrato at 6.4Hz)
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.vib_cnt ( vib_cnt ),
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.vib_dep ( vib_dep ),
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.viben_I ( viben_I ),
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// phase operation
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.pg_rst_II ( pg_rst_II ),
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.keycode_II ( keycode_II ),
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.phase_IV ( phase_IV )
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);
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jtopl_eg u_eg(
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.rst ( rst ),
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.clk ( clk ),
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.cenop ( cenop ),
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.zero ( zero ),
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.eg_stop ( eg_stop ),
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// envelope configuration
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.en_sus_I ( en_sus_I ), // enable sustain
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.keycode_II ( keycode_II ),
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.arate_I ( arate_I ), // attack rate
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.drate_I ( drate_I ), // decay rate
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.rrate_I ( rrate_I ), // release rate
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.sl_I ( sl_I ), // sustain level
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.ksr_II ( ksr_II ), // key scale
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// envelope operation
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.keyon_I ( keyon_I ),
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// envelope number
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.fnum_I ( fnum_I ),
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.block_I ( block_I ),
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.lfo_mod ( trem ),
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.amsen_IV ( amen_IV ),
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.ams_IV ( am_dep ),
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.tl_IV ( tl_IV ),
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.ksl_IV ( ksl_IV ),
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.eg_V ( eg_V ),
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.pg_rst_II ( pg_rst_II )
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);
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jtopl_op #(.OPL_TYPE(OPL_TYPE)) u_op(
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.rst ( rst ),
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.clk ( clk ),
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.cenop ( cenop ),
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// location of current operator
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.group ( group ),
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.op ( op ),
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.zero ( zero ),
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.pg_phase_I ( phase_IV ),
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.eg_atten_II( eg_V ), // output from envelope generator
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.fb_I ( fb_I ), // voice feedback
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.wavsel_I ( wavsel_I ), // sine mask (OPL2)
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.con_I ( con_I ),
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.op_result ( op_result ),
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.op_out ( op_out ),
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.con_out ( con_out )
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);
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jtopl_acc u_acc(
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.rst ( rst ),
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.clk ( clk ),
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.cenop ( cenop ),
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.zero ( zero ),
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.op_result ( op_result ),
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.op ( op_out ),
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.con ( con_out ),
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.snd ( snd )
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);
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endmodule
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