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52 lines
1.7 KiB
Verilog
52 lines
1.7 KiB
Verilog
/* This file is part of JTOPL.
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JTOPL is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JTOPL is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 10-10-2021
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*/
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module jtopl2(
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input rst, // rst should be at least 6 clk&cen cycles long
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input clk, // CPU clock
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input cen, // optional clock enable, it not needed leave as 1'b1
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input [ 7:0] din,
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input addr,
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input cs_n,
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input wr_n,
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output [ 7:0] dout,
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output irq_n,
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// combined output
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output signed [15:0] snd,
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output sample
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);
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`define JTOPL2
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jtopl #(.OPL_TYPE(2)) u_base(
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.rst ( rst ),
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.clk ( clk ),
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.cen ( cen ),
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.din ( din ),
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.addr ( addr ),
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.cs_n ( cs_n ),
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.wr_n ( wr_n ),
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.dout ( dout ),
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.irq_n ( irq_n ),
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.snd ( snd ),
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.sample ( sample )
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);
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endmodule |