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44 lines
1.2 KiB
Verilog
44 lines
1.2 KiB
Verilog
/* This file is part of JTOPL.
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JTOPL is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JTOPL is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 17-6-2020
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*/
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module jtopl_eg_cnt(
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input rst,
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input clk,
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input cen,
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input zero,
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output reg [14:0] eg_cnt
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);
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always @(posedge clk, posedge rst) begin : envelope_counter
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if( rst ) begin
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eg_cnt <=15'd0;
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end
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else begin
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if( zero && cen ) begin
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// envelope counter increases at each zero input
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// This is different from OPN/M where it increased
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// once every three zero inputs
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eg_cnt <= eg_cnt + 1'b1;
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end
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end
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end
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endmodule |