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26 lines
744 B
VHDL
26 lines
744 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity CPLD_74LS245 is
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Port ( nE : in STD_LOGIC;
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dir : in STD_LOGIC;
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Bin : in STD_LOGIC_VECTOR (7 downto 0);
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Ain : in STD_LOGIC_VECTOR (7 downto 0);
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Bout :out STD_LOGIC_VECTOR (7 downto 0);
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Aout : out STD_LOGIC_VECTOR (7 downto 0));
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end CPLD_74LS245;
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architecture Behavioral of CPLD_74LS245 is
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begin
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-- if nE = 1 or dir = '1' then HighZ
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-- else B
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Aout <= (7 downto 0 => 'Z') when nE = '1' OR dir = '1' else Bin;
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-- if nE = 1 or dir = '1' then HighZ
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-- wlse A
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Bout <= (7 downto 0 => 'Z') when nE = '1' OR dir = '0' else Ain;
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end Behavioral; |