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33 lines
760 B
VHDL
33 lines
760 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-------------------------------------------------------------------------------
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-- 74xx139
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-- 2-to-4 line decoder
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-------------------------------------------------------------------------------
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entity LOGIC_74XX139 is
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port (
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I_G : in std_logic;
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I_Sel : in std_logic_vector(1 downto 0);
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O_Q : out std_logic_vector(3 downto 0)
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);
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end;
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architecture RTL of LOGIC_74XX139 is
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begin
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xx139 : process (I_G, I_Sel)
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begin
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if I_G = '0' then
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case I_Sel is
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when "00" => O_Q <= "1110";
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when "01" => O_Q <= "1101";
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when "10" => O_Q <= "1011";
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when "11" => O_Q <= "0111";
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when others => null;
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end case;
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else
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O_Q <= "1111";
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end if;
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end process;
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end RTL; |