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130 lines
4.0 KiB
VHDL
130 lines
4.0 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- TTL 74175 - Quad D-Type Flip-Flops with Clear
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--
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-- $Id: ttl_175.vhd,v 1.5 2005/10/10 21:59:13 arnim Exp $
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity ttl_175 is
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port (
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ck_i : in std_logic;
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ck_en_i : in std_logic;
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por_n_i : in std_logic;
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cl_n_i : in std_logic;
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d_i : in std_logic_vector(4 downto 1);
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q_o : out std_logic_vector(4 downto 1);
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q_n_o : out std_logic_vector(4 downto 1);
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d_o : out std_logic_vector(4 downto 1);
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d_n_o : out std_logic_vector(4 downto 1)
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);
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end ttl_175;
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architecture rtl of ttl_175 is
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signal flops_q,
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flops_s : std_logic_vector(4 downto 1);
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begin
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-----------------------------------------------------------------------------
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-- Process flops
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--
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-- Purpose:
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-- Implement the sequential elements.
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--
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-- Note: We assume that the sequential elements power-up to the same state
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-- as forced into by cl_n_i.
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--
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flops: process (ck_i, por_n_i)
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begin
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if por_n_i = '0' then
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flops_q <= (others => '0');
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elsif ck_i'event and ck_i = '1' then
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flops_q <= flops_s;
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end if;
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end process flops;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process comb
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--
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-- Purpose:
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-- Implements the combinational logic.
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--
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comb: process (flops_q,
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cl_n_i,
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d_i,
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ck_en_i)
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begin
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-- default assignments
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flops_s <= flops_q;
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if cl_n_i = '1' then
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if ck_en_i = '1' then
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flops_s <= d_i;
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end if;
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else
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-- pseudo-asynchronous clear
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flops_s <= (others => '0');
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end if;
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end process comb;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Output Mapping
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-----------------------------------------------------------------------------
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q_o <= flops_q;
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q_n_o <= not flops_q;
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d_o <= flops_s;
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d_n_o <= not flops_s;
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end rtl;
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