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https://github.com/Gehstock/Mist_FPGA.git
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98 lines
1.8 KiB
VHDL
98 lines
1.8 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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Use IEEE.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity ttl_74ls138 is
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port
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(
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-- input
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a : in std_logic;
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b : in std_logic;
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c : in std_logic;
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g1 : in std_logic;
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g2a_n : in std_logic;
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g2b_n : in std_logic;
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-- output
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y_n : out std_logic_vector(7 downto 0)
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);
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end ttl_74ls138;
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architecture SYN of ttl_74ls138 is
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signal enabled : std_logic;
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begin
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enabled <= g1 and not g2a_n and not g2b_n;
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y_n(0) <= '1' when enabled = '0' else
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not (not a and not b and not c);
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y_n(1) <= '1' when enabled = '0' else
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not (a and not b and not c);
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y_n(2) <= '1' when enabled = '0' else
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not (not a and b and not c);
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y_n(3) <= '1' when enabled = '0' else
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not (a and b and not c);
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y_n(4) <= '1' when enabled = '0' else
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not (not a and not b and c);
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y_n(5) <= '1' when enabled = '0' else
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not (a and not b and c);
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y_n(6) <= '1' when enabled = '0' else
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not (not a and b and c);
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y_n(7) <= '1' when enabled = '0' else
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not (a and b and c);
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end SYN;
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library IEEE;
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use IEEE.std_logic_1164.all;
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Use IEEE.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity ttl_74ls138_p is
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port
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(
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-- input
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a : in std_logic;
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b : in std_logic;
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c : in std_logic;
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g1 : in std_logic;
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g2a : in std_logic;
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g2b : in std_logic;
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-- output
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y : out std_logic_vector(7 downto 0)
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);
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end ttl_74ls138_p;
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architecture SYN of ttl_74ls138_p is
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signal g2a_n : std_logic;
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signal g2b_n : std_logic;
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signal y_n : std_logic_vector(7 downto 0);
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begin
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g2a_n <= not g2a;
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g2b_n <= not g2b;
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y <= not y_n;
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ttl_74ls138_inst : entity work.ttl_74ls138
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port map
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(
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a => a,
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b => b,
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c => c,
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g1 => g1,
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g2a_n => g2a_n,
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g2b_n => g2b_n,
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y_n => y_n
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);
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end SYN;
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