mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-03-01 09:21:14 +00:00
247 lines
6.4 KiB
Verilog
247 lines
6.4 KiB
Verilog
/*
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---------------------------------------------------------------------------------
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To select a resolution and refresh rate, remove the comments around the desired
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block in this file. The pixel clock output by the DCM module should approximately
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equal the rate specified above the timing block that is uncommented.
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---------------------------------------------------------------------------------
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*/
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// DEFINE THE VARIOUS PIPELINE DELAYS
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`define CHARACTER_DECODE_DELAY 4
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// 640 X 480 @ 60Hz with a 25.175MHz pixel clock
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`define H_ACTIVE 640 // pixels
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`define H_FRONT_PORCH 16 // pixels
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`define H_SYNCH 96 // pixels
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`define H_BACK_PORCH 48 // pixels
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`define H_TOTAL 800 // pixels
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`define V_ACTIVE 480 // lines
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`define V_FRONT_PORCH 11 // lines
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`define V_SYNCH 2 // lines
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`define V_BACK_PORCH 31 // lines
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`define V_TOTAL 524 // lines
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`define CLK_MULTIPLY 2 // 50 * 2/4 = 25.000 MHz
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`define CLK_DIVIDE 4
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/*
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// 640 X 480 @ 72Hz with a 31.500MHz pixel clock
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`define H_ACTIVE 640 // pixels
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`define H_FRONT_PORCH 24 // pixels
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`define H_SYNCH 40 // pixels
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`define H_BACK_PORCH 128 // pixels
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`define H_TOTAL 832 // pixels
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`define V_ACTIVE 480 // lines
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`define V_FRONT_PORCH 9 // lines
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`define V_SYNCH 3 // lines
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`define V_BACK_PORCH 28 // lines
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`define V_TOTAL 520 // lines
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`define CLK_MULTIPLY 5 // 50 * 5/8 = 31.250 MHz
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`define CLK_DIVIDE 8
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*/
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/*
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// 640 X 480 @ 75Hz with a 31.500MHz pixel clock
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`define H_ACTIVE 640 // pixels
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`define H_FRONT_PORCH 16 // pixels
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`define H_SYNCH 96 // pixels
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`define H_BACK_PORCH 48 // pixels
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`define H_TOTAL 800 // pixels
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`define V_ACTIVE 480 // lines
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`define V_FRONT_PORCH 11 // lines
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`define V_SYNCH 2 // lines
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`define V_BACK_PORCH 32 // lines
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`define V_TOTAL 525 // lines
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`define CLK_MULTIPLY 5 // 50 * 5/8 = 31.250 MHz
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`define CLK_DIVIDE 8
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*/
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/*
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// 640 X 480 @ 85Hz with a 36.000MHz pixel clock
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`define H_ACTIVE 640 // pixels
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`define H_FRONT_PORCH 32 // pixels
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`define H_SYNCH 48 // pixels
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`define H_BACK_PORCH 112 // pixels
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`define H_TOTAL 832 // pixels
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`define V_ACTIVE 480 // lines
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`define V_FRONT_PORCH 1 // lines
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`define V_SYNCH 3 // lines
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`define V_BACK_PORCH 25 // lines
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`define V_TOTAL 509 // lines
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`define CLK_MULTIPLY 18 // 50 * 18/25 = 36.000 MHz
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`define CLK_DIVIDE 25
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*/
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/*
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// 800 X 600 @ 56Hz with a 38.100MHz pixel clock
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`define H_ACTIVE 800 // pixels
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`define H_FRONT_PORCH 32 // pixels
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`define H_SYNCH 128 // pixels
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`define H_BACK_PORCH 128 // pixels
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`define H_TOTAL 1088 // pixels
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`define V_ACTIVE 600 // lines
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`define V_FRONT_PORCH 1 // lines
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`define V_SYNCH 4 // lines
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`define V_BACK_PORCH 14 // lines
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`define V_TOTAL 619 // lines
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`define CLK_MULTIPLY 16 // 50 * 16/21 = 38.095 MHz
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`define CLK_DIVIDE 21
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*/
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/*
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// 800 X 600 @ 60Hz with a 40.000MHz pixel clock
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`define H_ACTIVE 800 // pixels
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`define H_FRONT_PORCH 40 // pixels
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`define H_SYNCH 128 // pixels
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`define H_BACK_PORCH 88 // pixels
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`define H_TOTAL 1056 // pixels
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`define V_ACTIVE 600 // lines
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`define V_FRONT_PORCH 1 // lines
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`define V_SYNCH 4 // lines
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`define V_BACK_PORCH 23 // lines
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`define V_TOTAL 628 // lines
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`define CLK_MULTIPLY 4 // 50 * 4/5 = 40.000 MHz
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`define CLK_DIVIDE 5
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*/
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/*
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// 800 X 600 @ 72Hz with a 50.000MHz pixel clock
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`define H_ACTIVE 800 // pixels
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`define H_FRONT_PORCH 56 // pixels
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`define H_SYNCH 120 // pixels
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`define H_BACK_PORCH 64 // pixels
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`define H_TOTAL 1040 // pixels
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`define V_ACTIVE 600 // lines
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`define V_FRONT_PORCH 37 // lines
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`define V_SYNCH 6 // lines
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`define V_BACK_PORCH 23 // lines
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`define V_TOTAL 666 // lines
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`define CLK_MULTIPLY 2 // 50 * 2/2 = 50.000 MHz
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`define CLK_DIVIDE 2
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*/
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/*
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// 800 X 600 @ 75Hz with a 49.500MHz pixel clock
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`define H_ACTIVE 800 // pixels
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`define H_FRONT_PORCH 16 // pixels
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`define H_SYNCH 80 // pixels
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`define H_BACK_PORCH 160 // pixels
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`define H_TOTAL 1056 // pixels
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`define V_ACTIVE 600 // lines
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`define V_FRONT_PORCH 1 // lines
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`define V_SYNCH 2 // lines
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`define V_BACK_PORCH 21 // lines
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`define V_TOTAL 624 // lines
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`define CLK_MULTIPLY 2 // 50 * 2/2 = 50.000 MHz
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`define CLK_DIVIDE 2
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*/
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/*
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// 800 X 600 @ 85Hz with a 56.250MHz pixel clock
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`define H_ACTIVE 800 // pixels
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`define H_FRONT_PORCH 32 // pixels
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`define H_SYNCH 64 // pixels
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`define H_BACK_PORCH 152 // pixels
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`define H_TOTAL 1048 // pixels
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`define V_ACTIVE 600 // lines
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`define V_FRONT_PORCH 1 // lines
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`define V_SYNCH 3 // lines
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`define V_BACK_PORCH 27 // lines
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`define V_TOTAL 631 // lines
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`define CLK_MULTIPLY 9 // 50 * 9/8 = 56.250 MHz
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`define CLK_DIVIDE 8
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*/
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/*
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// 1024 X 768 @ 60Hz with a 65.000MHz pixel clock
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`define H_ACTIVE 1024 // pixels
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`define H_FRONT_PORCH 24 // pixels
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`define H_SYNCH 136 // pixels
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`define H_BACK_PORCH 160 // pixels
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`define H_TOTAL 1344 // pixels
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`define V_ACTIVE 768 // lines
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`define V_FRONT_PORCH 3 // lines
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`define V_SYNCH 6 // lines
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`define V_BACK_PORCH 29 // lines
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`define V_TOTAL 806 // lines
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`define CLK_MULTIPLY 13 // 50 * 13/10 = 65.000 MHz
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`define CLK_DIVIDE 10
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/*
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/*
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// 1024 X 768 @ 70Hz with a 75.000MHz pixel clock
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`define H_ACTIVE 1024 // pixels
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`define H_FRONT_PORCH 24 // pixels
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`define H_SYNCH 136 // pixels
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`define H_BACK_PORCH 144 // pixels
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`define H_TOTAL 1328 // pixels
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`define V_ACTIVE 768 // lines
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`define V_FRONT_PORCH 3 // lines
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`define V_SYNCH 6 // lines
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`define V_BACK_PORCH 29 // lines
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`define V_TOTAL 806 // lines
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`define CLK_MULTIPLY 3 // 50 * 3/2 = 75.000 MHz
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`define CLK_DIVIDE 2
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*/
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/*
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// 1024 X 768 @ 75Hz with a 78.750MHz pixel clock
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`define H_ACTIVE 1024 // pixels
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`define H_FRONT_PORCH 16 // pixels
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`define H_SYNCH 96 // pixels
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`define H_BACK_PORCH 176 // pixels
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`define H_TOTAL 1312 // pixels
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`define V_ACTIVE 768 // lines
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`define V_FRONT_PORCH 1 // lines
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`define V_SYNCH 3 // lines
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`define V_BACK_PORCH 28 // lines
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`define V_TOTAL 800 // lines
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`define CLK_MULTIPLY 11 // 50 * 11/7 = 78.571 MHz
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`define CLK_DIVIDE 7
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*/
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/*
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// 1024 X 768 @ 85Hz with a 94.500MHz pixel clock
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`define H_ACTIVE 1024 // pixels
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`define H_FRONT_PORCH 48 // pixels
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`define H_SYNCH 96 // pixels
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`define H_BACK_PORCH 208 // pixels
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`define H_TOTAL 1376 // pixels
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`define V_ACTIVE 768 // lines
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`define V_FRONT_PORCH 1 // lines
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`define V_SYNCH 3 // lines
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`define V_BACK_PORCH 36 // lines
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`define V_TOTAL 808 // lines
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`define CLK_MULTIPLY 17 // 50 * 17/9 = 94.444 MHz
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`define CLK_DIVIDE 9
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*/
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