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https://github.com/Gehstock/Mist_FPGA.git
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354 lines
8.8 KiB
Verilog
354 lines
8.8 KiB
Verilog
`include "SVGA_DEFINES.v"
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`define SVGA_DECODE_DELAY 7
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// 延时：字符模式
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// 1、(001)锁存 vram 地址，2、(010)读取 vram 3、(011)锁存 vram 数据 4、(100)字库地址 5、(101)锁存字库
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// 6、(110)移位得到点阵，同时锁存vram数据用于调色板 7、(111)建立调色板，锁存色彩
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// Delay: Character mode
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// 1 (001) latch vram address, 2, (010) read vram 3, (011) latch vram data 4, (100) font address 5, (101) latch font
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// 6, (110) shift to get a lattice, while latching vram data for the palette 7, (111) to create a palette, latch color
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// 延时：图形模式 128x64 4色
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// 1、(001)锁存 vram 地址，2、(010)读取 vram 3、(011)锁存 vram 数据 4、(100)空 5、(101)数据锁存至移位寄存器
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// 6、(110)移位得到点阵 7、(111)建立调色板，锁存色彩
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// Delay: graphics mode 128x64 4 colors
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// 1, (001) latch vram address, 2, (010) read vram 3, (011) latch vram data 4, (100) empty 5, (101) data latched to the shift register
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// 6, (110) shift to get the dot matrix 7, (111) to create a palette, latch color
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module SVGA_TIMING_GENERATION
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(
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pixel_clock,
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reset,
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h_synch,
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v_synch,
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blank,
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pixel_count,
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line_count,
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show_border,
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// text
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subchar_pixel,
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subchar_line,
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char_column,
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char_line,
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// graph
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graph_pixel,
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graph_line_2x,
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graph_line_3x
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);
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input pixel_clock; // pixel clock
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input reset; // reset
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(*keep*)output reg h_synch; // horizontal synch for VGA connector
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(*keep*)output reg v_synch; // vertical synch for VGA connector
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output reg blank; // composite blanking
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output reg [10:0] pixel_count; // counts the pixels in a line
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output reg [9:0] line_count; // counts the display lines
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(*keep*)output reg show_border;
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// 字符控制
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(*keep*)output reg [3:0] subchar_pixel; // pixel position within the character
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(*keep*)output reg [4:0] subchar_line; // identifies the line number within a character block
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(*keep*)output reg [6:0] char_column; // character number on the current line
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(*keep*)output reg [6:0] char_line; // line number on the screen
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// 图形控制 128*64
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(*keep*)output reg [8:0] graph_pixel;
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(*keep*)output reg [9:0] graph_line_3x;
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// 图形控制 256*192
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(*keep*)output reg [9:0] graph_line_2x;
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(*keep*)reg h_blank;
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reg v_blank;
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reg show_pixel;
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reg show_line;
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// CREATE THE HORIZONTAL LINE PIXEL COUNTER
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always @ (posedge pixel_clock or posedge reset) begin
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if (reset)
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// on reset set pixel counter to 0
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pixel_count <= 11'd0;
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else if (pixel_count == (`H_TOTAL - 1))
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// last pixel in the line, so reset pixel counter
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pixel_count <= 11'd0;
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else
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pixel_count <= pixel_count + 1;
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end
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// CREATE THE HORIZONTAL SYNCH PULSE
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always @ (posedge pixel_clock or posedge reset) begin
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if (reset)
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// on reset remove h_synch
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h_synch <= 1'b0;
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else if (pixel_count == (`H_ACTIVE + `H_FRONT_PORCH - 1))
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// start of h_synch
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h_synch <= 1'b1;
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else if (pixel_count == (`H_TOTAL - `H_BACK_PORCH - 1))
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// end of h_synch
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h_synch <= 1'b0;
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end
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// CREATE THE VERTICAL FRAME LINE COUNTER
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always @ (posedge pixel_clock or posedge reset) begin
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if (reset)
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// on reset set line counter to 0
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line_count <= 10'd0;
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else if ((line_count == (`V_TOTAL - 1)) & (pixel_count == (`H_TOTAL - 1)))
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// last pixel in last line of frame, so reset line counter
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line_count <= 10'd0;
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else if ((pixel_count == (`H_TOTAL - 1)))
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// last pixel but not last line, so increment line counter
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line_count <= line_count + 1;
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end
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// CREATE THE VERTICAL SYNCH PULSE
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always @ (posedge pixel_clock or posedge reset) begin
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if (reset)
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// on reset remove v_synch
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v_synch <= 1'b0;
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else if ((line_count == (`V_ACTIVE + `V_FRONT_PORCH - 1) &
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(pixel_count == `H_TOTAL - 1)))
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// start of v_synch
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v_synch <= 1'b1;
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else if ((line_count == (`V_TOTAL - `V_BACK_PORCH - 1)) &
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(pixel_count == (`H_TOTAL - 1)))
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// end of v_synch
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v_synch <= 1'b0;
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end
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// CREATE THE HORIZONTAL BLANKING SIGNAL
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// the "-2" is used instead of "-1" because of the extra register delay
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// for the composite blanking signal
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always @ (posedge pixel_clock or posedge reset) begin
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if (reset)
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// on reset remove the h_blank
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h_blank <= 1'b0;
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else if (pixel_count == (`H_ACTIVE -2))
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// start of HBI
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h_blank <= 1'b1;
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else if (pixel_count == (`H_TOTAL -2))
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// end of HBI
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h_blank <= 1'b0;
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end
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// CREATE THE VERTICAL BLANKING SIGNAL
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// the "-2" is used instead of "-1" in the horizontal factor because of the extra
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// register delay for the composite blanking signal
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always @ (posedge pixel_clock or posedge reset) begin
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if (reset)
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// on reset remove v_blank
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v_blank <= 1'b0;
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else if ((line_count == (`V_ACTIVE - 1) &
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(pixel_count == `H_TOTAL - 2)))
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// start of VBI
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v_blank <= 1'b1;
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else if ((line_count == (`V_TOTAL - 1)) &
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(pixel_count == (`H_TOTAL - 2)))
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// end of VBI
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v_blank <= 1'b0;
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end
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// CREATE THE COMPOSITE BANKING SIGNAL
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always @ (posedge pixel_clock or posedge reset) begin
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if (reset)
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// on reset remove blank
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blank <= 1'b0;
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// blank during HBI or VBI
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else if (h_blank || v_blank)
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blank <= 1'b1;
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else
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// active video do not blank
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blank <= 1'b0;
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end
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////////////////////////////////////////////////////
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// 以上部分内容相对固定，是VGA的控制信号和计数器 //
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////////////////////////////////////////////////////
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/*
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CREATE THE CHARACTER COUNTER.
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CHARACTERS ARE DEFINED WITHIN AN 8 x 8 PIXEL BLOCK.
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A 640 x 480 video mode will display 80 characters on 60 lines.
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A 800 x 600 video mode will display 100 characters on 75 lines.
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A 1024 x 768 video mode will display 128 characters on 96 lines.
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"subchar_line" identifies the row in the 8 x 8 block.
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"subchar_pixel" identifies the column in the 8 x 8 block.
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*/
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// 8x12点阵 32x16个字符 256x192
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// 640x480 倍线 512x384 左右各空64个点，上下空 48 个点。
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// 需要生成四个数据：
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// 字符点阵 subchar_line subchar_pixel
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// 字符寻址 char_column char_line
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always @ (posedge pixel_clock or posedge reset) begin
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if (reset)
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show_pixel <= 1'b0;
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else if (pixel_count == (-1) + 64 - `SVGA_DECODE_DELAY)
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show_pixel <= 1'b1;
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else if (pixel_count == (`H_ACTIVE - 1) - 64 - `SVGA_DECODE_DELAY)
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show_pixel <= 1'b0;
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end
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always @ (posedge h_synch or posedge reset) begin
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if (reset)
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show_line <= 1'b0;
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else if (line_count == (-1) + 48)
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show_line <= 1'b1;
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else if (line_count == (`V_ACTIVE - 1) - 48)
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show_line <= 1'b0;
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end
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always @ (posedge pixel_clock or posedge reset) begin
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if (reset)
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show_border <= 1'b1;
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else if (pixel_count == (-1) + 64)
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show_border <= ~show_line;
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else if (pixel_count == (`H_ACTIVE - 1) - 64)
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show_border <= 1'b1;
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end
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// text 32x16
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always @ (posedge pixel_clock or posedge reset) begin
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if (reset)
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begin
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// reset to 5 so that the first character data can be latched
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subchar_pixel <= 4'b0000;
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char_column <= 7'd0;
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end
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else if (h_synch)
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begin
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// reset to 5 so that the first character data can be latched
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subchar_pixel <= 4'b0000;
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char_column <= 7'd0;
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end
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else if(show_pixel)
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begin
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subchar_pixel <= subchar_pixel + 1;
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if(subchar_pixel == 4'b1111) // 8*2-1
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char_column <= char_column + 1;
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end
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end
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always @ (posedge h_synch or posedge reset) begin
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if (reset)
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begin
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// on reset set line counter to 0
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subchar_line <= 5'b00000;
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char_line <= 7'd0;
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end
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else if(v_synch)
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begin
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// reset line counter
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subchar_line <= 5'b00000;
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char_line <= 7'd0;
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end
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else if(show_line)
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if(subchar_line == 5'd23) // 12*2-1
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begin
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subchar_line <= 5'b00000;
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char_line <= char_line + 1;
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end
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else
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// increment line counter
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subchar_line <= subchar_line + 1;
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end
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// 为所有图形模式提供水平计数
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always @ (posedge pixel_clock or posedge reset) begin
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if (reset)
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begin
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// reset to 5 so that the first character data can be latched
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graph_pixel <= 9'd0;
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end
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else if (h_synch)
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begin
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// reset to 5 so that the first character data can be latched
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graph_pixel <= 9'd0;
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end
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else if(show_pixel)
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begin
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graph_pixel <= graph_pixel + 1;
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end
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end
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// 为图形模式提供垂直计数
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// 64x64 4色
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// 128x64 2色
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// 128x64 4色
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always @ (posedge h_synch or posedge reset) begin
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if (reset)
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begin
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// on reset set line counter to 0
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graph_line_3x <= 10'd0;
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end
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else if(v_synch)
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begin
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// reset line counter
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graph_line_3x <= 10'd0;
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end
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else if(show_line)
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if(graph_line_3x[1:0] == 2'b10) // 3行为单位计数
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graph_line_3x <= graph_line_3x + 2;
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else
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// increment line counter
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graph_line_3x <= graph_line_3x + 1;
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end
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// 为图形模式提供垂直计数
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// 128x96 2色
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// 128x96 4色
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// 128x192 2色
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// 128x192 4色
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// 256x192 2色
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always @ (posedge h_synch or posedge reset) begin
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if (reset)
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begin
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// on reset set line counter to 0
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graph_line_2x <= 10'd0;
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end
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else if(v_synch)
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begin
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// reset line counter
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graph_line_2x <= 10'd0;
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end
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else if(show_line)
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// increment line counter
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graph_line_2x <= graph_line_2x + 1;
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end
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endmodule //SVGA_TIMING_GENERATION
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