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https://github.com/Gehstock/Mist_FPGA.git
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66 lines
1.6 KiB
VHDL
66 lines
1.6 KiB
VHDL
--
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-- DAC.vhd
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--
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-- Digital to analog convertor.
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--
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-- Copyright (C)2001 SEILEBOST
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-- All rights reserved.
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--
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-- $Id: DAC.vhd, v0.2 2001/11/02 00:00:00 SEILEBOST $
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--
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-- from XAPP154.pdf & XAPP154.ZIP (XILINX APPLICATION)
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--
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-- DAC 8 Bits ( method : sigma delta)
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-- 2^N clock to convert with N = width of input
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-- Ex : Bus 8 bits => 256 CLOCK master to convert an value.
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-- Theorem Shannon : 2 x Fmax x 256 =< 16 MHz => Fmax = 31250 Hz
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-- band of sound : 0 -> 20000 Hz : Ok !!
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity DAC is
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Port ( CLK_DAC : in std_logic;
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RST : in std_logic;
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IN_DAC : in std_logic_vector(7 downto 0);
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OUT_DAC : out std_logic );
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end DAC;
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architecture Behavioral of DAC is
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signal DeltaAdder : std_logic_vector(9 downto 0);
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signal SigmaAdder : std_logic_vector(9 downto 0);
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signal SigmaLatch : std_logic_vector(9 downto 0);
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signal DeltaB : std_logic_vector(9 downto 0);
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begin
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PROCESS(SigmaLatch, DeltaB)
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BEGIN
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DeltaB <= TRANSPORT ( SigmaLatch(9) & SigmaLatch(9) & "00000000");
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END PROCESS;
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PROCESS(IN_DAC, DeltaB, DeltaAdder)
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BEGIN
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DeltaAdder <= IN_DAC + DeltaB;
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END PROCESS;
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PROCESS(DeltaAdder, SigmaLatch)
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BEGIN
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SigmaAdder <= DeltaAdder + SigmaLatch;
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END PROCESS;
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PROCESS(CLK_DAC, RST)
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BEGIN
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if (RST = '1') then
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SigmaLatch <= "0100000000";
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OUT_DAC <= '1';
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elsif (CLK_DAC'event and CLK_DAC = '1') then
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SigmaLatch <= SigmaAdder;
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OUT_DAC <= SigmaLatch(9);
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end if;
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END PROCESS;
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end Behavioral;
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