mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-02-04 07:32:37 +00:00
882 lines
18 KiB
Systemverilog
882 lines
18 KiB
Systemverilog
//============================================================================
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//
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//============================================================================
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module emu
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(
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//Master input clock
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input CLK_50M,
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//Async reset from top-level module.
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//Can be used as initial reset.
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input RESET,
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//Must be passed to hps_io module
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inout [45:0] HPS_BUS,
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//Base video clock. Usually equals to CLK_SYS.
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output CLK_VIDEO,
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//Multiple resolutions are supported using different CE_PIXEL rates.
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//Must be based on CLK_VIDEO
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output CE_PIXEL,
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//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
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//if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio.
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output [12:0] VIDEO_ARX,
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output [12:0] VIDEO_ARY,
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output [7:0] VGA_R,
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output [7:0] VGA_G,
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output [7:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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output VGA_DE, // = ~(VBlank | HBlank)
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output VGA_F1,
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output [1:0] VGA_SL,
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output VGA_SCALER, // Force VGA scaler
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input [11:0] HDMI_WIDTH,
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input [11:0] HDMI_HEIGHT,
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output HDMI_FREEZE,
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`ifdef MISTER_FB
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// Use framebuffer in DDRAM (USE_FB=1 in qsf)
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// FB_FORMAT:
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// [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
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// [3] : 0=16bits 565 1=16bits 1555
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// [4] : 0=RGB 1=BGR (for 16/24/32 modes)
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//
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// FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes)
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output FB_EN,
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output [4:0] FB_FORMAT,
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output [11:0] FB_WIDTH,
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output [11:0] FB_HEIGHT,
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output [31:0] FB_BASE,
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output [13:0] FB_STRIDE,
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input FB_VBL,
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input FB_LL,
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output FB_FORCE_BLANK,
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`ifdef MISTER_FB_PALETTE
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// Palette control for 8bit modes.
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// Ignored for other video modes.
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output FB_PAL_CLK,
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output [7:0] FB_PAL_ADDR,
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output [23:0] FB_PAL_DOUT,
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input [23:0] FB_PAL_DIN,
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output FB_PAL_WR,
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`endif
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`endif
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output LED_USER, // 1 - ON, 0 - OFF.
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// b[1]: 0 - LED status is system status OR'd with b[0]
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// 1 - LED status is controled solely by b[0]
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// hint: supply 2'b00 to let the system control the LED.
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output [1:0] LED_POWER,
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output [1:0] LED_DISK,
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// I/O board button press simulation (active high)
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// b[1]: user button
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// b[0]: osd button
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output [1:0] BUTTONS,
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input CLK_AUDIO, // 24.576 MHz
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output [15:0] AUDIO_L,
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output [15:0] AUDIO_R,
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output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
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output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
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//ADC
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inout [3:0] ADC_BUS,
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//SD-SPI
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output SD_SCK,
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output SD_MOSI,
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input SD_MISO,
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output SD_CS,
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input SD_CD,
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//High latency DDR3 RAM interface
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//Use for non-critical time purposes
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output DDRAM_CLK,
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input DDRAM_BUSY,
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output [7:0] DDRAM_BURSTCNT,
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output [28:0] DDRAM_ADDR,
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input [63:0] DDRAM_DOUT,
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input DDRAM_DOUT_READY,
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output DDRAM_RD,
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output [63:0] DDRAM_DIN,
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output [7:0] DDRAM_BE,
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output DDRAM_WE,
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//SDRAM interface with lower latency
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output SDRAM_CLK,
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output SDRAM_CKE,
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output [12:0] SDRAM_A,
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output [1:0] SDRAM_BA,
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inout [15:0] SDRAM_DQ,
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output SDRAM_DQML,
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output SDRAM_DQMH,
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output SDRAM_nCS,
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output SDRAM_nCAS,
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output SDRAM_nRAS,
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output SDRAM_nWE,
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`ifdef MISTER_DUAL_SDRAM
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//Secondary SDRAM
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//Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0
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input SDRAM2_EN,
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output SDRAM2_CLK,
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output [12:0] SDRAM2_A,
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output [1:0] SDRAM2_BA,
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inout [15:0] SDRAM2_DQ,
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output SDRAM2_nCS,
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output SDRAM2_nCAS,
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output SDRAM2_nRAS,
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output SDRAM2_nWE,
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`endif
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input UART_CTS,
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output UART_RTS,
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input UART_RXD,
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output UART_TXD,
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output UART_DTR,
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input UART_DSR,
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// Open-drain User port.
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// 0 - D+/RX
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// 1 - D-/TX
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// 2..6 - USR2..USR6
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// Set USER_OUT to 1 to read from USER_IN.
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input [6:0] USER_IN,
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output [6:0] USER_OUT,
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input OSD_STATUS
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);
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///////// Default values for ports not used in this core /////////
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assign ADC_BUS = 'Z;
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assign USER_OUT = '1;
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assign {UART_RTS, UART_TXD, UART_DTR} = 0;
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assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
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assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
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assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = '0;
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assign VGA_SCALER = 0;
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assign HDMI_FREEZE = 0;
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assign AUDIO_S = 1;
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assign AUDIO_L = AUDIO_R;
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//assign AUDIO_R = sound_pad;
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assign AUDIO_MIX = 0;
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assign LED_DISK = 0;
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assign LED_POWER = 0;
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assign BUTTONS = 0;
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//////////////////////////////////////////////////////////////////
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wire [1:0] ar = status[11:10];
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video_freak video_freak
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(
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.*,
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.VGA_DE_IN(VGA_DE),
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.VGA_DE(),
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.ARX((!ar) ? 12'd4 : (ar - 1'd1)),
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.ARY((!ar) ? 12'd3 : 12'd0),
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.CROP_SIZE(0),
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.CROP_OFF(0),
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.SCALE(status[13:12])
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);
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wire tape_play = status[14];
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wire tape_rewind = status[15];
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`include "build_id.v"
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localparam CONF_STR = {
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"Interact;;",
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"F,CINK7 ,Load tape;",
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"TE,Play;",
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"TF,Stop & Rewind;",
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"-;",
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"OAB,Aspect ratio,Original,Full Screen,[ARC1],[ARC2];",
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"O24,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%,CRT 75%;",
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"OCD,Scale,Normal,V-Integer,Narrower HV-Integer,Wider HV-Integer;",
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"-;",
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"O6,Test Pattern,Off,On;",
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"-;",
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"T0,Reset;",
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"R0,Reset and close OSD;",
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"V,v",`BUILD_DATE
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};
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wire forced_scandoubler;
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wire freeze_sync;
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wire [21:0] gamma_bus;
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wire [1:0] buttons;
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wire [31:0] status;
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wire [10:0] ps2_key;
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wire [15:0] joystick_0,joystick_1;
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wire [15:0] joystick_analog_0, joystick_analog_1;
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wire [7:0] paddle_0, paddle_1;
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wire ioctl_download;
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wire ioctl_wr;
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wire [15:0] ioctl_addr;
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wire [7:0] ioctl_data;
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wire [7:0] ioctl_index;
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hps_io #(.CONF_STR(CONF_STR)) hps_io
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(
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.clk_sys(clk_sys),
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.HPS_BUS(HPS_BUS),
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.EXT_BUS(),
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.gamma_bus(gamma_bus),
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.forced_scandoubler(forced_scandoubler),
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.buttons(buttons),
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.status(status),
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.status_menumask({status[5]}),
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.ioctl_download(ioctl_download),
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.ioctl_wr(ioctl_wr),
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.ioctl_addr(ioctl_addr),
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.ioctl_dout(ioctl_data),
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.ioctl_index(ioctl_index),
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.joystick_0(joystick_0),
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.joystick_1(joystick_1),
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.joystick_analog_0(joystick_analog_0),
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.joystick_analog_1(joystick_analog_1),
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.paddle_0(paddle_0),
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.paddle_1(paddle_1),
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.ps2_key(ps2_key)
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);
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wire rom_download = ioctl_download && (ioctl_index == 0);
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wire tape_download = ioctl_download && (ioctl_index != 0);
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/////////////////////// CLOCKS ///////////////////////////////
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wire clk_sys;
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wire locked;
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pll pll
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(
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.refclk(CLK_50M),
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.rst(0),
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.outclk_0(CLK_VIDEO),
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.outclk_1(clk_sys),
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.locked(locked)
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);
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wire reset = RESET | status[0] | buttons[1] | rom_download;
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wire rst_n = ~reset;
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// vm80a needs a nice long reset
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reg [7:0] rcnt = 8'h00;
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wire cpu_rst_n = (rcnt == 8'hFF);
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always @(posedge clk_sys)
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begin
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if (reset)
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rcnt <= 8'h00;
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else
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if (rcnt != 8'hFF) rcnt <= rcnt + 8'h01;
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end
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wire ph1;
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wire ph2;
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wire cbclk;
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wire pix_a;
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wire vid_sel;
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wire [11:0] vid_a;
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wire vid_sel_n;
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wire nrr_n;
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wire ce_n;
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wire pce;
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wire vid_ltc;
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wire ram_clk;
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wire brst;
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wire tpclk;
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wire cmp_blank;
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wire irq;
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wire inte;
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wire cmp_sync;
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wire hblank_n;
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wire vblank_n;
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wire hsync_n;
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wire vsync_n;
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video_timing timing
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(
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.clk_14m(clk_sys),
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.rst_n(rst_n),
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.ph1(ph1),
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.ph2(ph2),
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.cbclk(cbclk),
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.pix_a(pix_a),
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.vid_sel(vid_sel),
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.vid_a0(vid_a[0]),
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.vid_a1(vid_a[1]),
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.vid_a2(vid_a[2]),
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.vid_a3(vid_a[3]),
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.vid_a4(vid_a[4]),
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.vid_a5(vid_a[5]),
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.vid_a6(vid_a[6]),
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.vid_a7(vid_a[7]),
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.vid_a8(vid_a[8]),
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.vid_a9(vid_a[9]),
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.vid_a10(vid_a[10]),
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.vid_a11(vid_a[11]),
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.vid_sel_n(vid_sel_n),
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.nrr_n(nrr_n),
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.ce_n(ce_n),
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.pce(pce),
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.vid_ltc(vid_ltc),
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.ram_clk(ram_clk),
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.brst(brst),
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.tpclk(tpclk),
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.cmp_blank(cmp_blank),
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.irq(irq),
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.inte(inte),
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.cmp_sync(cmp_sync),
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.hblank_n(hblank_n),
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.vblank_n(vblank_n),
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.hsync_n(hsync_n),
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.vsync_n(vsync_n)
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);
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/////////////////// CPU ///////////////////
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wire [15:0] addr;
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reg [7:0] cpu_din;
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wire [7:0] cpu_dout;
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wire wr_n;
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wire ready;
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wire hold;
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wire rd;
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wire sync;
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wire vait;
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wire hlda;
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wire pin_aena;
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wire pin_dena;
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assign hold = 1'b0;
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assign ready = 1'b1;
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vm80a_core cpu
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(
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.pin_clk(clk_sys),
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.pin_f1(~ph2),
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.pin_f2(ph2),
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.pin_reset(~cpu_rst_n),
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.pin_a(addr),
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.pin_dout(cpu_dout),
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.pin_din(cpu_din),
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.pin_aena (pin_aena),
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.pin_dena (pin_dena),
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.pin_hold(hold),
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.pin_ready(ready),
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.pin_int(irq),
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.pin_wr_n(wr_n),
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.pin_dbin(rd),
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.pin_inte(inte),
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.pin_hlda(hlda),
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.pin_wait(vait),
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.pin_sync(sync)
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);
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//////// STATUS system control ////////////
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reg[7:0] cpu_status;
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wire status_inta = cpu_status[0];
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//wire status_wo_n = cpu_status[1];
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//wire status_stack = cpu_status[2];
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//wire status_hlta = cpu_status[3];
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//wire status_out = cpu_status[4];
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//wire status_m1 = cpu_status[5];
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//wire status_inp = cpu_status[6];
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//wire status_memr = cpu_status[7];
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always @(posedge clk_sys or negedge rst_n)
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begin
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reg old_sync;
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if (!rst_n)
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cpu_status <= 8'b0;
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else
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begin
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old_sync <= sync;
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if(~old_sync & sync)
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cpu_status <= cpu_dout;
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end
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end
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always_comb begin
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casez({status_inta, rom_e, ram_e, ~io_3800_r_n, ~io_3000_r_n})
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5'b1????: cpu_din <= 8'hFF;
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5'b00001: cpu_din <= io_rd_rtc_ad;
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5'b00010: cpu_din <= key_data;
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5'b00100: cpu_din <= ram_out;
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5'b01000: cpu_din <= rom_out;
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default: cpu_din <= 8'hFF;
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endcase
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end
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/////////////////// MEMORY ///////////////////
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// 1111110000000000
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// 5432109876543210
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// ROM A 0000H 0000000000000000
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// ROM B 0800H 0000100000000000
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// IO 10 1000H 0001000000000000
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// IO 18 1800H 0001100000000000
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// IO 20 2000H 0010000000000000
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// IO 28 2800H 0010100000000000
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// IO 30 3000H 0011000000000000
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// IO 38 3800H 0011100000000000
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// VRAM 4000H 0100000000000000
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// 49FFH 0100100111111111
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// RAM 4800H 0100101000000000
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wire rom_e = ~addr[15] & ~addr[14] & ~addr[13] & ~addr[12] & ~addr[11];
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wire [7:0] rom_out;
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dpram #(.ADDRWIDTH(12), .NUMWORDS(4096), .MEM_INIT_FILE("rtl/boot.mif")) rom
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(
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.clock(clk_sys),
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.address_a(ioctl_addr),
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.data_a(ioctl_data),
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.wren_a(rom_download && ioctl_wr),
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.address_b(addr[11:0]),
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.q_b(rom_out)
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);
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wire ram_e = ~addr[15] & addr[14];
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wire [7:0] ram_out;
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wire ram_w = ram_e & ~wr_n;
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wire [7:0] vid_out;
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dpram #(.ADDRWIDTH(14)) ram
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(
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.clock(clk_sys),
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.address_a(addr[13:0]),
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.data_a(cpu_dout),
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.wren_a(ram_w),
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.q_a(ram_out),
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.address_b({2'b0, vid_a[11:0]}),
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.q_b(vid_out)
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);
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/////////////////// Memory Mapped IO Registers ///////////////////
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// sure we could do this with some simple verilog conditionals, but digging the old-time TTL ICs
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wire io_0000_r_n;
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wire io_0800_r_n;
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wire io_1000_r_n;
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wire io_1800_r_n;
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wire io_2000_r_n;
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wire io_2800_r_n;
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wire io_3000_r_n;
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wire io_3800_r_n;
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wire io_0000_w_n;
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wire io_0800_w_n;
|
|
wire io_1000_w_n;
|
|
wire io_1800_w_n;
|
|
wire io_2000_w_n;
|
|
wire io_2800_w_n;
|
|
wire io_3000_w_n;
|
|
wire io_3800_w_n;
|
|
|
|
SN74LS138 IC25 (
|
|
.a(addr[11]),
|
|
.b(addr[12]),
|
|
.c(addr[13]),
|
|
.g1(rd),
|
|
.g2an(addr[15]),
|
|
.g2bn(addr[14]),
|
|
.y0n(io_0000_r_n),
|
|
.y1n(io_0800_r_n),
|
|
.y2n(io_1000_r_n),
|
|
.y3n(io_1800_r_n),
|
|
.y4n(io_2000_r_n),
|
|
.y5n(io_2800_r_n),
|
|
.y6n(io_3000_r_n),
|
|
.y7n(io_3800_r_n)
|
|
);
|
|
|
|
SN74LS138 IC26 (
|
|
.a(addr[11]),
|
|
.b(addr[12]),
|
|
.c(addr[13]),
|
|
.g1(~wr_n),
|
|
.g2an(addr[15]),
|
|
.g2bn(addr[14]),
|
|
.y0n(io_0000_w_n),
|
|
.y1n(io_0800_w_n),
|
|
.y2n(io_1000_w_n),
|
|
.y3n(io_1800_w_n),
|
|
.y4n(io_2000_w_n),
|
|
.y5n(io_2800_w_n),
|
|
.y6n(io_3000_w_n),
|
|
.y7n(io_3800_w_n)
|
|
);
|
|
|
|
|
|
//wire [7:0] io_rd_rtc_ad = {(io_wr_misc[7:6] ? (io_wr_misc[7:6] == 2'b10 ? rtc[7] : 1'b0) : tape_flux), rtc[6:0]};
|
|
wire [7:0] io_rd_rtc_ad;
|
|
always_comb
|
|
casez (io_wr_misc[7:3])
|
|
5'b00111 : io_rd_rtc_ad = {tape_flux, rtc[6:0]};
|
|
5'b10111 : io_rd_rtc_ad = rtc;
|
|
5'b?1111 : io_rd_rtc_ad = {1'b0, rtc[6:0]};
|
|
5'b??001 : io_rd_rtc_ad = joystick_0[4] ? 8'h00 : 8'h80;
|
|
5'b??010 : io_rd_rtc_ad = {~joystick_analog_0[7], joystick_analog_0[6:0]};
|
|
5'b??100 : io_rd_rtc_ad = joystick_1[4] ? 8'h00 : 8'h80;
|
|
5'b??101 : io_rd_rtc_ad = {~joystick_analog_1[7], joystick_analog_1[6:0]};
|
|
default: io_rd_rtc_ad = 8'h00;
|
|
endcase
|
|
|
|
|
|
wire rtc_clr = ~rst_n | io_wr_misc[6];
|
|
reg [7:0] rtc;
|
|
wire rtc_clk = io_wr_misc[6] ? 1'b0 : (io_wr_misc[7] ? pix_a : tpclk);
|
|
|
|
always@(negedge rtc_clk or posedge rtc_clr)
|
|
begin
|
|
if (rtc_clr)
|
|
begin
|
|
rtc <= 8'b0;
|
|
end
|
|
else
|
|
begin
|
|
rtc <= rtc + 1'b1;
|
|
end
|
|
end
|
|
|
|
wire [7:0] keys [7:0];
|
|
wire [7:0] key_data = keys[addr[3:0]];
|
|
|
|
keyboard keyboard
|
|
(
|
|
.clk_sys(clk_sys),
|
|
.rst_n(rst_n),
|
|
.ps2_key(ps2_key),
|
|
.joystick_0(joystick_0),
|
|
.joystick_1(joystick_1),
|
|
.keys(keys)
|
|
);
|
|
|
|
|
|
reg [7:0] io_wr_color_a_tape;
|
|
reg [7:0] io_wr_color_b_snd;
|
|
|
|
reg [7:0] io_wr_sound_a [3:0];
|
|
reg [7:0] io_wr_sound_b [3:0];
|
|
|
|
reg [7:0] io_wr_misc;
|
|
|
|
always@(posedge io_1000_w_n or negedge rst_n)
|
|
begin
|
|
if (!rst_n)
|
|
begin
|
|
io_wr_color_a_tape <= 8'b0;
|
|
end
|
|
else
|
|
begin
|
|
io_wr_color_a_tape <= cpu_dout;
|
|
end
|
|
end
|
|
|
|
always@(posedge io_1800_w_n or negedge rst_n)
|
|
begin
|
|
if (!rst_n)
|
|
begin
|
|
io_wr_color_b_snd <= 8'b0;
|
|
end
|
|
else
|
|
begin
|
|
io_wr_color_b_snd <= cpu_dout;
|
|
end
|
|
end
|
|
|
|
always@(posedge io_2000_w_n or negedge rst_n)
|
|
begin
|
|
if (!rst_n)
|
|
begin
|
|
io_wr_sound_a[2'b00] <= 8'b0;
|
|
io_wr_sound_a[2'b01] <= 8'b0;
|
|
io_wr_sound_a[2'b10] <= 8'b0;
|
|
io_wr_sound_a[2'b11] <= 8'b0;
|
|
end
|
|
else
|
|
begin
|
|
io_wr_sound_a[addr[1:0]] <= cpu_dout;
|
|
end
|
|
end
|
|
|
|
always@(posedge io_2800_w_n or negedge rst_n)
|
|
begin
|
|
if (!rst_n)
|
|
begin
|
|
io_wr_sound_b[2'b00] <= 8'b0;
|
|
io_wr_sound_b[2'b01] <= 8'b0;
|
|
io_wr_sound_b[2'b10] <= 8'b0;
|
|
io_wr_sound_b[2'b11] <= 8'b0;
|
|
end
|
|
else
|
|
begin
|
|
io_wr_sound_b[addr[1:0]] <= cpu_dout;
|
|
end
|
|
end
|
|
|
|
always@(posedge io_3000_w_n or negedge rst_n)
|
|
begin
|
|
if (!rst_n)
|
|
begin
|
|
io_wr_misc <= 8'b0;
|
|
end
|
|
else
|
|
begin
|
|
io_wr_misc <= cpu_dout;
|
|
end
|
|
end
|
|
|
|
|
|
/////////////////// Video ///////////////////
|
|
|
|
|
|
//// Test generator start
|
|
|
|
reg [7:0] vidtest_x;
|
|
reg [7:0] vidtest_y;
|
|
wire [6:0] vidtest_scanline = vid_a[11:5];
|
|
|
|
always@(posedge vid_ltc or negedge hblank_n)
|
|
begin
|
|
if (!hblank_n)
|
|
vidtest_x <= 8'b0;
|
|
else
|
|
vidtest_x <= vidtest_x + 1'b1;
|
|
end
|
|
|
|
always@(posedge hsync_n or negedge vblank_n)
|
|
begin
|
|
if (!vblank_n)
|
|
vidtest_y <= 8'b0;
|
|
else
|
|
vidtest_y <= vidtest_y + 1'b1;
|
|
end
|
|
|
|
//// Test generator end
|
|
|
|
|
|
reg [7:0] pix_byte;
|
|
wire pix_en = vid_sel & vid_ltc & ~(ce_n | pce);
|
|
|
|
always@(posedge pix_en or negedge rst_n)
|
|
begin
|
|
if (!rst_n)
|
|
begin
|
|
pix_byte <= 8'b0;
|
|
end
|
|
else
|
|
begin
|
|
pix_byte <= vid_out;
|
|
end
|
|
end
|
|
|
|
reg [3:0] pix_nib;
|
|
|
|
always@(posedge vid_sel_n or negedge rst_n)
|
|
begin
|
|
if (!rst_n)
|
|
begin
|
|
pix_nib <= 4'b0;
|
|
end
|
|
else
|
|
begin
|
|
pix_nib <= pix_byte[7:4];
|
|
end
|
|
end
|
|
|
|
reg [7:0] R;
|
|
reg [7:0] G;
|
|
reg [7:0] B;
|
|
|
|
wire [1:0] pix = vid_sel ? (pix_a ? pix_nib[3:2] : pix_nib[1:0]) : (pix_a ? pix_byte[3:2] : pix_byte[1:0]);
|
|
|
|
wire [2:0] cr [3:0];
|
|
|
|
assign cr[2'b00] = io_wr_color_a_tape[2:0];
|
|
assign cr[2'b01] = io_wr_color_b_snd[2:0];
|
|
assign cr[2'b10] = io_wr_color_a_tape[5:3];
|
|
assign cr[2'b11] = io_wr_color_b_snd[5:3];
|
|
|
|
wire [2:0] color = cr[pix];
|
|
wire color_intensity = (pix == 2'b10) ? io_wr_color_b_snd[6] : 1'b0;
|
|
|
|
wire test_pattern = status[6];
|
|
|
|
always@(posedge vid_ltc or negedge rst_n)
|
|
begin
|
|
if (!rst_n)
|
|
begin
|
|
R <= 8'b0;
|
|
G <= 8'b0;
|
|
B <= 8'b0;
|
|
end
|
|
else
|
|
begin
|
|
if (cmp_blank)
|
|
begin
|
|
R <= 8'b0;
|
|
G <= 8'b0;
|
|
B <= 8'b0;
|
|
end
|
|
else if (test_pattern & (vidtest_x === 8'd0))
|
|
begin
|
|
R <= 8'h00; //darkgreen
|
|
G <= 8'h64;
|
|
B <= 8'h00;
|
|
end
|
|
else if (test_pattern & (vidtest_x === 8'd110))
|
|
begin
|
|
R <= 8'h7c; //lawngreen
|
|
G <= 8'hfc;
|
|
B <= 8'h00;
|
|
end
|
|
else if (test_pattern & (vidtest_scanline === 7'd0))
|
|
begin
|
|
R <= 8'h8A; //blueviolet
|
|
G <= 8'h2B;
|
|
B <= 8'hE2;
|
|
end
|
|
else if (test_pattern & (vidtest_scanline === 7'd75))
|
|
begin
|
|
R <= 8'h1e; //dodgerblue
|
|
G <= 8'h90;
|
|
B <= 8'hff;
|
|
end
|
|
else
|
|
begin
|
|
if (color_intensity)
|
|
begin
|
|
if (test_pattern)
|
|
begin
|
|
R <= 8'h7c; //lawngreen
|
|
G <= 8'hfc;
|
|
B <= 8'h00;
|
|
end
|
|
else
|
|
begin
|
|
R <= {1'b0, {7{color[0]}}};
|
|
G <= {1'b0, {7{color[1]}}};
|
|
B <= {1'b0, {7{color[2]}}};
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
R <= {8{color[0]}};
|
|
G <= {8{color[1]}};
|
|
B <= {8{color[2]}};
|
|
end
|
|
end
|
|
end
|
|
end
|
|
|
|
wire [2:0] scale = status[4:2];
|
|
wire [2:0] sl = scale ? scale - 1'd1 : 3'd0;
|
|
|
|
assign VGA_F1 = 0;
|
|
assign VGA_SL = sl[1:0];
|
|
|
|
video_mixer #(.LINE_LENGTH(112), .GAMMA(1)) video_mixer
|
|
(
|
|
.*,
|
|
.ce_pix(vid_ltc),
|
|
.HSync(~hsync_n),
|
|
.VSync(~vsync_n),
|
|
.HBlank(~hblank_n),
|
|
.VBlank(~vblank_n),
|
|
.hq2x(scale == 1),
|
|
.scandoubler(|scale || forced_scandoubler)
|
|
);
|
|
|
|
|
|
//// Tape Loading
|
|
|
|
wire [15:0] tape_addr;
|
|
wire [7:0] tape_data;
|
|
reg [15:0] tape_end;
|
|
|
|
dpram #(.ADDRWIDTH(16)) tape
|
|
(
|
|
.clock(CLK_VIDEO),
|
|
.address_a(ioctl_addr),
|
|
.data_a(ioctl_data),
|
|
.wren_a(tape_download && ioctl_wr),
|
|
|
|
.address_b(tape_addr),
|
|
.q_b(tape_data)
|
|
);
|
|
|
|
always@(posedge CLK_VIDEO or negedge rst_n)
|
|
begin
|
|
if (!rst_n)
|
|
begin
|
|
tape_end <= 16'b0;
|
|
end
|
|
else
|
|
begin
|
|
if (tape_download) tape_end <= ioctl_addr;
|
|
end
|
|
end
|
|
|
|
wire tape_playing;
|
|
wire tape_flux;
|
|
|
|
cassette cassette(
|
|
.clk(clk_sys),
|
|
.rst_n(rst_n),
|
|
.play(tape_play),
|
|
.rewind(tape_rewind),
|
|
.playing(tape_playing),
|
|
.motor(io_wr_color_a_tape[6]),
|
|
|
|
.tape_addr(tape_addr),
|
|
.tape_data(tape_data),
|
|
.tape_end(tape_end),
|
|
|
|
.flux(tape_flux),
|
|
.audio(AUDIO_R)
|
|
);
|
|
|
|
assign LED_USER = tape_playing;
|
|
|
|
endmodule
|