mirror of
https://github.com/Gehstock/Mist_FPGA.git
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117 lines
2.7 KiB
Systemverilog
117 lines
2.7 KiB
Systemverilog
module OricAtmos_MiST(
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input CLOCK_27,
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output [5:0] VGA_R,
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output [5:0] VGA_G,
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output [5:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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output LED,
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input UART_RXD,
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output UART_TXD,
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output AUDIO_L,
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output AUDIO_R,
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input SPI_SCK,
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output SPI_DO,
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input SPI_DI,
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input SPI_SS2,
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input SPI_SS3,
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input CONF_DATA0
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);
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`include "build_id.v"
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localparam CONF_STR = {
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"OricAtmos;;",
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"O23,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;",
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"T9,Reset;",
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"V,v1.00.",`BUILD_DATE
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};
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wire clk_24;
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wire key_pressed;
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wire [7:0] key_code;
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wire key_strobe;
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wire key_extended;
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wire r, g, b;
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wire hs, vs;
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wire [1:0] buttons, switches;
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wire ypbpr;
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wire scandoublerD;
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wire [31:0] status;
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wire [15:0] audio;
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assign LED = 1'b1;
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assign AUDIO_R = AUDIO_L;
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pll pll (
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.inclk0 (CLOCK_27 ),
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.c0 (clk_24 )
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);
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user_io #(
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.STRLEN (($size(CONF_STR)>>3)))
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user_io(
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.clk_sys (clk_24 ),
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.conf_str (CONF_STR ),
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.SPI_CLK (SPI_SCK ),
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.SPI_SS_IO (CONF_DATA0 ),
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.SPI_MISO (SPI_DO ),
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.SPI_MOSI (SPI_DI ),
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.buttons (buttons ),
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.switches (switches ),
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.scandoubler_disable (scandoublerD ),
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.ypbpr (ypbpr ),
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.key_strobe (key_strobe ),
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.key_pressed (key_pressed ),
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.key_extended (key_extended ),
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.key_code (key_code ),
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.status (status )
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);
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mist_video #(.COLOR_DEPTH(3)) mist_video(
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.clk_sys (clk_24 ),
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.SPI_SCK (SPI_SCK ),
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.SPI_SS3 (SPI_SS3 ),
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.SPI_DI (SPI_DI ),
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.R ({r,r,r} ),
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.G ({g,g,g} ),
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.B ({b,b,b} ),
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.HSync (hs ),
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.VSync (vs ),
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.VGA_R (VGA_R ),
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.VGA_G (VGA_G ),
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.VGA_B (VGA_B ),
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.VGA_VS (VGA_VS ),
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.VGA_HS (VGA_HS ),
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.ce_divider (1'b0 ),
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.scandoubler_disable(scandoublerD ),
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.scanlines (scandoublerD ? 2'b00 : status[4:3]),
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.ypbpr (ypbpr )
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);
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oricatmos oricatmos(
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.RESET (status[0] | status[9] | buttons[1]),
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.key_pressed (key_pressed ),
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.key_code (key_code ),
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.key_extended (key_extended ),
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.key_strobe (key_strobe ),
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.PSG_OUT (audio ),
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.VIDEO_R (r ),
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.VIDEO_G (g ),
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.VIDEO_B (b ),
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.VIDEO_HSYNC (hs ),
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.VIDEO_VSYNC (vs ),
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.K7_TAPEIN (UART_RXD ),
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.K7_TAPEOUT (UART_TXD ),
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.clk_in (clk_24 )
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);
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dac #(
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.c_bits (16 ))
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audiodac(
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.clk_i (clk_24 ),
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.res_n_i (1 ),
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.dac_i (audio ),
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.dac_o (AUDIO_L )
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);
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endmodule
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