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https://github.com/Gehstock/Mist_FPGA.git
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216 lines
6.4 KiB
VHDL
216 lines
6.4 KiB
VHDL
--
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-- video.vhd
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--
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-- Manage video attribute
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--
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-- Copyright (C)2001 - 2005 SEILEBOST
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-- All rights reserved.
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--
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-- $Id: video.vhd, v0.01 2005/01/01 00:00:00 SEILEBOST $
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--
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-- TODO :
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-- Remark :
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_STD.all;
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entity video is
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port ( RESETn : in std_logic;
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CLK_PIXEL : in std_logic;
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CLK_FLASH : in std_logic;
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-- delete 17/11/2009 FLASH_SEL : in std_logic;
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BLANKINGn : in std_logic;
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RELOAD_SEL : in std_logic;
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DATABUS : in std_logic_vector(7 downto 0);
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ATTRIB_DEC : in std_logic;
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DATABUS_EN : in std_logic;
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LDFROMBUS : in std_logic;
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LD_REG_0 : in std_logic;
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RELD_REG : in std_logic;
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CHROWCNT : in std_logic_vector(2 downto 0);
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RGB : out std_logic_vector(2 downto 0);
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FREQ_SEL : out std_logic;
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TXTHIR_SEL : out std_logic;
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isAttrib : out std_logic;
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DBLSTD_SEL : out std_logic;
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VAP2 : out std_logic_vector(15 downto 0)
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);
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end entity video;
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architecture video_arch of video is
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-- locals signals
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signal lDATABUS : std_logic_vector(7 downto 0);
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signal lSHFREG : std_logic_vector(5 downto 0);
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signal lREGHOLD : std_logic_vector(5 downto 0);
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signal lRGB : std_logic_vector(2 downto 0);
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signal lCLK_REG : std_logic_vector(3 downto 0);
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signal lREG_0 : std_logic_vector(2 downto 0);
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signal lREG_1 : std_logic_vector(2 downto 0);
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signal lREG_2 : std_logic_vector(2 downto 0);
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signal lREG_3 : std_logic_vector(2 downto 0);
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signal tmp : std_logic_vector(1 downto 0);
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signal lADD : std_logic_vector(1 downto 0);
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signal lDIN : std_logic; -- SET INVERSE SIGNAL
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signal lSHFVIDEO : std_logic;
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signal lBGFG_SEL : std_logic;
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signal lFLASH_SEL : std_logic;
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signal lIsATTRIB : std_logic;
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begin
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-- Latch data from Data Bus
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u_data_bus: PROCESS( DATABUS, DATABUS_EN)
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BEGIN
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-- Correctif 03/02/09 if (DATABUS_EN = '1') then
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if (rising_edge(DATABUS_EN)) then
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lDATABUS <= DATABUS;
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end if;
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END PROCESS;
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-- Ajout du 04/02/09 / Commentaire le 05/12/09
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--isAttrib <= not lDATABUS(6); -- =1 is an attribut, = 0 is not an attribut
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-- Decode register
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u_attr_dec: PROCESS(lDATABUS, ATTRIB_DEC)
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BEGIN
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lCLK_REG <= "0000"; -- Ajout 11/11/09
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if rising_edge(ATTRIB_DEC) then
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if (lDATABUS(6 downto 5) = "00") then
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case lDATABUS(4 downto 3) is
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when "00" => lCLK_REG <= "0001";
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when "01" => lCLK_REG <= "0010";
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when "10" => lCLK_REG <= "0100";
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when "11" => lCLK_REG <= "1000";
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when others => lCLK_REG <= "1111"; -- 11/11/09 null;
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end case;
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end if;
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end if;
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END PROCESS;
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-- ajout le 05/12/09
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u_isattrib : PROCESS(DATABUS_EN, ATTRIB_DEC, RESETn)
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BEGIN
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if (RESETn = '0') then
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lIsATTRIB <= '0';
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elsif rising_edge(ATTRIB_DEC) then
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lIsATTRIB <= not (DATABUS(6) or DATABUS(5)); -- =1 is an attribut, = 0 is not an attribut
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end if;
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END PROCESS;
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-- Assignation
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isAttrib <= lIsATTRIB;
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-- get value for register number 0 : INK
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u_ld_reg0: PROCESS(lCLK_REG, RELOAD_SEL, lDATABUS, RESETn)
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BEGIN
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-- Ajout du 17/11/2009
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if (RESETn = '0') then
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lREG_0 <= "000";
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elsif (RELOAD_SEL = '1') then
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lREG_0 <= "000";
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-- le 17/11/2009 elsif (lCLK_REG(0) = '1') then
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elsif rising_edge(lCLK_REG(0)) then
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lREG_0 <= lDATABUS(2 downto 0);
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end if;
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END PROCESS;
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-- get value for register number 1 : STYLE : Alt/std, Dbl/std, Flash sel
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u_ld_reg1: PROCESS(lCLK_REG, RELOAD_SEL, lDATABUS, RESETN)
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BEGIN
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-- Ajout du 17/11/2009
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if (RESETn = '0') then
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lREG_1 <= "000";
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elsif (RELOAD_SEL = '1') then
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lREG_1 <= "000";
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-- le 17/11/2009 elsif (lCLK_REG(1) = '1') then
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elsif rising_edge(lCLK_REG(1)) then
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lREG_1 <= lDATABUS(2 downto 0);
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end if;
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END PROCESS;
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-- get value for register number 2 : PAPER
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u_ld_reg2: PROCESS(lCLK_REG, RELOAD_SEL, lDATABUS, RESETN)
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BEGIN
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-- Ajout du 17/11/2009
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if (RESETn = '0') then
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lREG_2 <= "111";
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elsif (RELOAD_SEL = '1') then
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lREG_2 <= "111";
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-- le 17/11/2009 elsif (lCLK_REG(2) = '1') then
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elsif rising_edge(lCLK_REG(2)) then
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lREG_2 <= lDATABUS(2 downto 0);
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end if;
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END PROCESS;
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-- get value for register number 3 : Mode
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u_ld_reg3: PROCESS(lCLK_REG, lDATABUS, RESETn)
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BEGIN
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if (RESETn = '0') then
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lREG_3 <= "000";
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-- modif 04/02/09 elsif (lCLK_REG(3) = '1') then
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elsif rising_edge(lCLK_REG(3)) then
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lREG_3 <= lDATABUS(2 downto 0);
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end if;
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END PROCESS;
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-- hold data value
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u_hold_reg: PROCESS( LD_REG_0, LDFROMBUS, lDATABUS)
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BEGIN
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-- Chargement si attribut
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if (LD_REG_0 = '1') then
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lREGHOLD <= (OTHERS => '0');
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elsif (rising_edge(LDFROMBUS)) then
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lREGHOLD <= lDATABUS(5 downto 0);
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lDIN <= lDATABUS(7); -- Ajout du 15/12/2009
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end if;
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---mise en commentaire 15/12/2009 lDIN <= lDATABUS(7);
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END PROCESS;
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-- shift data for video
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u_shf_reg: PROCESS(RELD_REG, CLK_PIXEL, lREGHOLD)
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BEGIN
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-- Chargement du shifter avant le front montant de PHI2
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if (RELD_REG = '1') then
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lSHFREG <= lREGHOLD;
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-- 6 bits à envoyer
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elsif (rising_edge(CLK_PIXEL)) then
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lSHFVIDEO <= lSHFREG(5);
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lSHFREG <= lSHFREG(4 downto 0) & '0';
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end if;
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END PROCESS;
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lFLASH_SEL <= lREG_1(2);
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lBGFG_SEL <= NOT(lSHFVIDEO) when ( (CLK_FLASH = '1') AND (lFLASH_SEL = '1') ) else lSHFVIDEO;
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-- le 17/11/2009 : lBGFG_SEL <= NOT(lSHFVIDEO) when ( (CLK_FLASH = '1') AND (FLASH_SEL = '1') ) else lSHFVIDEO;
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-- lBGFG_SEL <= lSHFVIDEO and not ( CLK_FLASH AND FLASH_SEL );
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-- local assign for R(ed)G(reen)B(lue) signal
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lRGB <= lREG_0 when lBGFG_SEL = '0' else lREG_2;
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-- Assign out signal
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RGB <= lRGB when (lDIN = '0' and BLANKINGn = '1') else
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not(lRGB) when (lDIN = '1' and BLANKINGn = '1') else
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"000";
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DBLSTD_SEL <= lREG_1(1); -- Double/Standard height character select
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FREQ_SEL <= lREG_3(1); -- Frenquecy video (50/60Hz) select
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TXTHIR_SEL <= lREG_3(2); -- Texte/Hires mode select
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-- Compute offset
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tmp <= lREG_3(2) & lREG_1(0);
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with tmp select
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lADD <= "01" when "00", -- TXT & STD
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"10" when "01", -- TXT & ALT
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"10" when "10", -- HIRES & STD
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"11" when "11", -- HIRES & ALT
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"01" when others; -- Du fait que le design original de l'ULA
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-- n'a pas de reset, nous supposerons que
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-- l'ULA est en mode text et standard
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-- Generate Address Phase 2
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VAP2 <= "10" & not lREG_3(2) & '1' & lADD & lDATABUS(6 downto 0) & CHROWCNT;
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end architecture video_arch;
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