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274 lines
10 KiB
VHDL
274 lines
10 KiB
VHDL
-------------------------------------------------------------------------------
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-- CPU86 - VHDL CPU8088 IP core --
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-- Copyright (C) 2002-2008 HT-LAB --
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-- --
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-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
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-- Web : http://www.ht-lab.com --
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-- --
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-- CPU86 is released as open-source under the GNU GPL license. This means --
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-- that designs based on CPU86 must be distributed in full source code --
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-- under the same license. Contact HT-Lab for commercial applications where --
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-- source-code distribution is not desirable. --
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-- --
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-------------------------------------------------------------------------------
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-- --
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-- This library is free software; you can redistribute it and/or --
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-- modify it under the terms of the GNU Lesser General Public --
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-- License as published by the Free Software Foundation; either --
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-- version 2.1 of the License, or (at your option) any later version. --
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-- --
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-- This library is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
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-- Lesser General Public License for more details. --
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-- --
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-- Full details of the license can be found in the file "copying.txt". --
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-- --
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-- You should have received a copy of the GNU Lesser General Public --
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-- License along with this library; if not, write to the Free Software --
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
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-- --
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-------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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USE work.cpu86pack.ALL;
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USE work.cpu86instr.ALL;
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ENTITY cpu86 IS
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PORT(
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clk : IN std_logic;
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dbus_in : IN std_logic_vector (7 DOWNTO 0);
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intr : IN std_logic;
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nmi : IN std_logic;
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por : IN std_logic;
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abus : OUT std_logic_vector (19 DOWNTO 0);
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dbus_out : OUT std_logic_vector (7 DOWNTO 0);
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cpuerror : OUT std_logic;
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inta : OUT std_logic;
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iom : OUT std_logic;
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rdn : OUT std_logic;
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resoutn : OUT std_logic;
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wran : OUT std_logic;
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wrn : OUT std_logic
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);
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END cpu86 ;
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ARCHITECTURE struct OF cpu86 IS
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SIGNAL biu_error : std_logic;
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SIGNAL clrop : std_logic;
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SIGNAL dbusdp_out : std_logic_vector(15 DOWNTO 0);
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SIGNAL decode_state : std_logic;
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SIGNAL eabus : std_logic_vector(15 DOWNTO 0);
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SIGNAL flush_ack : std_logic;
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SIGNAL flush_coming : std_logic;
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SIGNAL flush_req : std_logic;
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SIGNAL instr : instruction_type;
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SIGNAL inta1 : std_logic;
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SIGNAL intack : std_logic;
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SIGNAL iomem : std_logic;
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SIGNAL irq_blocked : std_logic;
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SIGNAL irq_req : std_logic;
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SIGNAL latcho : std_logic;
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SIGNAL mdbus_out : std_logic_vector(15 DOWNTO 0);
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SIGNAL opc_req : std_logic;
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SIGNAL path : path_in_type;
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SIGNAL proc_error : std_logic;
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SIGNAL read_req : std_logic;
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SIGNAL reset : std_logic;
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SIGNAL rw_ack : std_logic;
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SIGNAL segbus : std_logic_vector(15 DOWNTO 0);
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SIGNAL status : status_out_type;
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SIGNAL word : std_logic;
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SIGNAL write_req : std_logic;
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SIGNAL wrpath : write_in_type;
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-- Component Declarations
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COMPONENT biu
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PORT (
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clk : IN std_logic ;
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csbus : IN std_logic_vector (15 DOWNTO 0);
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dbus_in : IN std_logic_vector (7 DOWNTO 0);
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dbusdp_in : IN std_logic_vector (15 DOWNTO 0);
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decode_state : IN std_logic ;
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flush_coming : IN std_logic ;
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flush_req : IN std_logic ;
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intack : IN std_logic ;
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intr : IN std_logic ;
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iomem : IN std_logic ;
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ipbus : IN std_logic_vector (15 DOWNTO 0);
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irq_block : IN std_logic ;
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nmi : IN std_logic ;
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opc_req : IN std_logic ;
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read_req : IN std_logic ;
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reset : IN std_logic ;
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status : IN status_out_type ;
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word : IN std_logic ;
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write_req : IN std_logic ;
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abus : OUT std_logic_vector (19 DOWNTO 0);
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biu_error : OUT std_logic ;
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dbus_out : OUT std_logic_vector (7 DOWNTO 0);
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flush_ack : OUT std_logic ;
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instr : OUT instruction_type ;
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inta : OUT std_logic ;
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inta1 : OUT std_logic ;
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iom : OUT std_logic ;
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irq_req : OUT std_logic ;
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latcho : OUT std_logic ;
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mdbus_out : OUT std_logic_vector (15 DOWNTO 0);
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rdn : OUT std_logic ;
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rw_ack : OUT std_logic ;
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wran : OUT std_logic ;
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wrn : OUT std_logic
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);
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END COMPONENT;
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COMPONENT datapath
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PORT (
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clk : IN std_logic ;
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clrop : IN std_logic ;
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instr : IN instruction_type ;
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iomem : IN std_logic ;
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mdbus_in : IN std_logic_vector (15 DOWNTO 0);
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path : IN path_in_type ;
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reset : IN std_logic ;
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wrpath : IN write_in_type ;
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dbusdp_out : OUT std_logic_vector (15 DOWNTO 0);
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eabus : OUT std_logic_vector (15 DOWNTO 0);
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segbus : OUT std_logic_vector (15 DOWNTO 0);
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status : OUT status_out_type
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);
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END COMPONENT;
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COMPONENT proc
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PORT (
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clk : IN std_logic ;
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flush_ack : IN std_logic ;
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instr : IN instruction_type ;
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inta1 : IN std_logic ;
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irq_req : IN std_logic ;
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latcho : IN std_logic ;
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reset : IN std_logic ;
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rw_ack : IN std_logic ;
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status : IN status_out_type ;
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clrop : OUT std_logic ;
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decode_state : OUT std_logic ;
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flush_coming : OUT std_logic ;
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flush_req : OUT std_logic ;
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intack : OUT std_logic ;
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iomem : OUT std_logic ;
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irq_blocked : OUT std_logic ;
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opc_req : OUT std_logic ;
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path : OUT path_in_type ;
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proc_error : OUT std_logic ;
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read_req : OUT std_logic ;
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word : OUT std_logic ;
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write_req : OUT std_logic ;
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wrpath : OUT write_in_type
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);
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END COMPONENT;
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BEGIN
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-- synchronous reset
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-- Internal use active high, external use active low
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-- Async Asserted, sync negated
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process (clk, por)
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begin
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if por='1' then
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reset <= '1';
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resoutn <= '0';
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elsif rising_edge(clk) then
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reset <= '0';
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resoutn <= '1';
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end if;
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end process;
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cpuerror <= proc_error OR biu_error;
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cpubiu : biu
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PORT MAP (
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clk => clk,
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csbus => segbus,
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dbus_in => dbus_in,
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dbusdp_in => dbusdp_out,
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decode_state => decode_state,
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flush_coming => flush_coming,
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flush_req => flush_req,
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intack => intack,
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intr => intr,
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iomem => iomem,
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ipbus => eabus,
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irq_block => irq_blocked,
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nmi => nmi,
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opc_req => opc_req,
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read_req => read_req,
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reset => reset,
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status => status,
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word => word,
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write_req => write_req,
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abus => abus,
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biu_error => biu_error,
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dbus_out => dbus_out,
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flush_ack => flush_ack,
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instr => instr,
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inta => inta,
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inta1 => inta1,
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iom => iom,
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irq_req => irq_req,
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latcho => latcho,
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mdbus_out => mdbus_out,
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rdn => rdn,
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rw_ack => rw_ack,
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wran => wran,
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wrn => wrn
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);
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cpudpath : datapath
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PORT MAP (
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clk => clk,
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clrop => clrop,
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instr => instr,
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iomem => iomem,
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mdbus_in => mdbus_out,
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path => path,
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reset => reset,
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wrpath => wrpath,
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dbusdp_out => dbusdp_out,
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eabus => eabus,
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segbus => segbus,
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status => status
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);
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cpuproc : proc
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PORT MAP (
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clk => clk,
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flush_ack => flush_ack,
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instr => instr,
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inta1 => inta1,
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irq_req => irq_req,
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latcho => latcho,
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reset => reset,
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rw_ack => rw_ack,
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status => status,
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clrop => clrop,
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decode_state => decode_state,
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flush_coming => flush_coming,
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flush_req => flush_req,
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intack => intack,
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iomem => iomem,
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irq_blocked => irq_blocked,
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opc_req => opc_req,
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path => path,
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proc_error => proc_error,
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read_req => read_req,
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word => word,
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write_req => write_req,
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wrpath => wrpath
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);
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END struct;
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