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96 lines
3.2 KiB
VHDL
96 lines
3.2 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- Synchronous 8-Bit Binary Counter with preset.
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--
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-- $Id: ladybug_counter.vhd,v 1.9 2005/10/10 21:59:13 arnim Exp $
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity counter is
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port (
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ck_i : in std_logic;
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ck_en_i : in std_logic;
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reset_n_i : in std_logic;
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load_i : in std_logic;
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preset_i : in std_logic_vector(7 downto 0);
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q_o : out std_logic_vector(7 downto 0);
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rise_q_o : out std_logic_vector(7 downto 0);
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d_o : out std_logic_vector(7 downto 0);
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co_o : out std_logic
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);
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end counter;
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architecture rtl of counter is
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signal cnt_q : std_logic_vector(7 downto 0);
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signal cnt_s : std_logic_vector(7 downto 0);
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begin
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seq: process (ck_i, reset_n_i)
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begin
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if reset_n_i = '0' then
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cnt_q <= (others => '0');
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elsif rising_edge(ck_i) then
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cnt_q <= cnt_s;
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end if;
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end process seq;
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adder: process (ck_en_i, cnt_q, load_i, preset_i)
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begin
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cnt_s <= cnt_q;
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if ck_en_i = '1' then
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if load_i = '1' then
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cnt_s <= preset_i;
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else
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cnt_s <= cnt_q + 1;
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end if;
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end if;
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end process adder;
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co_o <= '1' when cnt_q = x"FF" else '0';
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rise_q_o <= cnt_s and not cnt_q;
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q_o <= cnt_q;
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d_o <= cnt_s;
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end rtl;
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