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36 lines
1.2 KiB
VHDL
36 lines
1.2 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
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--
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-------------------------------------------------------------------------------
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--
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-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
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--
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-- Note that this file is copyrighted, and is not supposed to be used in other
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-- projects without written permission from the author.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package sid_debug_pkg is
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type t_voice_debug is record
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state : unsigned(1 downto 0);
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enveloppe : unsigned(7 downto 0);
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pre15 : unsigned(14 downto 0);
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pre5 : unsigned(4 downto 0);
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presc : unsigned(14 downto 0);
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gate : std_logic;
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attack : std_logic_vector(3 downto 0);
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decay : std_logic_vector(3 downto 0);
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sustain : std_logic_vector(3 downto 0);
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release : std_logic_vector(3 downto 0);
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end record;
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type t_voice_debug_array is array(natural range <>) of t_voice_debug;
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end;
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