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47 lines
1.2 KiB
Verilog
47 lines
1.2 KiB
Verilog
// memory block transfer routine
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// L.C.Ashmore feb17
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//
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// PRG T64 CRT TAP files load to intermediate buffer 0x200000 (2m)
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//
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// this routine reads 1st 16bytes to determine file type then either:
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// 1, if CRT or TAP move to 0x100000 (1m) and sets cartridge or tap attached flags
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// 2, if PRG or T64 moves directly into c64 memory map (injection)
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// T64 format pain in the arse so only basic function !!
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module block_transfer
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(
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input clk32,
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input [31:0] addr_total_size,
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input sdram_we,
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input sdram_data_out,
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output cart_attached,
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output reg [24:0] sdram_read_addr,
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output reg [24:0] sdram_write_addr,
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inout reg [7:0] sdram_data
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);
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localparam buffer_address2m = 'h200000;
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localparam buffer_address1m = 'h100000;
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reg [24:0] block_addr;
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//reg [24:0] sdram_read_addr;
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//reg [24:0] sdram_write_addr;
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//reg [7:0] sdram_data;
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reg transfer_active;
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reg read_flag;
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always @(negedge clk32)
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begin
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if (sdram_we == 1 && transfer_active && !read_flag) //sdram in read cycle - not yet read
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begin
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sdram_read_addr <= block_addr + buffer_address2m;
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sdram_data <= sdram_data_out;
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read_flag = 1;
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end
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if (sdram_we == 0 && read_flag)
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begin
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sdram_write_addr <= block_addr +buffer_address1m;
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end
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end
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endmodule
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