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15 lines
215 B
Verilog
15 lines
215 B
Verilog
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module eu_rom(
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input clka,
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input [11:0] addra,
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output reg [31:0] douta
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);
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reg [31:0] memory[3961:0];
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initial $readmemb("microcode.mem", memory);
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always @(posedge clka)
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douta <= memory[addra];
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endmodule
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