mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-05-01 14:16:34 +00:00
281 lines
6.7 KiB
VHDL
281 lines
6.7 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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package pace_pkg is
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--
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-- PACE constants which *MUST* be defined
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--
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type PACETargetType is
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(
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PACE_TARGET_NANOBOARD_NB1,
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PACE_TARGET_DE0,
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PACE_TARGET_DE0_CV, -- 5CEBA4
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PACE_TARGET_DE0_NANO, -- EP4CE22
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PACE_TARGET_DE1,
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PACE_TARGET_DE2,
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PACE_TARGET_DE2_70, -- EP2C70
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PACE_TARGET_DE2_115, -- EP4CE115
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PACE_TARGET_P2, -- A02 build
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PACE_TARGET_P2A, -- A04/A build (SRAM byte selects)
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PACE_TARGET_P3M,
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PACE_TARGET_S3A_700, -- Spartan 3A/N Starter Kit
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PACE_TARGET_RC10,
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PACE_TARGET_NX2_12,
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PACE_TARGET_NEXYS_3, -- Digilent S6 board
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PACE_TARGET_CYC3DEV,
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PACE_TARGET_CYC5GXDEV,
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PACE_TARGET_COCO3PLUS,
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PACE_TARGET_S5A,
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PACE_TARGET_CARTEBLANCHE_250,
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PACE_TARGET_CARTEBLANCHE_500,
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PACE_TARGET_BEMICRO,
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PACE_TARGET_OPENEP3C16,
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PACE_TARGET_MIST,
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PACE_TARGET_CHAMELEON64,
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PACE_TARGET_RETRORAMBLINGS_CYC3, -- Generic EP3C25 board with custom io boards
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PACE_TARGET_S5A_R2_EP4C,
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PACE_TARGET_S5A_R2_EP3SL,
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PACE_TARGET_S5A_R2B0_EP4C,
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PACE_TARGET_S5A_R2B0_EP3SL,
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PACE_TARGET_S5A_R2C0_EP4C,
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PACE_TARGET_S5A_R2C0_EP3SL,
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PACE_TARGET_S5L_A0_EP4C,
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PACE_TARGET_S5L_A0_EP3SL,
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PACE_TARGET_NAVICO_ROCKY,
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PACE_TARGET_NGPACE,
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PACE_TARGET_S6M_A0
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);
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type PACEFpgaVendor_t is
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(
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PACE_FPGA_VENDOR_ALTERA,
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PACE_FPGA_VENDOR_XILINX,
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PACE_FPGA_VENDOR_LATTICE
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);
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type PACEFpgaFamily_t is
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(
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PACE_FPGA_FAMILY_CYCLONE1,
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PACE_FPGA_FAMILY_CYCLONE2,
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PACE_FPGA_FAMILY_CYCLONE3,
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PACE_FPGA_FAMILY_CYCLONE4,
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PACE_FPGA_FAMILY_CYCLONE5,
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PACE_FPGA_FAMILY_CYCLONE6,
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PACE_FPGA_FAMILY_STRATIX_III,
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PACE_FPGA_FAMILY_SPARTAN3,
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PACE_FPGA_FAMILY_SPARTAN3A,
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PACE_FPGA_FAMILY_SPARTAN3E
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);
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type PACEJamma_t is
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(
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PACE_JAMMA_NONE,
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PACE_JAMMA_MAPLE,
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PACE_JAMMA_NGC,
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PACE_JAMMA_PS2
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);
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-- Types
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type ByteArrayType is array (natural range <>) of std_logic_vector(7 downto 0);
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type from_CLKRST_t is record
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arst : std_logic;
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arst_n : std_logic;
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rst : std_logic_vector(0 to 3);
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clk_ref : std_logic; --reference clock
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clk : std_logic_vector(0 to 3);
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end record;
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-- maximums from the DE2 target
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constant PACE_NUM_SWITCHES : natural := 18;
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subtype from_SWITCHES_t is std_logic_vector(PACE_NUM_SWITCHES-1 downto 0);
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constant PACE_NUM_BUTTONS : natural := 4;
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subtype from_BUTTONS_t is std_logic_vector(PACE_NUM_BUTTONS-1 downto 0);
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constant PACE_NUM_LEDS : natural := 18;
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subtype to_LEDS_t is std_logic_vector(PACE_NUM_LEDS-1 downto 0);
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--
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-- JAMMA interface data structures
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-- - note: all signals are active LOW
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--
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type from_JAMMA_player_t is record
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start : std_logic;
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up : std_logic;
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down : std_logic;
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left : std_logic;
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right : std_logic;
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button : std_logic_vector(1 to 5);
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end record;
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type from_JAMMA_player_a is array (natural range <>) of from_JAMMA_player_t;
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type from_JAMMA_t is record
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coin_cnt : std_logic_vector(1 to 2);
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service : std_logic;
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tilt : std_logic;
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test : std_logic;
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coin : std_logic_vector(1 to 2);
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p : from_JAMMA_player_a(1 to 2);
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end record;
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--
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-- INPUTS
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--
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subtype analogue_in_t is std_logic_vector(9 downto 0);
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type analogue_in_a is array (natural range <>) of analogue_in_t;
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type from_INPUTS_t is record
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ps2_kclk : std_logic;
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ps2_kdat : std_logic;
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ps2_mclk : std_logic;
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ps2_mdat : std_logic;
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jamma_n : from_JAMMA_t;
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-- up to 4 10-bit analgue inputs
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analogue : analogue_in_a(1 to 4);
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end record;
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type in8_t is record
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d : std_logic_vector(7 downto 0);
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end record;
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type from_MAPPED_INPUTS_t is array (natural range <>) of in8_t;
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--
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-- SRAM interface data structure
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--
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type from_SRAM_t is record
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d : std_logic_vector(31 downto 0);
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end record;
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type to_SRAM_t is record
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a : std_logic_vector(23 downto 0);
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d : std_logic_vector(31 downto 0);
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be : std_logic_vector(3 downto 0);
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cs : std_logic;
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oe : std_logic;
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we : std_logic;
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end record;
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function NULL_TO_SRAM return to_SRAM_t;
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--
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-- FLASH interface data structure
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--
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type from_FLASH_t is record
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d : std_logic_vector(15 downto 0);
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end record;
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type to_FLASH_t is record
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a : std_logic_vector(21 downto 0);
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d : std_logic_vector(15 downto 0);
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we : std_logic;
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cs : std_logic;
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oe : std_logic;
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end record;
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function NULL_TO_FLASH return to_FLASH_t;
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type from_AUDIO_t is record
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clk : std_logic;
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end record;
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type to_AUDIO_t is record
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clk : std_logic;
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ldata : std_logic_vector(15 downto 0);
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rdata : std_logic_vector(15 downto 0);
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end record;
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function NULL_TO_AUDIO return to_AUDIO_t;
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type from_SPI_t is record
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din : std_logic;
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end record;
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type to_SPI_t is record
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clk : std_logic;
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mode : std_logic;
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sel : std_logic;
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ena : std_logic;
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dout : std_logic;
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end record;
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function NULL_TO_SPI return to_SPI_t;
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type to_SERIAL_t is record
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txd : std_logic;
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rts : std_logic;
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end record;
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function NULL_TO_SERIAL return to_SERIAL_t;
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type from_SERIAL_t is record
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dcd : std_logic;
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rxd : std_logic;
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cts : std_logic;
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end record;
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constant PACE_NUM_GPI : natural := 72;
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subtype from_GP_t is std_logic_vector(PACE_NUM_GPI-1 downto 0);
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constant PACE_NUM_GPO : natural := PACE_NUM_GPI;
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type to_GP_t is record
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d : std_logic_vector(PACE_NUM_GPO-1 downto 0);
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oe : std_logic_vector(PACE_NUM_GPO-1 downto 0);
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end record;
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function NULL_TO_GP return to_GP_t;
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subtype SND_A_t is std_logic_vector(7 downto 0);
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subtype SND_D_t is std_logic_vector(7 downto 0);
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type to_SOUND_t is record
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a : SND_A_t;
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d : SND_D_t;
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rd : std_logic;
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wr : std_logic;
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end record;
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type from_SOUND_t is record
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d : SND_D_t;
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end record;
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function NULL_TO_SOUND return to_SOUND_t;
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--
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-- OSD interface data structure
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--
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type from_OSD_t is record
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d : std_logic_vector(7 downto 0);
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end record;
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function NULL_FROM_OSD return from_OSD_t;
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type to_OSD_t is record
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en : std_logic;
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a : std_logic_vector(7 downto 0);
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d : std_logic_vector(7 downto 0);
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we : std_logic;
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end record;
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function NULL_TO_OSD return to_OSD_t;
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-- create a constant that automatically determines
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-- whether this is simulation or synthesis
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constant IN_SIMULATION : BOOLEAN := false
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-- synthesis translate_off
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or true
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-- synthesis translate_on
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;
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constant IN_SYNTHESIS : boolean := not IN_SIMULATION;
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end;
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