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48 lines
1.2 KiB
Verilog
48 lines
1.2 KiB
Verilog
module mc8051_core(
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input clk,
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input reset,
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input [7:0] rom_data_i,
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input [7:0] ram_data_i,
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input int0_i,
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input int1_i,
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input all_t0_i,
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input all_t1_i,
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input all_rxd_i,
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input [7:0] p0_i,
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input [7:0] p1_i,
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input [7:0] p2_i,
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input [7:0] p3_i,
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output [7:0] p0_o,
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output [7:0] p1_o,
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output [7:0] p2_o,
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output [7:0] p3_o,
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output all_rxd_o,
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output all_txd_o,
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output all_rxdwr_o,
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output [15:0] rom_adr_o,
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output [ 7:0] ram_data_o,
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output [ 6:0] ram_adr_o,
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output ram_wr_o,
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output ram_en_o,
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input [ 7:0] datax_i,
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output [ 7:0] datax_o,
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output [15:0] adrx_o,
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output wrx_o
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);
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assign rom_adr_o = 16'd0;
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assign ram_en_o = 1'b0;
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assign ram_wr_o = 1'b0;
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assign datax_o = 8'd0;
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assign adrx_o = 16'd0;
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assign p0_o = 8'd0;
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assign p1_o = 8'd0;
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assign p2_o = 8'd0;
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assign p3_o = 8'h20;
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assign all_rxd_o = 1'b0;
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assign all_txd_o = 1'b0;
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assign all_rxdwr_o = 1'b0;
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endmodule // mc8051_core
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