mirror of
https://github.com/Gehstock/Mist_FPGA.git
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441 lines
12 KiB
Verilog
441 lines
12 KiB
Verilog
/* This file is part of JT51.
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JT51 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT51 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT51. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 27-10-2016
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*/
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`timescale 1ns / 1ps
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module jt51_eg(
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`ifdef TEST_SUPPORT
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input test_eg,
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`endif
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input rst,
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input clk,
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input cen,
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input zero,
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// envelope configuration
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input [4:0] keycode_III,
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input [4:0] arate_II,
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input [4:0] rate1_II,
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input [4:0] rate2_II,
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input [3:0] rrate_II,
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input [3:0] d1l_I,
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input [1:0] ks_III,
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// envelope operation
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input keyon_II,
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output reg pg_rst_III,
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// envelope number
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input [6:0] tl_VII,
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input [6:0] am,
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input [1:0] ams_VII,
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input amsen_VII,
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output [9:0] eg_XI
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);
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// eg[9:6] -> direct attenuation (divide by 2)
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// eg[5:0] -> mantisa attenuation (uses LUT)
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// 1 LSB of eg is -0.09257 dB
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localparam ATTACK=2'd0,
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DECAY1=2'd1,
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DECAY2=2'd2,
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RELEASE=2'd3;
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reg [4:0] d1level_II;
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reg [2:0] cnt_V;
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reg [5:0] rate_IV;
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wire [9:0] eg_VI;
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reg [9:0] eg_VII, eg_VIII;
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wire [9:0] eg_II;
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reg [11:0] sum_eg_tl_VII;
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reg step_V, step_VI;
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reg sum_up;
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reg [5:0] rate_V;
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reg [5:1] rate_VI;
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// remember: { log_msb, pow_addr } <= log_val[11:0] + { tl, 5'd0 } + { eg, 2'd0 };
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reg [1:0] eg_cnt_base;
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reg [14:0] eg_cnt /*verilator public*/;
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reg [8:0] am_final_VII;
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always @(posedge clk) begin : envelope_counter
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if( rst ) begin
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eg_cnt_base <= 2'd0;
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eg_cnt <=15'd0;
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end
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else if(cen) begin
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if( zero ) begin
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// envelope counter increases every 3 output samples,
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// there is one sample every 32 clock ticks
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if( eg_cnt_base == 2'd2 ) begin
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eg_cnt <= eg_cnt + 1'b1;
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eg_cnt_base <= 2'd0;
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end
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else eg_cnt_base <= eg_cnt_base + 1'b1;
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end
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end
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end
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wire cnt_out; // = all_cnt_last[3*31-1:3*30];
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reg [6:0] pre_rate_III;
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reg [4:0] cfg_III;
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always @(*) begin : pre_rate_calc
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if( cfg_III == 5'd0 )
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pre_rate_III = 7'd0;
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else
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case( ks_III )
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2'd3: pre_rate_III = { 1'b0, cfg_III, 1'b0 } + { 2'b0, keycode_III };
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2'd2: pre_rate_III = { 1'b0, cfg_III, 1'b0 } + { 3'b0, keycode_III[4:1] };
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2'd1: pre_rate_III = { 1'b0, cfg_III, 1'b0 } + { 4'b0, keycode_III[4:2] };
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2'd0: pre_rate_III = { 1'b0, cfg_III, 1'b0 } + { 5'b0, keycode_III[4:3] };
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endcase
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end
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reg [7:0] step_idx;
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reg [1:0] state_in_III, state_in_IV, state_in_V, state_in_VI;
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always @(*) begin : rate_step
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if( rate_V[5:4]==2'b11 ) begin // 0 means 1x, 1 means 2x
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if( rate_V[5:2]==4'hf && state_in_V == ATTACK)
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step_idx = 8'b11111111; // Maximum attack speed, rates 60&61
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else
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case( rate_V[1:0] )
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2'd0: step_idx = 8'b00000000;
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2'd1: step_idx = 8'b10001000; // 2
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2'd2: step_idx = 8'b10101010; // 4
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2'd3: step_idx = 8'b11101110; // 6
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endcase
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end
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else begin
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if( rate_V[5:2]==4'd0 && state_in_V != ATTACK)
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step_idx = 8'b11111110; // limit slowest decay rate_IV
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else
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case( rate_V[1:0] )
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2'd0: step_idx = 8'b10101010; // 4
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2'd1: step_idx = 8'b11101010; // 5
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2'd2: step_idx = 8'b11101110; // 6
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2'd3: step_idx = 8'b11111110; // 7
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endcase
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end
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// a rate_IV of zero keeps the level still
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step_V = rate_V[5:1]==5'd0 ? 1'b0 : step_idx[ cnt_V ];
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end
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wire ar_off_VI;
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always @(posedge clk) if(cen) begin
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// I
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if( d1l_I == 4'd15 )
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d1level_II <= 5'h10; // 48dB
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else
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d1level_II <= {1'b0,d1l_I};
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end
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// II
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wire keyon_last_II;
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wire keyon_now_II = !keyon_last_II && keyon_II;
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wire keyoff_now_II = keyon_last_II && !keyon_II;
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wire ar_off_II = keyon_now_II && (arate_II == 5'h1f);
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wire [1:0] state_II;
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always @(posedge clk) if(cen) begin
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pg_rst_III <= keyon_now_II;
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// trigger release
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if( keyoff_now_II ) begin
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cfg_III <= { rrate_II, 1'b1 };
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state_in_III <= RELEASE;
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end
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else begin
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// trigger 1st decay
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if( keyon_now_II ) begin
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cfg_III <= arate_II;
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state_in_III <= ATTACK;
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end
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else begin : sel_rate
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case ( state_II )
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ATTACK: begin
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if( eg_II==10'd0 ) begin
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state_in_III <= DECAY1;
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cfg_III <= rate1_II;
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end
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else begin
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state_in_III <= state_II; // attack
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cfg_III <= arate_II;
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end
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end
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DECAY1: begin
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if( eg_II[9:5] >= d1level_II ) begin
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cfg_III <= rate2_II;
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state_in_III <= DECAY2;
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end
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else begin
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cfg_III <= rate1_II;
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state_in_III <= state_II; // decay1
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end
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end
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DECAY2: begin
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cfg_III <= rate2_II;
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state_in_III <= state_II; // decay2
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end
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RELEASE: begin
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cfg_III <= { rrate_II, 1'b1 };
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state_in_III <= state_II; // release
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end
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endcase
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end
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end
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end
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// III
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always @(posedge clk) if(cen) begin
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state_in_IV <= state_in_III;
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rate_IV <= pre_rate_III[6] ? 6'd63 : pre_rate_III[5:0];
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end
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// IV
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always @(posedge clk) if(cen) begin
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state_in_V <= state_in_IV;
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rate_V <= rate_IV;
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if( state_in_IV == ATTACK )
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case( rate_IV[5:2] )
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4'h0: cnt_V <= eg_cnt[13:11];
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4'h1: cnt_V <= eg_cnt[12:10];
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4'h2: cnt_V <= eg_cnt[11: 9];
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4'h3: cnt_V <= eg_cnt[10: 8];
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4'h4: cnt_V <= eg_cnt[ 9: 7];
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4'h5: cnt_V <= eg_cnt[ 8: 6];
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4'h6: cnt_V <= eg_cnt[ 7: 5];
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4'h7: cnt_V <= eg_cnt[ 6: 4];
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4'h8: cnt_V <= eg_cnt[ 5: 3];
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4'h9: cnt_V <= eg_cnt[ 4: 2];
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4'ha: cnt_V <= eg_cnt[ 3: 1];
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default: cnt_V <= eg_cnt[ 2: 0];
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endcase
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else
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case( rate_IV[5:2] )
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4'h0: cnt_V <= eg_cnt[14:12];
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4'h1: cnt_V <= eg_cnt[13:11];
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4'h2: cnt_V <= eg_cnt[12:10];
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4'h3: cnt_V <= eg_cnt[11: 9];
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4'h4: cnt_V <= eg_cnt[10: 8];
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4'h5: cnt_V <= eg_cnt[ 9: 7];
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4'h6: cnt_V <= eg_cnt[ 8: 6];
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4'h7: cnt_V <= eg_cnt[ 7: 5];
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4'h8: cnt_V <= eg_cnt[ 6: 4];
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4'h9: cnt_V <= eg_cnt[ 5: 3];
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4'ha: cnt_V <= eg_cnt[ 4: 2];
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4'hb: cnt_V <= eg_cnt[ 3: 1];
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default: cnt_V <= eg_cnt[ 2: 0];
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endcase
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end
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// V
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always @(posedge clk) if(cen) begin
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state_in_VI <= state_in_V;
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rate_VI <= rate_V[5:1];
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sum_up <= cnt_V[0] != cnt_out;
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step_VI <= step_V;
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end
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///////////////////////////////////////
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// VI
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reg [8:0] ar_sum0_VI;
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reg [9:0] ar_result_VI, ar_sum_VI;
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always @(*) begin : ar_calculation
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casez( rate_VI[5:2] )
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default: ar_sum0_VI = { 3'd0, eg_VI[9:4] } + 9'd1;
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4'b1100: ar_sum0_VI = { 3'd0, eg_VI[9:4] } + 9'd1;
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4'b1101: ar_sum0_VI = { 2'd0, eg_VI[9:3] } + 9'd1;
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4'b111?: ar_sum0_VI = { 1'd0, eg_VI[9:2] } + 9'd1;
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endcase
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if( rate_VI[5:4] == 2'b11 )
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ar_sum_VI = step_VI ? { ar_sum0_VI, 1'b0 } : { 1'b0, ar_sum0_VI };
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else
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ar_sum_VI = step_VI ? { 1'b0, ar_sum0_VI } : 10'd0;
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ar_result_VI = ar_sum_VI<eg_VI ? eg_VI-ar_sum_VI : 10'd0;
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end
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always @(posedge clk) if(cen) begin
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if( ar_off_VI )
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eg_VII <= 10'd0;
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else
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if( state_in_VI == ATTACK ) begin
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if( sum_up && eg_VI != 10'd0 )
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if( rate_VI[5:1]==5'hf )
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eg_VII <= 10'd0;
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else
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eg_VII <= ar_result_VI;
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else
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eg_VII <= eg_VI;
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end
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else begin : DECAY_SUM
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if( sum_up ) begin
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if ( eg_VI<= (10'd1023-10'd8) )
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case( rate_VI[5:2] )
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4'b1100: eg_VII <= eg_VI + { 8'd0, step_VI, ~step_VI }; // 12
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4'b1101: eg_VII <= eg_VI + { 7'd0, step_VI, ~step_VI, 1'b0 }; // 13
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4'b1110: eg_VII <= eg_VI + { 6'd0, step_VI, ~step_VI, 2'b0 }; // 14
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4'b1111: eg_VII <= eg_VI + 10'd8;// 15
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default: eg_VII <= eg_VI + { 8'd0, step_VI, 1'b0 };
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endcase
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else eg_VII <= 10'h3FF;
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end
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else eg_VII <= eg_VI;
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end
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end
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// VII
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always @(*) begin : sum_eg_and_tl
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casez( {amsen_VII, ams_VII } )
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3'b0??,3'b100: am_final_VII = 9'd0;
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3'b101: am_final_VII = { 2'b00, am };
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3'b110: am_final_VII = { 1'b0, am, 1'b0};
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3'b111: am_final_VII = { am, 2'b0 };
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endcase
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`ifdef TEST_SUPPORT
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if( test_eg && tl_VII!=7'd0 )
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sum_eg_tl_VII = 12'd0;
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else
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`endif
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sum_eg_tl_VII = { 2'b0, tl_VII, 3'd0 }
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+ {2'b0, eg_VII}
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+ {2'b0, am_final_VII, 1'b0 };
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end
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always @(posedge clk) if(cen) begin
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eg_VIII <= sum_eg_tl_VII[11:10] > 2'b0 ? {10{1'b1}} : sum_eg_tl_VII[9:0];
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end
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jt51_sh #( .width(10), .stages(3) ) u_egpadding (
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.rst ( rst ),
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.clk ( clk ),
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.cen ( cen ),
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.din ( eg_VIII ),
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.drop ( eg_XI )
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);
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// Shift registers
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jt51_sh #( .width(10), .stages(32-7+2), .rstval(1'b1) ) u_eg1sh(
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.rst ( rst ),
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.clk ( clk ),
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.cen ( cen ),
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.din ( eg_VII ),
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.drop ( eg_II )
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);
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jt51_sh #( .width(10), .stages(4), .rstval(1'b1) ) u_eg2sh(
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.rst ( rst ),
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.clk ( clk ),
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.cen ( cen ),
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.din ( eg_II ),
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.drop ( eg_VI )
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);
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jt51_sh #( .width(1), .stages(4) ) u_aroffsh(
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.rst ( rst ),
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.clk ( clk ),
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.cen ( cen ),
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.din ( ar_off_II ),
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.drop ( ar_off_VI )
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);
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jt51_sh #( .width(1), .stages(32) ) u_konsh(
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.rst ( rst ),
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.clk ( clk ),
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.din ( keyon_II ),
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.cen ( cen ),
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.drop ( keyon_last_II )
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);
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jt51_sh #( .width(1), .stages(32) ) u_cntsh(
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.rst ( rst ),
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.clk ( clk ),
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.cen ( cen ),
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.din ( cnt_V[0] ),
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.drop ( cnt_out )
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);
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jt51_sh #( .width(2), .stages(32-3+2), .rstval(1'b1) ) u_statesh(
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.rst ( rst ),
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.clk ( clk ),
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.cen ( cen ),
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.din ( state_in_III ),
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.drop ( state_II )
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);
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`ifndef JT51_NODEBUG
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`ifdef SIMULATION
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/* verilator lint_off PINMISSING */
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wire [4:0] cnt;
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sep32_cnt u_sep32_cnt (.clk(clk), .cen(cen), .zero(zero), .cnt(cnt));
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sep32 #(.width(10),.stg(11)) sep_eg(
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.clk ( clk ),
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.cen ( cen ),
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.mixed ( eg_XI ),
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.cnt ( cnt )
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);
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sep32 #(.width(7),.stg(7)) sep_tl(
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.clk ( clk ),
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.cen ( cen ),
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.mixed ( tl_VII ),
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.cnt ( cnt )
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);
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sep32 #(.width(2),.stg(2)) sep_state(
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.clk ( clk ),
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.cen ( cen ),
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.mixed ( state_II ),
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.cnt ( cnt )
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);
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sep32 #(.width(5),.stg(6)) sep_rate(
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.clk ( clk ),
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.mixed ( rate_VI ),
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.cnt ( cnt )
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);
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sep32 #(.width(9),.stg(7)) sep_amfinal(
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.clk ( clk ),
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.cen ( cen ),
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.mixed ( am_final_VII ),
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.cnt ( cnt )
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);
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/* verilator lint_on PINMISSING */
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`endif
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`endif
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endmodule
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