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https://github.com/Gehstock/Mist_FPGA.git
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39 lines
2.0 KiB
VHDL
39 lines
2.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all,ieee.numeric_std.all;
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entity sp_palette is
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port (
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clk : in std_logic;
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addr : in std_logic_vector(7 downto 0);
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data : out std_logic_vector(7 downto 0)
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);
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end entity;
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architecture prom of sp_palette is
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type rom is array(0 to 255) of std_logic_vector(7 downto 0);
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signal rom_data: rom := (
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X"0F",X"08",X"0E",X"02",X"0F",X"05",X"0B",X"0C",X"0F",X"00",X"0B",X"01",X"0F",X"01",X"0B",X"02",
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X"0F",X"08",X"0D",X"02",X"0F",X"06",X"01",X"04",X"0F",X"09",X"01",X"05",X"0F",X"07",X"0B",X"01",
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X"0F",X"01",X"06",X"0B",X"0F",X"01",X"0B",X"00",X"0F",X"01",X"02",X"00",X"0F",X"00",X"01",X"06",
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X"0F",X"00",X"00",X"06",X"0F",X"03",X"0B",X"09",X"0F",X"06",X"02",X"00",X"00",X"00",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
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begin
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process(clk)
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begin
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if rising_edge(clk) then
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data <= rom_data(to_integer(unsigned(addr)));
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end if;
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end process;
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end architecture;
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